DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 05/18/2026.
Claims 1-3, 5-7, 10-17, 19 and 21-23 are presented for further examination.
Response to Arguments
Applicant’s argument: Ramanujan fails to teach and render obvious the idea of a portion serving as DRAM being system visible and a different portion serving as DRAM being transparent. For example, Ramanujan at [0176] describes that non-volatile memory (e.g., system memory) is distinct from DRAM-based near memory, but Ramanujan is silent on non-volatile memory serving as DRAM.
Applicant’s arguments have been fully considered but are not persuasive.
Applicant argues that Ramanujan fails to teach a portion of DRAM that is system visible and a different portion of DRAM that operates transparently.
Contrary to this assertion, Ramanujan expressly teaches that the near memory—which may be DRAM (Ramanujan, [0061], [0138])—is partitionable such that different partitions concurrently operate in different modes (Ramanujan, [0069]). In a hybrid mode, portions of the near memory are exposed to software for direct use and are directly addressable within the system address space, while the remaining portion operates as an MSC cache and does not form part of the system address space. Ramanujan, [0161]; see also [0066], [0070]-[0071], [0076], [0185], [0204]-[0207]. Thus, Ramanujan expressly teaches both a system-visible portion of DRAM and a software-transparent cache portion of the DRAM.
Applicant’s additional assertion that Ramanujan is silent regarding nonvolatile memory “serving as DRAM” is not commensurate with the scope of claim 1 because claim 1 does not require the persistent memory to be DRAM. Rather, claim 1 recites that the persistent memory “extends” the DRAM. Ramanujan teaches that NVRAM supplements traditional DRAM as system memory (Ramanujan, [0091]), that the bulk of DRAM system memory may be replaced by higher-capacity PCM (Ramanujan, [0135]), and that memory allocations may be divided between a small, high-performance near-memory region and a lower-performance bulk far-memory region (Ramanujan, [0161]). Accordingly, Ramanujan teaches persistent memory extending the system-memory capacity provided by DRAM.
Ramanujan [0176] does not limit Ramanujan’s disclosure to an arrangement in which all DRAM is transparent. Paragraph [0176] introduces one two-level configuration; Ramanujan thereafter expressly describes direct-access and hybrid configurations in which portions of the DRAM are system visible. Applicant’s argument therefore does not overcome the rejection.
Claim Rejections - 35 USC § 103
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5-7, 10-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ramanujan et al. (US 2014/0304475; hereinafter Ramanujan) in view of Li et al. (US 2019/0138448; hereinafter Li).
Regarding independent claims 1, 10 and 15, taking claim 1 as exemplary analysis, Ramanujan teaches A semiconductor apparatus (Fig. 4, semiconductor apparatus; Fig. 1, storage device with two-level memory hierarchy; [0291], a non-transitory computer readable medium) comprising: a host interface implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the host interface to receive a request from a host application to allocate memory address space for a buffer (Fig. 7A, Software 750 interface with MSC controller 512; [0219], Software 750 identifies a specific portion of the cache 740 to be de-activated or re-activated; [0066], the cache memories 101 a-109 may operate transparently to the software …the cores may also support execution of instructions to allow software to provide some control (configuration, policies, hints, etc.) to some or all of the cache(s)); and a memory controller to: map, via a memory controller, cached data allocate the memory address space in a dynamic random access memory that acts as a transparent cache for a persistent memory, including to map data in the buffer to an original address of copied data in a persistent memory, wherein the memory controller includes a two level memory controller mode that uses the dynamic random access memory as a transparent cache for the persistent memory (
Figs. 7A, 7B; Fig. 5; [0152], allows the near memory address to be directly extracted from the system memory address; [0091], NVRAM 142 represents the introduction of a second-level system memory (e.g., the system memory may be viewed as having a first level system memory comprising near memory as cache 150B (part of the DRAM device 340) and a second level system memory comprising far memory (FM) 151B (part of the NVRAM 142); [0176], a two-level memory hierarchy may be used for introducing fast non-volatile memory such as PCM as system memory while using a very large DRAM-based near memory; [0214], a two-level memory hierarchy with a MSC which includes a flush engine that (1) evicts dirty cache lines and invalidate them in a specified manner (although the underlying principles of the invention may be used in the context of any multi-level memory hierarchy); (2) monitors cache usage dynamically; (3) allows software to specify a power management policy; and (4) de-activates specified portions of the volatile-memory based MSC);
track, via the memory controller, whether the cached data in the dynamic random access memory is valid or track the memory address space as invalid data with respect to the copied data in the persistent memory (Fig. 5A-5E; [0149]-[0152], a 3-Byte (24-bit) tag 522 is used with the bit assignments illustrated in FIG. 5D…bits 21-22 indicate the current state of the cache line (e.g., 00=clean; 01=dirty; 10 and 11=unused); and bit 23 indicates whether the cache line is valid (e.g., 1=valid; 0=invalid); [0153], a dirty line tag cache that maintains the tags of recently-accessed near memory addresses (NMAs). Since many writes target recently accessed addresses, a reasonably small tag cache can get an effective hit rate to filter most of the reads prior to a write)
Ramanujan teaches write back dirty and valid data to the persistent memory when the cached data is tracked as invalid data, and Ramanujan teaches evict, via the memory controller, the cached data from the dynamic random access memory ([0192], A flush engine to evict dirty lines to PCM and invalidate in specified regions of the near memory address space);
Ramanujan does not teach bypass a writeback of dirty but invalid data.
In an analogous art of cache management, Li teaches
in response to an indication via the host interface that the data in the buffer is invalid (
[0039], FIG. 6 illustrates an embodiment of a read-with-invalidate (RWI) command 600 triggered by the driver 121 to invalidate data in cache lines stored in the cache memory 114. The RWI command 600 includes an RWI opcode 602 identifying an RWI command to the 2LM controller 110, a target address 604 having data to read and invalidate, and a portion 606 of the target address 604 to read and invalidate...user defined bus signals for a cache operation may use one of the encoding of the signals to identify the cache operation as an RWI command. When the driver 121 sends a read command onto the bus 112 {host interface}, the driver 121 may also assert the RWI signal together with the transaction; [0040], FIG. 7 illustrates an embodiment of operations performed by the 2LM controller 110 to process a read-with-invalidate (RWI) command 600 received from one of the components 104, 106, 108 that is reading locally used and modified data for the last time that is now ready to be discarded without needing to be further saved); and
evict, via the memory controller, the cached data from the dynamic random access memory ([0021], The 2LM controller 110, also on the SoC 102, stores cache lines for addresses in a cache memory 114, also referred to as a near memory or first memory. Modified data in cache lines evicted from the cache memory 114 to make room for new data are copied to a non-volatile memory 116); and
bypass, via the memory controller, a bypass a writeback to the persistent memory of the cached data that has been evicted to the persistent in the buffer in response to an eviction of the buffer from the dynamic random access memory when the cached data memory address space is tracked as invalid data (
[0022], This invalidation of the portion of the data prevents the data in the cache line from being copied to the non-volatile memory 116. In this way, the 2LM controller 110 frees a cache line in the cache memory 114 to make room for new data without having to flush the modified cache line to the non-volatile (far) memory 116;
[0049], With the embodiment of FIG. 8, a cache line having all portions invalidated, such as through an RWI command 600 or other process, that also has modified/dirty data, is removed from cache, such as when selected to cache data for another address according to an associative caching algorithm, without copying to the non-volatile memory 116. The modified data for the cache line does not need to be copied and preserved in the non-volatile memory 116 because all portions of the cache line have been invalidated by the process that stored the data in the cache memory 114 for local use during processing operations. Discarding modified data without copying to the non-volatile memory 116, which will not be needed by future processes, minimizes writing and reading operations to the non-volatile memory 116 to avoid wear and extend the life of the non-volatile memory 116, which is particularly important for non-volatile memory devices that experience usage wear leveling).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention was made, with the teachings of Ramanujan and Li before them, to incorporate Li’s discarding modified data without copying to the non-volatile memory 116, which will not be needed by future processes for the motivation of minimizes writing and reading operations to the non-volatile memory to avoid wear and extend the life of the non-volatile memory, which is particularly important for non-volatile memory devices that experience usage wear leveling (Li, [0016], [0049]).
Ramanujan further teaches wherein the persistent memory extends the dynamic random access memory ([0036], divides memory requirements between a relatively small amount of higher-speed DRAM and bulk system memory implemented using NVRAM; [0067]-[0070], system-memory address space includes both near memory configured as system memory and NVRAM system memory; [0091], NVRAM acts as a supplement for traditional DRAM technology in system memory; [0135], the bulk of DRAM in system memory is replaced with PCM to provide increased memory capacity; [0161], applications split memory allocation between a small, high-performance near-memory region and a lower-performance bulk far-memory region); wherein the dynamic random access memory is system visible ([0061], [0138], the near memory may comprise DRAM; [0066], system memory is visible to and/or directly addressable by software; [0069], the near memory is partitionable such that different partitions concurrently operate in different modes, including a system-memory direct-access mode; [0070], a portion of near memory is assigned a portion of the system address space; [0076], all or portions of near memory operating in direct-access mode are directly visible to software and form part of the system physical address space; [0161], portions of the near memory are exposed to software for direct use and are directly addressable within the system address space, while the remaining portion operates as a transparent MSC cache; also see Fig. 9A & [0279]); and wherein the persistent memory has a write bandwidth that is lower than and a storage capacity that is larger than the dynamic random access memory (Fig. 4A and [0115]- [0116], DRAM devices 403-406 are connected to processor 310 through on-package high-bandwidth links 407, whereas PCM DIMMs 450-451 acting as far memory communicate through DDR bus/channels 440; [0061] & [0063], DRAM-based near memory has significantly lower write latency than the far memory; [0135], PCM exhibits asymmetric read-versus-write performance; [0140], the DRAM-based MSC absorbs, coalesces, and filters write transactions directed to PCM; [0143], the DRAM-based MSC may be one-tenth the size of the PCM far memory, e.g., a 16 GB DRAM MSC for a 128 GB PCM far memory). Li further confirms that, in a two-level memory system, DRAM is used as the faster near memory for a larger, slower-access nonvolatile far memory and that the nonvolatile memory has a larger capacity than the DRAM cache memory (Li, [0002], [0015], [0021]).
Regarding claim(s) 2, 11 and 16, the combination of Ramanujan and Li further teaches the memory controller further to: receive a free buffer command from the host application indicating that the data in the buffer is invalid data (Ramanujan, [0263], software 850 can command the flush engine 701 to invalidate “zero” or “discarded” pages from the MSC 510; Li, [0022], Upon reading such local data for a last time, the component 104, 106, 108 hardware may issue a read-with-invalidate (RWI) command to the cache line or a portion of the cache line having the data being read for the last time to cause that portion of the data in the cache line to be invalidated after being read), and
wherein the memory controller is to track the memory address space as invalid data [[is]] based on the received free buffer command (Li, [0022], The 2LM controller 110 includes a tag table 200 having information on addresses of data stored in cache lines in the cache memory 114, e.g., address, valid bit, dirty bit, etc., and a read-with-invalidate (RWI) table 300 having entries for some or all of the cache lines in the cache memory 114 that indicates whether portions of data in a cache line have valid data...Upon reading such local data for a last time, the component 104, 106, 108 hardware may issue a read-with-invalidate (RWI) command to the cache line or a portion of the cache line having the data being read for the last time to cause that portion of the data in the cache line to be invalidated after being read...This invalidation of the portion of the data prevents the data in the cache line from being copied to the non-volatile memory 116).
Regarding claim(s) 3, the combination of Ramanujan and Li further teaches wherein the operation to track the cached data as valid or invalid includes an operation to mark, via the memory controller, the cached data as valid or memory address space as invalid and comprises the memory controller to mark the memory address space as dirty or clean, wherein the operation to bypass the writeback of the cached data is performed is in response to the cached data is memory address space being marked as dirty but invalid (Li, [0022], The 2LM controller 110 includes a tag table 200 having information on addresses of data stored in cache lines in the cache memory 114, e.g., address, valid bit, dirty bit, etc., and a read-with-invalidate (RWI) table 300 having entries for some or all of the cache lines in the cache memory 114 that indicates whether portions of data in a cache line have valid data...Upon reading such local data for a last time, the component 104, 106, 108 hardware may issue a read-with-invalidate (RWI) command to the cache line or a portion of the cache line having the data being read for the last time to cause that portion of the data in the cache line to be invalidated after being read...This invalidation of the portion of the data prevents the data in the cache line from being copied to the non-volatile memory 116).
Regarding claim(s) 5, the combination of Ramanujan and Li further teaches wherein the operation memory controller is to mark the cached data memory address space as dirty but invalid based on one or more of the following events: a deallocation of data during an iteration of machine learning training, upon a system shutdown, and a closing of the active host application (Ramanujan, [0264]-[0265], when the power fail detector unit 830 detects a power fail state and generates a warning to the flush engine 701, the following sequence occurs: the flush engine 701 is triggered to start sequentially traversing the MSC 510 for dirty lines;
Li, [0049], a cache line having all portions invalidated, such as through an RWI command 600 or other process, that also has modified/dirty data, is removed from cache, such as when selected to cache data for another address according to an associative caching algorithm, without copying to the non-volatile memory 116. The modified data {dirty data} for the cache line does not need to be copied and preserved in the non-volatile memory 116 because all portions of the cache line have been invalidated by the process that stored the data in the cache memory 114 for local use during processing operations).
Regarding claim(s) 12 and 17, the combination of Ramanujan and Li further teaches wherein … (Claim recites substantially the same limitations as in claims 3 and 5, is therefore rejected for the same reasons set forth in the analysis of claims 3 and 5).
Regarding claim(s) 6 and 13, the combination of Ramanujan and Li further teaches perform writeback to the persistent memory of the data in the buffer in response to an eviction of the buffer from the dynamic random access memory when the memory address space is marked as dirty and valid data (Li, [0045], if (at block 806) not all portion indicators 506 1, 506 2 . . . 506 n in the tag 500 i for the selected cache line having modified data are set to invalid, then the cache line, including portions of data marked invalid, is copied (at block 812) to the non-volatile memory 116. If (at block 804) the selected cache line does not have modified/dirty data, then the data for the target address is written (at block 814) to the selected cache line in the cache memory 114).
Regarding claim(s) 7 and 19, the combination of Ramanujan and Li further teaches wherein the memory address space marked as dirty stores data including one or more of: duplicate data, outdated data, insecure data, incorrect data, incomplete data, and inconsistent data (Ramanujan, [0279], “dirty”—i.e., a modified state that is no longer reflected in the copy stored in PCM 530; Li, [0032], a dirty bit 204 indicating whether the cache line corresponding to the tag entry 200 i has modified data; and a valid bit 206 indicating whether the cache line has valid data.).
Regarding claim(s) 14, the combination of Ramanujan and Li further teaches wherein … (Claim recites substantially the same limitations as in claims 7 and 9, is therefore rejected for the same reasons set forth in the analysis of claims 7 and 9).
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ramanujan et al. (US 2014/0304475; hereinafter Ramanujan) in view of Li et al. (US 2019/0138448; hereinafter Li), further in view of Hsia (US 2013/0054925).
Regarding claim(s) 21, 22 and 23, the combination of Ramanujan and Li teaches host application indicating that the data in the buffer is invalid data, and wherein the memory controller is to track the memory address space as invalid data based on the received application command (Li, [0017], To allow communication of such an invalidation of data upon last read access, described embodiments provide a read-with-invalidate (RWI) command to read and invalidate at least one portion of a plurality of portions of a cache line having modified data. When the cache line having modified data is selected for replacement, the modified data is not copied to the non-volatile (far) memory if portions (some or all) of the cache line being flushed have been invalidated with the (RWI) command).
Although Li teaches using host API to indicate invalid memory, Ramanujan and Li do not expressly teach a free buffer command received during a garbage collection routine. In an analogous art of memory management, Hsia teaches a free buffer command received during a garbage collection routine ([0056], the memory allocation command and the memory free command can be received as explicit instructions from the at least one process. Alternatively, at reference numeral 908, the memory free command and/or the memory allocation command can be received in connection with a system-managed garbage collection routine. In the latter case discussed with regard to reference numeral 908, then at reference numeral 910, the tag can be updated in response to a change in a memory allocation reference provided by the system-managed garbage collection routine; [0046], rather than expecting a corresponding memory release call, such can be managed by, e.g., a garbage collection operation or algorithm or another managed process, denoted as garbage collection process 208. In the case of managed operations such as garbage collection routines, intercept component 102 can subsequently intercept an associated memory release call (e.g., GC Start 210, GC Finish 212, . . . ) explicitly called by garbage collection process 208).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention was made, with the teachings of Hsia, Ramanujan and Li before them, to incorporate Hsia’s explicit memory free command provided by garbage collection routine to invalidate memory for the motivation that bypass writeback could be utilized during garbage collection to reduce un-necessary writeback during garbage collection.
Thus, the combination of Ramanujan, Li and Hsia teaches receive a free buffer command from a host operating system during a garbage collection routine indicating that the data in the buffer is invalid data, and wherein the memory controller is to track the memory address space as invalid data based on the received free buffer command.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TRACY C CHAN/ Primary Examiner, Art Unit 2138
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