DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed on 07/22/2025 with respect to claims 1, 10, 14 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Takizawa (US Patent No. 6952027).
Regarding claim 1, Takizawa discloses an electrostatic discharge (ESD) protection apparatus (fig. 22, Col. 14 lines 52+) comprising: a first diode (P12) with a first side (cathode) and a second side (anode) opposite the first side (cathode), the first side (cathode) of the first diode (P12) electrically coupled with a voltage drain drain (Vdd) (Vcc); a second diode (N12) with a first side (cathode) and a second side (anode) opposite the first side (cathode), the second side (anode) of the second diode (N12) electrically coupled with a voltage source source (Vss) (GND); an electrical pad (PAD); an electrical circuit protected by the ESD apparatus (300, fig. 44, Col. 22 lines 54+), the circuit (300) electrically coupled with the second side (anode) of the first diode (P12), the first side (cathode) of the second diode (N12), and the electrical pad (PAD); and wherein the first diode (P12) and the second diode (N12) are in a metal layer (128) above a transistor layer (140), the metal layer (128) vertically spaced apart (i.e., 1st metal layer 128 and 2nd metal layer 140 are distant) from the transistor layer (140).
Regarding claim 2, Takizawa discloses the apparatus (fig. 22, Col. 14 lines 52+), wherein the first side (cathode) of the first diode (P12) and the first side (cathode) of the second diode (N12) are cathode sides, and wherein the second side (anode) of the first diode (P12) and the second side (anode) of the second diode (N12) are anode sides.
Regarding claim 3, Takizawa discloses the apparatus (fig. 22, Col. 14 lines 52+), wherein the electrical circuit includes a plurality of transistors (PFET, NFET).
Regarding claim 4, Takizawa discloses the apparatus (fig. 22, Col. 14 lines 52+), wherein the first diode (P12) and the second diode (N12) are metal-semiconductor-metal (MSM) diodes (i.e., implicit as a 1st metal layer 128 and a 2nd metal layer 140, also each diode in the ESD circuit is a MOS scheme).
Regarding claim 5, Takizawa discloses the apparatus (fig. 22, Col. 14 lines 52+), wherein the first diode (P12) and the second diode (N12) include a selected one or more of: titanium, nickel, or amorphous silicon (i.e., such as metal, silicide, electrically conductive polysilicon, etc.).
Regarding claim 6, Takizawa discloses the apparatus (fig. 22, Col. 14 lines 52+), wherein the first diode (P12) and the second diode (N12) include a via or plug connection (i.e., such as 134, fig. 17, Col. 12 lines 61+).
Regarding claim 7, Takizawa discloses the apparatus (fig. 22, Col. 14 lines 52+), wherein the electrical pad (PAD) is an input/output (I/O) pad (PAD).
Regarding claim 8, Takizawa discloses the apparatus (fig. 22, Col. 14 lines 52+), wherein at least a portion of the electrical circuit (i.e., such Vcc, GND, etc.) is in a portion (104) of the substrate (P, i.e., implicit as seen in fig. 17, Col. 12 lines 61+).
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Regarding claim 9, Takizawa discloses the apparatus (fig. 22, Col. 14 lines 52+), wherein the portion (104) of the substrate (P) is a front end of line (FEOL) portion of the substrate (P, i.e., implicit as seen in fig. 17, Col. 12 lines 61+).
Regarding claim 10, Takizawa discloses a method (fig. 22, Col. 14 lines 52+) comprising: forming a first diode (P12) and a second diode (N12) in a metal layer (128) above a transistor layer (140), the metal layer (128) vertically spaced apart (i.e., 1st metal layer 128 and 2nd metal layer 140 are distant) from the transistor layer (140) electrically coupling an anode of the first diode (P12) with a cathode of the second diode (N12); electrically coupling an input/output (I/O) pad (PAD) with the anode of the first diode (P12); electrically coupling a cathode of the first diode (P12) to a Vdd (Vcc); and electrically coupling an anode of the second diode (N12) to a Vss (GND).
Regarding claim 11, Takizawa discloses the method (fig. 22, Col. 14 lines 52+), further comprising electrically coupling an electrical circuit (300, fig. 44, Col. 22 lines 54+) to the anode of the first diode (P12) and a cathode of the second diode (N12).
Regarding claim 12, Takizawa discloses the method (fig. 22, Col. 14 lines 52+), wherein the first diode (P12) and the second diode (N12) are metal-semiconductor-metal (MSM) diodes (i.e., implicit as a 1st metal layer 128 and a 2nd metal layer 140, also each diode in the ESD circuit is a MOS scheme).
Regarding claim 13, Takizawa discloses the method (fig. 22, Col. 14 lines 52+), wherein the first diode (P12) and the second diode (N12) include a selected one or more of: titanium, nickel, or amorphous silicon (i.e., such as metal, silicide, electrically conductive polysilicon, etc.).
Regarding claim 14, Takizawa discloses an apparatus to detect electrostatic discharge (ESD) (fig. 22, Col. 14 lines 52+), the apparatus comprising: a voltage source (Vcc); an anode of a first diode (P12) electrically coupled with the voltage source (Vcc); an anode of a second diode (N12) electrically coupled with a cathode of the first diode (P12); a cathode of a third diode (P11) electrically coupled with the voltage source (Vcc); a cathode of a fourth diode (N11) electrically coupled with an anode of the third diode (P11); an input/output (I/O) pad (PAD) electrically coupled with a cathode of the second diode (N12) and with an anode of the fourth diode (N11); a fuse (F2) electrically coupled with the voltage source (Vcc) and with the cathode of the first diode (P12) and with the anode of the third diode (P11); and wherein a selected one or more of: the first diode (P12), the second diode (N12), the third diode (P11), or the fourth diode (N11), are in a metal layer (128) above a transistor layer (140), the metal layer (128) vertically spaced apart (i.e., 1st metal layer 128 and 2nd metal layer 140 are distant) from the transistor layer (140).
Regarding claim 15, Takizawa discloses the apparatus (fig. 22, Col. 14 lines 52+), wherein a selected one or more of: the first diode (P12), the second diode (N12), the third diode (P11), or the fourth diode (N11), are metal-semiconductor-metal (MSM) diodes (i.e., implicit as a 1st metal layer 128 and a 2nd metal layer 140, also each diode in the ESD circuit is a MOS scheme).
Regarding claim 16, Takizawa discloses the apparatus (fig. 22, Col. 14 lines 52+), wherein the fuse (F2) is a first fuse (F2), and further comprising a second fuse (F4) electrically coupled with the voltage source (Vcc) and with the I/O pad (PAD, i.e., 140-Vcc & 140-PAD).
Regarding claim 17, Takizawa discloses the apparatus (fig. 22, Col. 14 lines 52+), wherein the fuse (F2) is between the metal layer 2 (116) and the metal layer 4 (120) of the substrate P (i.e., diffusion layers as layer 1/114; layer 2/116; layer 3/118; layer 4/120).
Regarding claim 18, Takizawa discloses a package (fig. 22, Col. 14 lines 52+) comprising: a substrate (P, fig. 17 shown above for illustration purposes, Col. 12 lines 61+) comprising: a first diode (P12) with a first side (cathode) and a second side (anode) opposite the first side (cathode), the first side (cathode) of the first diode (P12) electrically coupled with a voltage drain drain (Vdd) (Vcc);a second diode (N12) with a first side (cathode) and a second side (anode) opposite the first side (cathode), the second side (anode) of the second diode (N12) electrically coupled with a Vss (GND); an electrical pad (PAD); wherein the first diode (P12) and the second diode (N12) are in a metal layer (128) above a transistor layer (140), the metal layer (128) vertically spaced apart (i.e., 1st metal layer 128 and 2nd metal layer 140 are distant) from the transistor layer (140) and a transistor circuit (PFET, NFET) electrically coupled with the second side (anode) of the first diode (P12), the first side (cathode) of the second diode (N12), and the electrical pad (PAD); and a die (300, fig. 44, Col. 22 lines 54+), electrically coupled with the substrate (P).
Regarding claim 19, Takizawa discloses the package (fig. 22, Col. 14 lines 52+), wherein the transistor circuit (PFET, NFET) is in a front end of line (FEOL) portion (104) of the substrate (P) and the first diode (P12) and the second diode (N12) are in a back end of line (BEOL) portion (104) of the substrate (P, fig. 17 shown above for illustration purposes, Col. 12 lines 61+).
Regarding claim 20, Takizawa discloses the package (fig. 22, Col. 14 lines 52+), wherein the first diode (P12) and the second diode (N12) are metal-semiconductor-metal (MSM) diodes (i.e., implicit as a 1st metal layer 128 and a 2nd metal layer 140, also each diode in the ESD circuit is a MOS scheme).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270- 1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838