DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on October 14, 2025 have been considered and entered.
Specification
The amendment to the specification submitted on October 14, 2025 has been considered and entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 12 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 6, the claim currently recites that “the 16‑bit floating‑point value is one of a BF16 or a FP16 value.” However, independent claim 1 already specifies that the 16‑bit floating‑point value is BF16, so claim 6 as written appears to conflict with or dilute the limitation in claim 1. It is also unclear whether the intent is for FP16 to replace BF16 in claim 1 or to cover an additional conversion step. To avoid inconsistency and to clarify the scope, consider revising claim 6 to explicitly state the intended relationship to claim 1 — for example, if the applicant intends to claim conversion back from BF16 to FP16, recast claim 6 to read something like: “Wherein the 16‑bit floating‑point value is BF16 as recited in claim 1, and the method further comprises converting the BF16 value to an FP16 value.” This formulation preserves the BF16 limitation of claim 1 while clearly claiming the additional FP16 conversion.
As per claims 12 and 18, they’re rejected for the same reasoning set forth above in claim 6.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 5-9, 11-15 and 17-18 are provisionally rejected on the grounds of non-statutory anticipation-type double patenting as being unpatentable over claims 1-18, respectively, of co-pending Application No. 17/560557 as indicated in the previous office action. The rejections are maintained.
If Applicant wishes to traverse these rejections, the Office will reconsider them upon receipt of either: (a) a substantive response that addresses the double‑patenting grounds with claim amendments and/or persuasive argumentation demonstrating patentable distinction over the identified co‑pending claims; or (b) a terminal disclaimer filed in compliance with applicable rules and practice (including common ownership requirements), which, when entered, will overcome the non‑statutory double‑patenting objection.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 5-9, 11-15 and 17-18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claims are directed to the abstract idea of a mental process without significantly more.
Claim 1 recites an apparatus that decodes and executes an instruction which converts a 16-bit floating-point value from a source operand into a 32-bit floating-point value, and stores the converted value in one or more positions of a destination operand.
Step 2A, Prong One – Yes: The claim is directed to the abstract idea of a mental process because a person can mentally convert 16-bit floating point values into 32-bit floating point values.
The additional element of “decoder circuitry to decode a single instruction, the single instruction to include fields for an opcode, an identification of source operand location, and an identification of destination operand location” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a decoder is a generic computer component required to execute any instruction to carry out the abstract idea.
The additional element of “store that 32-bit floating point value in one or more data element positions of the identified destination operand” is insignificant extra solution activity since it amounts to mere data gathering and does not add a meaningful limitation to the single instruction.
The additional element of “instruction processing circuitry to execute the decoded instruction according to the opcode” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a generic computer includes instruction processing circuitry that executes decoded instructions.
Step 2A, Prong Two – No: The additional elements are generically recited computer elements that fail to provide a meaningful limitation to the abstract idea because they amount to simply implementing the abstract idea on a computer. They do not alone or in combination integrate the abstract idea into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, either alone or in combination. The analysis for Step 2B is the same as for Step 2A. Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. As discussed, the additional limitations of a decoder and instruction processing circuitry, are mere uses on a generic computer, and the additional limitation of storing of the 32-bit value is insignificant extra-solution activity and a well-understood, routine, and conventional function, and, therefore, none of the additional limitations can provide the abstract idea with significantly more to render the combination of the additional limitations an inventive concept, under MPEP 2106.05(f) and MPEP 2106.05(g) respectively.
The added limitation “wherein the 16-bit floating-point value is a BF16 value”, merely describes the 16-bit floating point value that a person can mentally convert into a 32-bit floating point value and as such is directed further to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 2 recites “wherein the field for an identification of the source operand location is to identify a vector register”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 3 recites “wherein the field for an identification of the source operand location is to identify a memory location”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 5 recites “wherein to convert the BF16 value to the 32-bit floating point value, the instruction processing circuitry is to append sixteen zeros to the BF16 value”. However, this limitation merely further describes the converting that a person can mentally perform and as such is further directed to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 6 recites “wherein the 16-bit floating-point value is one of a BF16 or a FP16 value”. However, this limitation merely describes the 16-bit floating point value that a person can mentally convert into a 32-bit floating point value and as such is directed further to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 7 recites a method to translate, decode and execute an instruction which converts a 16-bit floating-point value from a source operand into a 32-bit floating-point value, and stores the converted value in one or more positions of a destination operand.
Step 2A, Prong One – Yes: The claim is directed to the abstract idea of a mental process because a person can mentally convert 16-bit floating point values into 32-bit floating point values.
The additional element of “translating a single instruction of a first instruction set architecture into one or more instructions of a second, different instruction set architecture” is insignificant extra solution activity as it does not meaningfully limit the claim, it is merely a nominal extra-solution component of the claim.
The additional element of “the single instruction to include fields for an opcode, an identification of source operand location, and an identification of destination operand location” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as it describes an instruction required to implement the abstract idea on a generic computer.
The additional element of “store that 32-bit floating point value in one or more data element positions of the identified destination operand” is insignificant extra solution activity since it amounts to mere data gathering and does not add a meaningful limitation to the single instruction.
The additional element of “decoding one or more instructions of a second, different instruction set architecture” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a generic computer decodes component required to execute any instruction to carry out the abstract idea.
The additional element of “executing the decoded one or more instructions of a second, different instruction set architecture according to the opcode of the single instruction of the first instruction set architecture” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a generic computer includes executes decoded instructions according to their opcode.
Step 2A, Prong Two – No: The additional elements are generically recited computer elements that fail to provide a meaningful limitation to the abstract idea because they amount to simply implementing the abstract idea on a computer. They do not alone or in combination integrate the abstract idea into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, either alone or in combination. The analysis for Step 2B is the same as for Step 2A. Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. As discussed, the additional limitations of a single instruction, decoding and executing, are mere uses on a generic computer, and the additional limitations of translating an instruction and storing the 32-bit value are insignificant extra-solution activity and well-understood, routine, and conventional functions, and, therefore, none of the additional limitations can provide the abstract idea with significantly more to render the combination of the additional limitations an inventive concept, under MPEP 2106.05(f) and MPEP 2106.05(g) respectively.
The added limitation “wherein the 16-bit floating-point value is a BF16 value”, merely describes the 16-bit floating point value that a person can mentally convert into a 32-bit floating point value and as such is directed further to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 8 recites “wherein the field for an identification of the source operand location is to identify a vector register”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 9 recites “wherein the field for an identification of the source operand location is to identify a memory location”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 11 recites “wherein to convert the BF16 value to the 32-bit floating point value, the instruction processing circuitry is to append sixteen zeros to the BF16 value”. However, this limitation merely further describes the converting that a person can mentally perform and as such is further directed to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 12 recites “wherein the 16-bit floating-point value is one of a BF16 or a FP16 value”. However, this limitation merely describes the 16-bit floating point value that a person can mentally convert into a 32-bit floating point value and as such is directed further to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 13 recites a system that comprises memory, decode circuitry and instruction processing circuitry for an instruction which converts a 16-bit floating-point value from a source operand into a 32-bit floating-point value, and stores the converted value in one or more positions of a destination operand.
Step 2A, Prong One – Yes: The claim is directed to the abstract idea of a mental process because a person can mentally convert 16-bit floating point values into 32-bit floating point values.
The additional element of “a memory to store an instance of single instruction” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as memory to store an instruction is a generic computer component required to execute any instruction to carry out the abstract idea.
The additional element of “the single instruction to include fields for an opcode, an identification of source operand location, and an identification of destination operand location” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as it describes an instruction required to implement the abstract idea on a generic computer.
The additional element of “decoder circuitry to decode the at least one instance of the single instruction,” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a decoder is a generic computer component required to execute any instruction to carry out the abstract idea.
The additional element of “store that 32-bit floating point value in one or more data element positions of the identified destination operand” is insignificant extra solution activity since it amounts to mere data gathering and does not add a meaningful limitation to the single instruction.
The additional element of “instruction processing circuitry to execute the decoded instruction according to the opcode” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a generic computer includes instruction processing circuitry that executes decoded instructions.
Step 2A, Prong Two – No: The additional elements are generically recited computer elements that fail to provide a meaningful limitation to the abstract idea because they amount to simply implementing the abstract idea on a computer. They do not alone or in combination integrate the abstract idea into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, either alone or in combination. The analysis for Step 2B is the same as for Step 2A. Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. As discussed, the additional limitations of memory, a single instruction, a decoder and instruction processing circuitry, are mere uses on a generic computer, and the additional limitation of storing the 32-bit value is an insignificant extra-solution activity and well-understood, routine, and conventional function, and, therefore, none of the additional limitations can provide the abstract idea with significantly more to render the combination of the additional limitations an inventive concept, under MPEP 2106.05(f) and MPEP 2106.05(g) respectively.
The added limitation “wherein the 16-bit floating-point value is a BF16 value”, merely describes the 16-bit floating point value that a person can mentally convert into a 32-bit floating point value and as such is directed further to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 14 recites “wherein the field for an identification of the source operand location is to identify a vector register”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 15 recites “wherein the field for an identification of the source operand location is to identify a memory location”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 17 recites “wherein to convert the BF16 value to the 32-bit floating point value, the instruction processing circuitry is to append sixteen zeros to the BF16 value”. However, this limitation merely further describes the converting that a person can mentally perform and as such is further directed to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 18 recites “wherein the 16-bit floating-point value is one of a BF16 or a FP16 value”. However, this limitation merely describes the 16-bit floating point value that a person can mentally convert into a 32-bit floating point value and as such is directed further to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-9, 11-15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Valentine et al (US20190163474A1, herein Valentine), in view of Langhammer et al (US20190155574A1, herein Langhammer).
Regarding Claim 1, Valentine teaches an apparatus (FIGS. 4B, 12, 13 and [0170]: The apparatus of FIG. 12 may be included in a processor and/or system of FIG. 4B, in which processor 490 may include any or all of the blocks and/or elements shown in FIG. 12, which may operate according to the techniques and/or method described in the descriptions of FIG. 13.) comprising:
decoder circuitry to decode a single instruction (FIG. 4B: decode unit 440),
the single instruction to include fields for an opcode, an identification of a source operand location, and an identification of a destination operand location (FIG. 13 and [0175]: A first instruction (e.g., VCVTPH2PS) is fetched, the instruction having fields to specify an opcode, a source operand, a destination operand, and a broadcast indicator.),
wherein the opcode is to indicate instruction processing circuitry is to convert a 16-bit floating-point value from the identified source operand location into a 32-bit floating point value and store that 32-bit floating point value in one or more data element positions of the identified destination operand (FIGS. 12,13 and [0171-0173]: Precision converter 1200 converts a floating-point value stored in a source location in register file/memory 1210 from 16-bit half-precision to 32-bit single-precision and stores the resulting floating-point value in a destination location in register file/memory 1210. An embodiment uses processing hardware to perform conversion of packed data values in response to decoding a single instruction, identified herein with the mnemonic VCVTPH2PS. A VCVTPH2PS instruction may provide for optional write-masking, broadcasting, and/or zeroing. The format of a VCVTPH2PS instruction may include a broadcast field that indicates that a broadcast type data manipulation is to be performed, the broadcast may be performed by converting, from half-precision to single-precision, the floating-point value stored in the lowest element of the source memory location and storing the result in each element of the destination register.); and
the instruction processing circuitry to execute the decoded instruction according to the opcode (FIG. 4B: execution engine unit 450; [0172]: An embodiment uses processing hardware to perform conversion of packed data values in response to decoding a single instruction, identified herein with the mnemonic VCVTPH2PS).
Valentine does not explicitly teach the 16-bit floating-point value being a BF16 value.
Langhammer teaches a 16-bit floating-point value being a BF16 value (FIG. 7 and [0076-77]: During second floating-point mode 702, DSP block 120 may be configured to receive “BFLOAT16” inputs. BFLOAT16 floating-point numbers are 16 bits).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have modified Valentine to include the 16-bit floating-point value being a BF16 value. One of ordinary skill in the art would have been motivated to do this for the benefit of a greater exponent width with less mantissa precision, allowing for increased dynamic range with reduced accuracy (Langhammer, [0077]). Additionally, the exponent of a BFLOAT16 number is identical to the exponent of the single precision floating-point format, making it simple to cast/convert between the two formats (Langhammer, [0083]).).
This will result in the 16-bit floating-point value being a BF16 value.
Regarding Claim 2, Valentine teaches the apparatus of claim 1, wherein the field for an identification of the source operand location is to identify a vector register (FIG. 3 and [0111] discuss that in an embodiment of the invention, there are 32 vector registers 310, referenced as the zmm, ymm or xmm register set; [0126] discusses the processor core 490 has the physical register file(s) unit 458 which comprises a vector registers unit; [0170-0171] discusses the Precision converter 1200 converts a floating-point value stored in a source location in register file/memory 1210, which is included in the processor 490.).
Regarding Claim 3, Valentine teaches the apparatus of claim 1, wherein the field for an identification of the source operand location is to identify a memory location (FIG. 12 and [0170]: Precision converter 1200 converts a floating-point value stored in a source location in register file/memory 1210).
Regarding Claim 5, the combination of Valentine and Langhammer teaches the apparatus of claim 1.
However, the combination of Valentine and Langhammer does not explicitly teach converting the BF16 value to the 32-bit floating point value, by appending sixteen zeros to the BF16 value.
Langhammer further teaches converting the BF16 value to the 32-bit floating point value, by appending sixteen zeros to the BF16 value ([0083]: Casting between BFLOAT16 and FP32 is greatly simplified because of the identical number of exponents. To cast from BFLOAT16 to FP32, 16 zeros can be appended to the LSB of the mantissa.).
One of ordinary skill in the art, before the effective filing date of the claim invention, would have modified the combination of Valentine and Langhammer to include converting the BF16 value to the 32-bit floating point value, by appending sixteen zeros to the BF16 value. One of ordinary skill would have been motivated to do this for the benefit of being able to convert from a BF16 value with less accuracy, to a 32-bit floating point value (FP32), which offers higher accuracy as well as a wider dynamic range. For both BF16 and FP32 values, the size of the exponent is 8 bits, which allows for a direct transfer when converting, and the FP32 with 23 mantissa bits can represent all the exact values from the BF16. Padding 16 zeros to the end of the 16-bit floating-point value inserts the zeros in the mantissa bits, and preserves special values in the conversion. Additionally, appending zeros ensures that the original bits of the 16-bit floating-point value are unaltered and it keeps the bit pattern aligned when in 32-bit floating-point format.
This will result in the apparatus including converting the BF16 value to the 32-bit floating point value, by appending sixteen zeros to the BF16 value.
Regarding Claim 6, Valentine teaches the apparatus of claim 1.
However, Valentine does not explicitly teach the 16-bit floating-point value is one of a BF16 or a FP16 value.
Langhammer teaches a 16-bit floating-point value is one of a BF16 or a FP16 value (FIG. 7; [0073-0076] discusses DSP block 120 is operable in a first floating-point mode 700, where DSP block 120 may be configured to receive FP16 inputs, and a second floating-point mode 702, where DSP block 120 may be configured to receive “BFLOAT16” inputs.).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have modified Valentine to include the 16-bit floating-point value is one of a BF16 or a FP16 value. One of ordinary skill in the art would have been motivated to do this for the benefit of having an apparatus that can take both FP16 and BF16 floating-point values as inputs. The FP16 and the BF16 floating-point formats have different advantages, where FP16 value has greater mantissa precision allowing for increased accuracy, and the BF16 value has a larger exponent width increasing dynamic range (Langhammer, [0077]). Additionally, the floating-point 16 (FP16) operators support machine learning training procedures such as Convolution Neural Network algorithms (or Recursive Neural Network inference algorithms) which provides a technical improvement of greatly increasing the functional density of machine learning algorithms (Langhammer, [0017]).
This will result in the 16-bit floating-point value being one of a BF16 or a FP16 value.
Regarding Claims 7-9, Valentine teaches a method (FIG. 13) comprising: translating a single instruction of a first instruction set architecture into one or more instructions of a second, different instruction set architecture ( [0129] and [0170] discuss that the processor core 490 supports instruction sets, including the x86 instruction set, which includes the VCVTPH2PS instruction.; [0168] discusses instruction converter 1112 is used to convert the x86 binary code 1106 into code that may be natively executed by the processor without an x86 instruction set core 1114. The converted code will accomplish the general operation and be made up of instructions from the alternative instruction set), as well as additional steps to perform the method with corresponding limitations to the apparatus of claims 1-3, and are therefore rejected on the same premises.
Regarding Claims 11-12, the claims recite a method corresponding to the apparatus of claims 5-6, respectively, and are therefore rejected on the same premises.
Regarding Claims 13-15, Valentine teaches a system comprising (FIGS. 4A and 4B): memory to store at least one instance of a single instruction (FIG. 4B: memory unit 470), as well as additional system components with corresponding limitations to the apparatus of claims 1-3, and are therefore rejected on the same premises.
Regarding Claims 17-18, the claims recite a system, corresponding to the apparatus of claims 5-6, respectively, and are therefore rejected on the same premises.
Response to Arguments
Applicant's arguments filed on October 14, 2025 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to 35 USC 101 are not persuasive. The asserted 16-bit to 32-bit floating-point conversion claim remains not patent-eligible under 35 U.S.C. § 101. The claimed elements, viewed individually and in combination, do not integrate the abstract idea (data conversion) into a practical application, nor do they provide an “inventive concept” beyond a generic computer implementation. The applicant’s emphasis on purported improvements to floating-point conversion and references to Desjardins do not establish eligibility for the claimed combination as written. The cited paragraphs describe benefits; the Office’s position remains that benefits alone do not cure patent-eligibility if the claim’s essential elements are generic and do not amount to a concrete improvement.
The claims are directed to an abstract idea (data conversion) and the added elements (decoder circuitry, generic instruction processing circuitry, and data storage) are well-understood, routine, and conventional computer components. No “inventive concept” is present to transform the abstract idea into a patent-eligible application. The claimed integration is not shown to produce a technical improvement beyond standard computer functionality. Mere integration of a known abstract operation with generic components is not enough to render the claim eligible.
Regarding 35 U.S.C. 102, the Applicant argues that Langhammer teaches a hardware cast from FP32 to BFLOAT16 is not required in programmable device 100 and can be performed effectively for free using soft logic during the transfer of data bits from the DSP block output to other destinations. The Applicant further asserts that the claim requires the use of instruction processing circuitry to perform this conversion.
The Examiner respectfully disagrees. It is well understood in the art that software and hardware can be functionally equivalent and, in many implementations, perform the same conversion regardless of whether it is accomplished in software or hardware; the result is the same. Moreover, Langhammer expressly describes that “this programmable logic and routing circuitry is referred to as soft logic,” which corresponds to the function of processing circuitry. In other words, the Langhammer reference teaches both soft logic and the underlying hardware paths that perform the conversion, which can be invoked by instruction processing pathways in a practical implementation. Therefore, the presence of soft logic in Langhammer reads on the argued claim limitation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Heinecke et al (US20190079767A1) discusses converting a 16-bit floating point values into a 32-bit floating-point value, using a helper function that inserts zeros in the lower 16-bits. Sprangle et al (US8667250B2) discusses a vector-load-convert-and-write (VLoadConWr) instruction which converts from float16 to float32 format. Madduri et al (US 10223114 B1) discusses zero extending data elements in the destination location. Urbanski et al (US20190205131A1) discusses broadcasting data elements from 2 source data operands, performing an operation on the 2 sources and then storing in a destination operand location. Ishii et al (US20060112160A1) discusses a floating-point converter apparatus where a 16-bit floating-point value from a source is converted in a 32-bit floating-point value.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181