CTNF 17/560,557 CTNF 82148 DETAILED ACTION Claims 1-18 are pending in the case. Claims 1, 7, and 13 are independent claims. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are provisionally rejected on the grounds of non-statutory anticipation-type double patenting as being unpatentable over claims 1-18, respectively, of co-pending Application No. 17/560534 as indicated in the previous office action. The rejections are maintained. If Applicant wishes to traverse these rejections, the Office will reconsider them upon receipt of either: (a) a substantive response that addresses the double ‑ patenting grounds with claim amendments and/or persuasive argumentation demonstrating patentable distinction over the identified co ‑ pending claims; or (b) a terminal disclaimer filed in compliance with applicable rules and practice (including common ownership requirements), which, when entered, will overcome the non ‑ statutory double ‑ patenting objection. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claims are directed to the abstract idea of a mental process without significantly more. Claim 1 recites an apparatus that decodes and executes an instruction which converts a 16-bit floating-point value from a source operand into a 32-bit floating-point value, and stores the converted value in one or more positions of a destination operand. Step 2A, Prong One – Yes: The claim is directed to the abstract idea of a mental process because a person can mentally convert 16-bit floating point values into 32-bit floating point values. The additional element of “decoder circuitry to decode a single instruction, the single instruction to include fields for an opcode, an identification of source operand location, and an identification of destination operand location” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a decoder is a generic computer component required to execute any instruction to carry out the abstract idea. The additional element of “instruction processing circuitry to execute the decoded instruction according to the opcode” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a generic computer includes instruction processing circuitry that executes decoded instructions. Step 2A, Prong Two – No: The additional elements are generically recited computer elements that fail to provide a meaningful limitation to the abstract idea because they amount to simply implementing the abstract idea on a computer. They do not alone or in combination integrate the abstract idea into a practical application. Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, either alone or in combination. The analysis for Step 2B is the same as for Step 2A. Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. As discussed, the additional limitations of a decoder and instruction processing circuitry, are mere uses on a generic computer, and the additional limitation of storing of the 32-bit value is insignificant extra-solution activity and a well-understood, routine, and conventional function, and, therefore, none of the additional limitations can provide the abstract idea with significantly more to render the combination of the additional limitations an inventive concept, under MPEP 2106.05(f) and MPEP 2106.05(g) respectively. The added limitation “wherein the 16-bit floating-point value is a BF16 value”, merely describes the 16-bit floating point value that a person can mentally convert into a 32-bit floating point value and as such is directed further to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 2 recites “wherein the field for an identification of the source operand location is to identify a vector register”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 3 recites “wherein the field for an identification of the source operand location is to identify a memory location”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 4 recites “wherein the 16-bit floating point values are BF16 values”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 5 recites “wherein to convert the BF16 values to 32-bit floating point values by appending sixteen zeros to each of the BF16 values.” However, this limitation merely further describes the converting that a person can mentally perform and as such is further directed to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 6 recites “wherein the 16-bit floating point values are FP16 values”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 7 recites a method to translate, decode and execute an instruction which converts a 16-bit floating-point value from a source operand into a 32-bit floating-point value, and stores the converted value in one or more positions of a destination operand. Step 2A, Prong One – Yes: The claim is directed to the abstract idea of a mental process because a person can mentally convert 16-bit floating point values into 32-bit floating point values. The additional element of “translating a single instruction of a first instruction set architecture into one or more instructions of a second, different instruction set architecture” is insignificant extra solution activity as it does not meaningfully limit the claim, it is merely a nominal extra-solution component of the claim. The additional element of “the single instruction to include fields for an opcode, an identification of source operand location, and an identification of destination operand location” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as it describes an instruction required to implement the abstract idea on a generic computer. The additional element of “store that 32-bit floating point value in one or more data element positions of the identified destination operand” is insignificant extra solution activity since it amounts to mere data gathering and does not add a meaningful limitation to the single instruction. The additional element of “decoding one or more instructions of a second, different instruction set architecture” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a generic computer decodes component required to execute any instruction to carry out the abstract idea. The additional element of “executing the decoded one or more instructions of a second, different instruction set architecture according to the opcode of the single instruction of the first instruction set architecture” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a generic computer includes executes decoded instructions according to their opcode. Step 2A, Prong Two – No: The additional elements are generically recited computer elements that fail to provide a meaningful limitation to the abstract idea because they amount to simply implementing the abstract idea on a computer. They do not alone or in combination integrate the abstract idea into a practical application. Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, either alone or in combination. The analysis for Step 2B is the same as for Step 2A. Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. As discussed, the additional limitations of a single instruction, decoding and executing, are mere uses on a generic computer, and the additional limitations of translating an instruction and storing the 32-bit value are insignificant extra-solution activity and well-understood, routine, and conventional functions, and, therefore, none of the additional limitations can provide the abstract idea with significantly more to render the combination of the additional limitations an inventive concept, under MPEP 2106.05(f) and MPEP 2106.05(g) respectively. The added limitation “wherein the 16-bit floating-point value is a BF16 value”, merely describes the 16-bit floating point value that a person can mentally convert into a 32-bit floating point value and as such is directed further to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 8 recites “wherein the field for an identification of the source operand location is to identify a vector register”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 9 recites “wherein the field for an identification of the source operand location is to identify a memory location”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 10 recites “wherein the 16-bit floating point values are BF16 values”. However, this limitation merely further describes the converting that a person can mentally perform and as such is further directed to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 11 recites “wherein to convert the BF16 value to the 32-bit floating point value, the instruction processing circuitry is to append sixteen zeros to the BF16 value”. However, this limitation merely further describes the converting that a person can mentally perform and as such is further directed to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 12 recites “wherein the 16-bit floating-point value is one of a BF16 or a FP16 value”. However, this limitation merely describes the 16-bit floating point value that a person can mentally convert into a 32-bit floating point value and as such is directed further to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 13 recites a system that comprises memory, decode circuitry and instruction processing circuitry for an instruction which converts a 16-bit floating-point value from a source operand into a 32-bit floating-point value, and stores the converted value in one or more positions of a destination operand. Step 2A, Prong One – Yes: The claim is directed to the abstract idea of a mental process because a person can mentally convert 16-bit floating point values into 32-bit floating point values. The additional element of “a memory to store an instance of single instruction” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as memory to store an instruction is a generic computer component required to execute any instruction to carry out the abstract idea. The additional element of “the single instruction to include fields for an opcode, an identification of source operand location, and an identification of destination operand location” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as it describes an instruction required to implement the abstract idea on a generic computer. The additional element of “decoder circuitry to decode the at least one instance of the single instruction,” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a decoder is a generic computer component required to execute any instruction to carry out the abstract idea. The additional element of “store that 32-bit floating point value in one or more data element positions of the identified destination operand” is insignificant extra solution activity since it amounts to mere data gathering and does not add a meaningful limitation to the single instruction. The additional element of “instruction processing circuitry to execute the decoded instruction according to the opcode” amounts to the mere use of a generic computer as a tool to perform the abstract idea, as a generic computer includes instruction processing circuitry that executes decoded instructions. Step 2A, Prong Two – No: The additional elements are generically recited computer elements that fail to provide a meaningful limitation to the abstract idea because they amount to simply implementing the abstract idea on a computer. They do not alone or in combination integrate the abstract idea into a practical application. Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, either alone or in combination. The analysis for Step 2B is the same as for Step 2A. Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. As discussed, the additional limitations of memory, a single instruction, a decoder and instruction processing circuitry, are mere uses on a generic computer, and the additional limitation of storing the 32-bit value is an insignificant extra-solution activity and well-understood, routine, and conventional function, and, therefore, none of the additional limitations can provide the abstract idea with significantly more to render the combination of the additional limitations an inventive concept, under MPEP 2106.05(f) and MPEP 2106.05(g) respectively. The added limitation “wherein the 16-bit floating-point value is a BF16 value”, merely describes the 16-bit floating point value that a person can mentally convert into a 32-bit floating point value and as such is directed further to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 14 recites “wherein the field for an identification of the source operand location is to identify a vector register”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 15 recites “wherein the field for an identification of the source operand location is to identify a memory location”. However, this limitation merely describes the field of the instruction that implements the abstract idea on a generic computer. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 16 recites “wherein the 16-bit floating point values are BF16 values”. However, this limitation merely further describes the converting that a person can mentally perform and as such is further directed to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 17 recites “wherein to convert the BF16 value to the 32-bit floating point value, the instruction processing circuitry is to append sixteen zeros to the BF16 value”. However, this limitation merely further describes the converting that a person can mentally perform and as such is further directed to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 18 recites “wherein the 16-bit floating point values are FP16 values”. However, this limitation merely further describes the converting that a person can mentally perform and as such is further directed to the mental process. Thus, this limitation, taken alone or in combination, does not recite any additional element that would integrate the judicial exception into a practical application (Step 2A Prong Two – No) or amount to significantly more than the judicial exception (Step 2B – No). Accordingly, the claim is not patent-eligible under 35 U.S.C 101. Claim 19 recites “wherein the instruction processing circuitry does not have native support for the 16-bit floating value operations”. It does not change the statutory eligibility analysis. It merely limits the execution of an abstract data-conversion concept to specific category of constrained, generic processors. It does not alter the fact that the decoder and execution circuit are performing their well-understood, routine, and conventional generic functions of instruction handling. Therefore, it fails to provide “significantly more.” Claim 20 recites “wherein the instruction processing circuitry does not have native support for the 16-bit floating value operations”. It does not change the statutory eligibility analysis. It merely limits the execution of an abstract data-conversion concept to specific category of constrained, generic processors. It does not alter the fact that the decoder and execution circuit are performing their well-understood, routine, and conventional generic functions of instruction handling. Therefore, it fails to provide “significantly more.” Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim(s) 1- 3, 7-9, and 13-15 are reje cted under 35 U.S.C. 103 as being unpatentable over Eape n (US 20170031682 A1) in view of Valentine (US 20190163474 A1) in further view of Kashyap (US 20190042544 A1). Rega rding claim 1 , Eapen teaches an apparatus comprising: decoder circuitry to decode a single instruction (FIG. 1 Decode Circuitry element 20 and [0057]: Instructions are passed through decode circuitry 20 which decodes each instruction)… , wherein the opcode is to indicate instruction processing circuitry ( FIG. 15 and [0100]: the instruction opcode determines the type of the operation to be performed; FIG. 4 and [0069]: “The processing circuitry 100-0 also receives an instruction form signal 102 indicating which form of the instruction is being executed”. The type of operation and form of instruction refer to the same concept, indicating that the opcode specifies the operation to be performed by the processing circuitry. Additionally, [0056] “the different forms of the element size increasing instruction may have different opcodes” where [0066] “the second form of the lengthening instruction acts on the odd-numbered input data elements” ) is to convert 16 M -bit floating point values from odd data element positions from the identified source operand into 32 N -bit floating point values (FIG. 9 and [0076]: conversion instructions convert odd M bits into N bits; claim 7, [0045]: N = 2M) and instruction processing circuitry to execute the decoded instruction according to the opcode (FIG. 1 and [0057]: decoded instructions are passed to issue stage circuitry for issuing to execution pipelines. “The execution pipelines 30, 35, 40, 80 may collectively be considered to form processing circuitry”) . Eapen does not explicitly teach the single instruction to include fields for an opcode, an identification of a source operand, and an identification of destination operand, … converting from 16-bit floating point values from the identified source operand into 32-bit floating point values using round to nearest even … store the 32-bit floating point values in data element positions of the identified destination operand . Valentine teaches the single instruction to include fields for an opcode, an identification of a source operand, and an identification of a destination operand, (FIG. 13 and [0175]: an instruction is fetched having fields to specify an opcode, a source operand, a destination operand) , … converting 16-bit floating point values from the identified source operand into 32-bit floating point values (FIG. 12-13 and [0169-0179], and [0195]: convert a half-precision floating-point value to a single-precision floating-point value) using round to nearest even ([0059]: “Round operation control field 158—its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field 158 allows for the changing of the rounding mode on a per instruction basis”) and store the 32-bit floating point values in data element positions of the identified destination operand ([0195-0196]: store the single-precision floating-point value in element locations of a destination). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen by incorporating the teachings of Valentine to specify that for the M-bit data element, its format is half precision which is 16-bit floating point and for the N-bit data element, its format is single precision which is 32-bit floating point; and that the instruction have fields for an opcode, source operand and destination operand; and a rounding mode. Doing so would improve data processing performance while reducing storage requirements compared to other formats. It would also allow for efficient encoding and execution of mixed-precision operations in a processor. Eapen in view of Valentine does not explicitly teach using round to nearest even. Kashyap teaches using round to nearest even ([0133] “Round operation control field 959A—just as round operation control field 958, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest)” and [0223] “Example 8 includes the substance of the exemplary processor of Example 1, wherein the rounding mode is one of round to nearest even”) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen in view of Valentine by incorporating the teachings of Kashyap to use round to nearest even as a rounding mode. Doing so would allow for an additional rounding mode which provides statistically unbiased rounding. Regarding claim 2, Eapen in view of Valentine in further view of Kashyap teaches the apparatus of claim 1. Although Eapen teaches identifying a vector register ([0059-0060]: a vector register from vector register bank 65 is identified), Eapen does not explicitly teach such identification by “the field for the identifier of the source operand”. Valentine teaches wherein the field for the identifier of the source operand is to identify a vector register ([0178]: the source and destination operand fields may specify registers or memory locations, such registers including vector registers as supported in FIG. 4 and [0126]) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen in view of valentine in further view of Kashyap by incorporating the further teachings of Valentine to specify the field for the identifier of the source operand in an instruction. Doing so would provide a well-known and predictable mechanism for operand identification, allowing the instruction to flexibly reference various kinds of operand types. Regarding claim 3 , Eapen in view of Valentine in further view of Kashyap teaches the apparatus of claim 1. Valentine further teaches wherein the field for the identifier of the source operand is to identify a memory location ([0178]: the source and destination operand fields may specify registers or memory locations). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen in view of Valentine in further view of Kashyap by incorporating the further teachings of Valentine to include wherein the field for the identifier of the source operand is to identify a memory location. Doing so would enable efficient data retrieval, since data can be prefetched, reducing latency and improving parallel execution. Doing so would also maintain compatibility with existing instruction set architectures since many ISAs support operand retrieval via memory locations. Regarding claim 7 , Eapen teaches a method comprising: … wherein the opcode is to indicate instruction processing circuitry ( [0100]: the instruction opcode determines the type of the operation to be performed. [0056] “the different forms of the element size increasing instruction may have different opcodes” where [0066] “the second form of the lengthening instruction acts on the odd-numbered input data elements” ) is to convert 16 M -bit floating point values from odd data element positions from the identified source operand into 32 N -bit floating point values (FIG. 9 and [0076]: conversion instructions convert odd M bits into N bits; claim 7, [0045]: N = 2M) decoding a one or more instructions of the second set; (FIG. 1 Decode Circuitry element 20 and [0057]: Instructions are passed through decode circuitry 20 which decodes each instruction) , and executing the decoded one or more instructions of the second set according to the opcode of the single instruction of the first instruction set (FIG. 1 and [0057]: decoded instructions are passed to issue stage circuitry for issuing to execution pipelines. “The execution pipelines 30, 35, 40, 80 may collectively be considered to form processing circuitry”) . Eapen does not explicitly teach translating a single instruction of a first instruction set into one or more instructions of a second instruction set , the single instruction to include fields for an opcode, an identification of a source operand, and an identification of destination operand , … converting from 16-bit floating point values from the identified source operand into 32-bit floating point values using round to nearest even … store the 32-bit floating point values in data element positions of the identified destination operand . Valentine teaches translating a single instruction of a first instruction set into one or more instructions of a second instruction set (FIG. 11 and [0168]: “block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set”), the single instruction to include fields for an opcode, an identification of a source operand, and an identification of destination operand, (FIG. 13 and [0175]: an instruction is fetched having fields to specify an opcode, a source operand, a destination operand) , … converting from 16-bit floating point values from the identified source operand into 32-bit floating point values (FIG. 12-13 and [0169-0179, 0195]: convert a half-precision floating-point value to a single-precision floating-point value) using round to nearest even ([0059]: “Round operation control field 158—its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field 158 allows for the changing of the rounding mode on a per instruction basis”) and store the 32-bit floating point values in data element positions of the identified destination operand ([0195-0196]: store the single-precision floating-point value in element locations of a destination). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen by incorporating the teachings of Valentine to include translating a single instruction of a first instruction set into one or more instructions of a second instruction set; and to specify that for the M-bit data element, its format is half precision which is 16-bit floating point and for the N-bit data element, its format is single precision which is 32-bit floating point; and that the instruction have fields for an opcode, source operand and destination operand; and a rounding mode. Doing so would improve data processing performance while reducing storage requirements compared to other formats and would allow for efficient encoding and execution of mixed-precision operations in a processor. It would also be beneficial for cross instruction set architecture compatibility which the different ISAs exist due to varying design goals such as efficiency and performance. Compatibility between ISAs is useful to ensure seamless software execution. Eapen in view of Valentine does not explicitly teach using round to nearest even. Kashyap teaches using round to nearest even ([0133] “Round operation control field 959A—just as round operation control field 958, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest)” and [0223] “Example 8 includes the substance of the exemplary processor of Example 1, wherein the rounding mode is one of round to nearest even”) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen in view of Valentine by incorporating the teachings of Kashyap to use round to nearest even as a rounding mode. Doing so would allow for an additional rounding mode which provides statistically unbiased rounding. Regarding claim 8, Eapen in view of Valentine in further view of Kashyap teaches the method of claim 7. Although Eapen teaches identifying a vector register ([0059-0060]: a vector register from vector register bank 65 is identified), Eapen does not explicitly teach such identification by “the field for the identifier of the source operand”. Valentine teaches wherein the field for the identifier of the source operand is to identify a vector register ([0178]: the source and destination operand fields may specify registers or memory locations, such registers including vector registers as supported in FIG. 4 and [0126]) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen in view of Valentine in further view of Kashyap by incorporating the further teachings of Valentine to specify the field for the identifier of the source operand in an instruction. Doing so would provide a well-known and predictable mechanism for operand identification, allowing the instruction to flexibly reference various kinds of operand types. Regarding claim 9 , Eapen in view of Valentine in further view of Kashyap teaches the method of claim 7. Valentine further teaches wherein the field for the identifier of the source operand is to identify a memory location ([0178]: the source and destination operand fields may specify registers or memory locations). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen in view of Valentine in further view of Kashyap by incorporating the further teachings of Valentine to include wherein the field for the identifier of the source operand is to identify a memory location. Doing so would enable efficient data retrieval, since data can be prefetched, reducing latency and improving parallel execution. Doing so would also maintain compatibility with existing instruction set architectures since many ISAs support operand retrieval via memory locations. Regarding claims 13-15, the claims recite a system comprising: memory to store an instance of a single instruction (Eapen, [0057]: An instruction cache which is typically coupled to memory is used to fetch the instructions), the single instruction to include fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate instruction processing circuitry to perform operations corresponding to the apparatus of claims 1-3 respectively, and are therefore rejected on the same premises . 07-21-aia AIA Claim (s) 4-6, 10-12, and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eapen (US 20170031682 A1), in view of Valentine (US 20190163474 A1), in further view of Kashyap (US 20190042544 A1), and in further view of Langhammer (US 20190155574 A1) . Regarding claim 4 , Eapen in view of Valentine in further view of Kashyap teaches the apparatus of claim 1. Eapen in view of Valentine in further view of Kashyap does not explicitly teach wherein the 16-bit floating point values are BF16 values . Langhammer teaches wherein the 16-bit floating point values are BF16 values (FIG. 7 and [0076]: states that the DSP may be configured to receive BFLOAT16 inputs). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen in view of Valentine in further view of Kashyap by incorporating the teachings of Langhammer to include wherein the 16-bit floating point values are BF16 values. Doing so would trade off the mantissa precision for exponent width, which increases the dynamic range in exchange for reduced accuracy (Langhammer, [0077]). Conversion between BFLOAT16 and 32-bit floating point would be greatly simplified because the number of exponents is identical (Langhammer, [0083]). Regarding claim 5 , Eapen in view of Valentine in further view of Kashyap and Langhammer teaches the apparatus of claim 4. Langhammer further teaches wherein instruction processing circuitry is to convert the BF16 values to 32-bit floating point values by appending sixteen zeros to each of the BF16 values (Langhammer, [0083]: “To cast from BFLOAT16 to FP32, 16 zeros can be appended to the LSB of the mantissa”). Regarding claim 6 , Eapen in view of Valentine in further view of Kashyap teaches the apparatus of claim 1. Eapen in view of Valentine in further view of Kashyap does not explicitly teach wherein the 16-bit floating point values are FP16 values. Langhammer teaches wherein the 16-bit floating point values are FP16 values ([0052]: states that an FP16 value may be promoted or cast from FP16 to FP32 using a format casting/promoting circuit). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen in view of Valentine in further view of Kashyap by incorporating the teachings of Langhammer to include wherein the 16-bit floating point values are FP16 values. Doing so would be beneficial for supporting machine learning training procedures such as Convolution Neural Network algorithms or Recursive Neural Network inference algorithms (Langhammer, [0017]). Doing so would also trade off the exponent width for a larger mantissa precision compared to other 16-bit floating point representations (Langhammer, [0077]). Regarding claim 10 , Eapen in view of Valentine in further view of Kashyap teaches the method of claim 7. Eapen in view of Valentine in further view of Kashyap does not explicitly teach wherein the 16-bit floating point values are BF16 values . Langhammer teaches wherein the 16-bit floating point values are BF16 values ([0076]: states that the DSP may be configured to receive BFLOAT16 inputs). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen in view of Valentine in further view of Kashyap by incorporating the teachings of Langhammer to include wherein the 16-bit floating point values are BF16 values. Doing so would trade off the mantissa precision for exponent width, which increases the dynamic range in exchange for reduced accuracy (Langhammer, [0077]). Conversion between BFLOAT16 and 32-bit floating point would be greatly simplified because the number of exponents is identical (Langhammer, [0083]). Regarding claim 11 , Eapen in view of Valentine in further view of Kashyap and Langhammer teaches the method of claim 10. Langhammer further teaches wherein instruction processing circuitry is to convert the BF16 values to 32-bit floating point values by appending sixteen zeros to each of the BF16 values (Langhammer, [0083]: “To cast from BFLOAT16 to FP32, 16 zeros can be appended to the LSB of the mantissa”). Regarding claim 12 , Eapen in view of Valentine in further view of Kashyap teaches the method of claim 7. Eapen in view of Valentine in further view of Kashyap does not explicitly teach wherein the 16-bit floating point values are FP16 values. Langhammer teaches wherein the 16-bit floating point values are FP16 values ([0052]: states that an FP16 value may be promoted or cast from FP16 to FP32 using a format casting/promoting circuit). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Eapen in view of Valentine in further view of Kashyap by incorporating the teachings of Langhammer to include wherein the 16-bit floating point values are FP16 values. Doing so would be beneficial for supporting machine learning training procedures such as Convolution Neural Network algorithms or Recursive Neural Network inference algorithms (Langhammer, [0017]). Doing so would also trade off the exponent width for a larger mantissa precision compared to other 16-bit floating point representations (Langhammer, [0077]). Regarding claim 16-18, the claims recite a system corresponding to the apparatus of claims 4-6 respectively, and are therefore rejected on the same premises . 07-21-aia AIA Claim (s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eapen (US 20170031682 A1), in view of Valentine (US 20190163474 A1), in further view of Kashyap (US 20190042544 A1), and in further view of Tang et al. US PG-Pub No.: 2005/0138101 (hereinafter Tang) . As per claims 19 and 20, the combination of Eapen, Valentine and Kashyap did not specifically teach wherein the instruction processing circuitry does not native support for 16-bit floating point value operations. However, Tang teaches that many mobile processors, such as Intel XScale processors, are integer-based processors that provide native native-integer based operations, and that the limitation numeric range of integer types may be overcome by executing floating-point emulation software on integer-based processors. Thus, Tang teaches that floating-point functionality, including single precision floating-point representation/processing, may be provided on instruction processing circuitry that does not natively support floating-point operations, but instead natively supports integer operations and uses emulation software (Tang, paragraph [0003] to [0005]). One of ordinary skill in the art, before the effective filing date of the claimed invention, would have modified Eapen, Valentine and Kashyap to use Tang’s integer-based/emulated implementation environment to reduce hardware area, power consumption, and implementation complexity while maintaining compactible with FP16-format results. Response to Arguments/Amendments Applicant’s amendments, filed February 17, 2026, with respect to the prior art rejection have been considered but are not persuasive. Applicant argues that the cited references fail to teach that the opcode indicates use of round-to-nearest-even because the cited rounding control information is allegedly outside the opcode. However, the claims are directed to a single instruction including multiple fields, and the cited art teaches instruction encodings in which operation-control information, including rounding control, is provided as part of the instruction. Valentine teaches a vector-friendly instruction format including opcode-related fields and an augmentation operation field, wherein a round operation control field distinguishes which rounding operation is to be performed and allows rounding mode selection on a per-instruction basis. Kashyap further teaches that the rounding mode may be specified per instruction by an immediate value and expressly identifies round-to-nearest-with-ties-to-even as an IEEE rounding mode. Accordingly, the combination teaches or at least renders obvious a single instruction whose decoded operation indicates conversion of a 16-bit floating-point values to 32-bit floating-point values using round-to-nearest-even. Applicant’s argument that use of a field outside the real opcode would require extra bits and defeat efficient encoding is also not persuasive. The efficient-encoding rationale does not require all operation-control information to be contained in a single opcode byte. Rather, the cited vector instruction formats expressly use opcode, operand, immediate, and augmentation/control fields to compactly encode the operation in a single instruction. Thus, use of a round-control/immediate field is consistent with, not contrary to, efficient instruction encoding. New claims 19 and 20 are further rejected in view of Tang to show lacking native floating-point support and performing floating-point functionality through integer/emulated operations. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDRISS N ALROBAYE whose telephone number is (571)270-1023. The examiner can normally be reached Mon-Fri, 8am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached at 571-272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181 Application/Control Number: 17/560,557 Page 2 Art Unit: 2181 Application/Control Number: 17/560,557 Page 3 Art Unit: 2181 Application/Control Number: 17/560,557 Page 4 Art Unit: 2181 Application/Control Number: 17/560,557 Page 5 Art Unit: 2181 Application/Control Number: 17/560,557 Page 6 Art Unit: 2181 Application/Control Number: 17/560,557 Page 7 Art Unit: 2181 Application/Control Number: 17/560,557 Page 8 Art Unit: 2181 Application/Control Number: 17/560,557 Page 9 Art Unit: 2181 Application/Control Number: 17/560,557 Page 10 Art Unit: 2181 Application/Control Number: 17/560,557 Page 11 Art Unit: 2181 Application/Control Number: 17/560,557 Page 12 Art Unit: 2181 Application/Control Number: 17/560,557 Page 13 Art Unit: 2181 Application/Control Number: 17/560,557 Page 14 Art Unit: 2181 Application/Control Number: 17/560,557 Page 15 Art Unit: 2181 Application/Control Number: 17/560,557 Page 16 Art Unit: 2181 Application/Control Number: 17/560,557 Page 17 Art Unit: 2181 Application/Control Number: 17/560,557 Page 18 Art Unit: 2181 Application/Control Number: 17/560,557 Page 19 Art Unit: 2181 Application/Control Number: 17/560,557 Page 20 Art Unit: 2181 Application/Control Number: 17/560,557 Page 21 Art Unit: 2181 Application/Control Number: 17/560,557 Page 22 Art Unit: 2181 Application/Control Number: 17/560,557 Page 23 Art Unit: 2181 Application/Control Number: 17/560,557 Page 24 Art Unit: 2181 Application/Control Number: 17/560,557 Page 25 Art Unit: 2181
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