CTNF 17/560,622 CTNF 99329 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Continued Examination Under 37 CFR 1.114 07-42-04 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/27/2026 has been entered. Claims 1-20 remain pending in this application. Claim Objections 07-29-01 AIA Claim s 1 and 8 are objected to because of the following informalities: Claims 1 and 8 recite "...determine an execution circuitry configuration based, at least in part, instruction types of the monitored threads..." The claims should recite ""...determine an execution circuitry configuration based, at least in part, on instruction types of the monitored threads...” Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1, 6, 8, 13, 15, and 19 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Chien (US Pub. No. 2018/0095792 A1) . As per claim 1, Chien teaches an apparatus comprising: monitoring circuitry to monitor threads in a processor core (¶ [0022], “The apparatus 100 comprises a multi-core processor 105 including a plurality of processor cores such as four processor cores 1052A-1052D, a task scheduler 110, and a processor manager 115 .” ¶ [0045], “For example, the processor manager 115 can be arranged to turn on/off the processor cores (e.g. power gating), suspend/pause/resume the processor cores (e.g. clock gating), increase/decrease the working frequencies of the processor cores, and/or change/adjust other characteristics of the processor cores based on the information gathered from the task scheduler 110 and/or the information of characteristics of the processor cores. The processor manager 115 can be implemented in the operating system or implemented as a firmware, which can decide to manage the characteristics of the processor cores based on the information form the task scheduler 110. Alternatively, the processor manager 115 can be implemented as a hardware circuit which can decide to manage the characteristics of the processor cores based on the processor cores' utilization rates, performance counters, ISA usage counters, and/or virtual core distribution.”); a scheduler to determine an execution circuitry configuration based, at least in part, instruction types of the monitored threads (¶ [0022]-[0023], ““The apparatus 100 comprises a multi-core processor 105 including a plurality of processor cores such as four processor cores 1052A-1052D, a task scheduler 110 , and a processor manager 115…The task scheduler 110 is coupled to the multi-core processor 105 and arranged to dispatch at least one task from a task queue (not shown in FIG. 1) to the processor cores 1052A-1052D wherein the at least one task comprises N-bit task(s) and/or 2N-bit task(s) (but not limited); the at least one task may comprises (N/2)-bit subset tasks. For example, the task scheduler 110 can be arranged to dispatch the at least one task to the processor cores 1052A-1052D by referring to at least one information of an instruction set architecture compatibility of the at least one task , a priority of tasks pending in the task queue, and/or the characteristics of the processor cores 1052A-1052D.” See also paras. 0039-0040.); and hardware unit off resources, in response to commands from the scheduler, to selectively enable and/or disable over-provisionable execution circuitry of different types according to the execution circuitry configuration in the processor core to tune the processor core for a thread (¶ [0033], “The task scheduler 110 can preferentially assign 32-bit task(s) to the processor cores 3052C which are equivalently processor cores dedicated to run the 32-bit task(s). The processor manager 115 can turn on at least one of the power efficient processor cores 3052A and turn off the fast processor cores 3052B, and the task scheduler 110 assigns specific task(s) to the at least one turned-on power efficient process core, if running the specific task(s) does not need to consume more computation resources or more power. The processor manager 115 can turn on at least one of the fast processor cores 3052B and the task scheduler 110 assigns specific task(s) to the at least one turned-on fast process core if running the specific task(s) needs to consume more computation resources or more power.” ¶ [0041]-[0042], “For the implementation of task scheduler 110, the operating system is arranged to maintain a list of 32-bit and 64-bit pending tasks, and picks up another compatible task from the task queue when a context switch interrupt on a processor core happens. The operating system sets up corresponding registers, updates the user space execution mode, and performs the context switch. Information of the task queue (e.g. the number of pending tasks) and the priority of list maintained by the operating system can be referenced by the processor manager 115 to control or turn on/off the physical processor cores. For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue…In addition, if a 64-bit task requires a lock which is held by a 32-bit task, it is preferable to increase the execution speed of the 32-bit task. For increasing the execution speed, it is preferred to increase the working frequency of processor cores compatible with 32-bit tasks or to turn on more processor cores compatible with 32-bit tasks so that a blocking task has more opportunity to be scheduled.” See also para. 0034.). As per claim 6, Chien teaches the apparatus of claim 1. Chien also teaches wherein the monitoring circuitry is external to the processor core (¶ [0024], “The processor manager 115 is coupled to the multi-core processor 105 and task scheduler 110, and is arranged to turn on/off the processor cores 1052A-1052D. For example, the processor manager 115 can be arranged to turn on/off the processor cores 1052A-1052D according to the information gathered from the task scheduler 110 and/or the information from the processor cores 1052A-1052D.” See also Fig. 1.). As per claim 8, it is a system claim comprising similar limitations to claim 1, so it is rejected for similar reasons. Chien also teaches memory to store an operating system that includes a scheduler (¶ [0041], “Further, in one embodiment, the task scheduler 110 can be implemented in the operating system. An advantage is that the operating system can be aware of the physical configuration of the processor cores; the processor cores of FIGS. 1-5 also refer to physical processor cores.”). As per claim 13, it is a system claim comprising similar limitations to claim 6, so it is rejected for similar reasons. As per claim 15, Chien teaches a method comprising: receiving information regarding monitored threads on one or more processor cores or accelerators (¶ [0045], “For example, the processor manager 115 can be arranged to turn on/off the processor cores (e.g. power gating), suspend/pause/resume the processor cores (e.g. clock gating), increase/decrease the working frequencies of the processor cores, and/or change/adjust other characteristics of the processor cores based on the information gathered from the task scheduler 110 and/or the information of characteristics of the processor cores. The processor manager 115 can be implemented in the operating system or implemented as a firmware, which can decide to manage the characteristics of the processor cores based on the information form the task scheduler 110. Alternatively, the processor manager 115 can be implemented as a hardware circuit which can decide to manage the characteristics of the processor cores based on the processor cores' utilization rates, performance counters, ISA usage counters, and/or virtual core distribution.”); determining a resource configuration for a particular thread to be executed on at least one processor core or accelerator based, at least in part, on information regarding monitored threads including instruction types ((¶ [0022]-[0023], ““The apparatus 100 comprises a multi-core processor 105 including a plurality of processor cores such as four processor cores 1052A-1052D, a task scheduler 110 , and a processor manager 115…The task scheduler 110 is coupled to the multi-core processor 105 and arranged to dispatch at least one task from a task queue (not shown in FIG. 1) to the processor cores 1052A-1052D wherein the at least one task comprises N-bit task(s) and/or 2N-bit task(s) (but not limited); the at least one task may comprises (N/2)-bit subset tasks. For example, the task scheduler 110 can be arranged to dispatch the at least one task to the processor cores 1052A-1052D by referring to at least one information of an instruction set architecture compatibility of the at least one task , a priority of tasks pending in the task queue, and/or the characteristics of the processor cores 1052A-1052D.” See also paras. 0039-0040.); and selectively enabling and/or disabling over-provisionable execution circuitry of different types according to the execution circuitry configuration using hardware unit off resources in a processor core or accelerator to configure the processor core or accelerator according to the determined resource configuration (¶ [0033], “The task scheduler 110 can preferentially assign 32-bit task(s) to the processor cores 3052C which are equivalently processor cores dedicated to run the 32-bit task(s). The processor manager 115 can turn on at least one of the power efficient processor cores 3052A and turn off the fast processor cores 3052B, and the task scheduler 110 assigns specific task(s) to the at least one turned-on power efficient process core, if running the specific task(s) does not need to consume more computation resources or more power. The processor manager 115 can turn on at least one of the fast processor cores 3052B and the task scheduler 110 assigns specific task(s) to the at least one turned-on fast process core if running the specific task(s) needs to consume more computation resources or more power.” ¶ [0041]-[0042], “For the implementation of task scheduler 110, the operating system is arranged to maintain a list of 32-bit and 64-bit pending tasks, and picks up another compatible task from the task queue when a context switch interrupt on a processor core happens. The operating system sets up corresponding registers, updates the user space execution mode, and performs the context switch. Information of the task queue (e.g. the number of pending tasks) and the priority of list maintained by the operating system can be referenced by the processor manager 115 to control or turn on/off the physical processor cores. For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue…In addition, if a 64-bit task requires a lock which is held by a 32-bit task, it is preferable to increase the execution speed of the 32-bit task. For increasing the execution speed, it is preferred to increase the working frequency of processor cores compatible with 32-bit tasks or to turn on more processor cores compatible with 32-bit tasks so that a blocking task has more opportunity to be scheduled.” See also para. 0034.). As per claim 19, it is a method claim comprising similar limitations to claim 6, so it is rejected for similar reasons . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim(s ) 2-5, 9-12 and 16-18 are re jected under 35 U.S.C. 103 as being unpatentable over Ch ien as applied to claims 1, 8, and 15 ab ove, and further in view of An anthakrishnan et al. (US Pub. No. 2019/0102221 A1 hereinafter Ananthakrishnan). As per claim 2, Chien teaches the apparatus of claim 1. Chien fails to explicitly teach the processor cores including floating point unit execution circuitry. However, Ananthakrishnan teaches wherein the processor core includes over-provisionable floating point unit execution circuitry (¶ [0061], “Processor 400 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SoC), or other device to execute code. Processor 400, in one embodiment, includes at least two cores—cores 401 and 402, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 400 may include any number of processing elements that may be symmetric or asymmetric.” ¶ [0078], “Various resources may be present in execution units 520, including, for example, various integer, floating point, and single instruction multiple data (SIMD) logic units, among other specialized hardware.”). Chien and Ananthakrishnan are considered to be analogous to the claimed invention because they are in the same field of task scheduling and/or resource allocation. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the processor cores of Chein with the processor cores that contain floating point unit execution circuitry of Ananthakrishnan to arrive at the claimed invention. This substitution would have been reasonable and yielded predictable results under MPEP § 2143 as both references configure/allocate processing resources for executing tasks. As per claim 3, Chien teaches the apparatus of claim 1. Chien fails to explicitly teach the processor cores including arithmetic logic unit execution circuitry. However, Ananthakrishnan teaches wherein the processor core includes over-provisionable arithmetic logic unit execution circuitry ((¶ [0061], “Processor 400 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SoC), or other device to execute code. Processor 400, in one embodiment, includes at least two cores—cores 401 and 402, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 400 may include any number of processing elements that may be symmetric or asymmetric.” ¶ [0078], “For example, such execution units may include one or more arithmetic logic units (ALUs) 522 and one or more vector execution units 524, among other such execution units.”). Chien and Ananthakrishnan are considered to be analogous to the claimed invention because they are in the same field of task scheduling and/or resource allocation. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the processor cores of Chein with the processor cores that contain arithmetic logic unit execution circuitry of Ananthakrishnan to arrive at the claimed invention. This substitution would have been reasonable and yielded predictable results under MPEP § 2143 as both references configure/allocate processing resources for executing tasks. As per claim 4, Chien teaches the apparatus of claim 1. Chien fails to teach monitoring circuitry being coupled to a decoder of the processor core. However, Ananthakrishnan teaches wherein the monitoring circuitry is coupled to a decoder of the processor core (¶ [0067], “Core 401 further includes decode module 425 coupled to a fetch unit to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 401a, 401b, respectively. Usually core 401 is associated with a first ISA, which defines/specifies instructions executable on processor 400. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode module 425 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA.”). Chien and Ananthakrishnan are considered to be analogous to the claimed invention because they are in the same field of task scheduling and/or resource allocation. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chien with the well-known technique of a processor core containing a decoder as taught by Ananthakrishnan to arrive at the claimed invention. This modification would have been reasonable and yielded predictable results under MPEP § 2143 as both references configure/allocate processing resources for executing tasks. As per claim 5, Chien teaches the apparatus of claim 1. Chien teaches the monitoring circuitry ((¶ [0022], “The apparatus 100 comprises a multi-core processor 105 including a plurality of processor cores such as four processor cores 1052A-1052D, a task scheduler 110, and a processor manager 115 .”). Chien fails to teach the monitoring circuitry being a part of a reservation station and/or scheduler. However, Ananthakrishnan teaches wherein the monitoring circuitry is a part of a reservation station and/or scheduler (¶ [0289]-[0291], “In one or more embodiments, the scheduling manager 2780 and/or the scheduler 2785 may implemented in software (e.g., the operating system, a stand-alone application, etc.). The scheduling manager 2780 may control the amount and/or format of the TA rankings 2750 and TS rankings 2760 provided to the scheduler 2785. For example, the scheduling manager 2780 may sort PE rankings, may filter PE rankings according to criteria (e.g., by age, by PE group, by thread group, by type, and so forth), may combine multiple PE rankings to generate combined PE rankings, may reformat PE rankings, and so forth. In one or more embodiments, the scheduler 2785 may use the TA rankings 2750 and/or the TS rankings 2760 to allocate threads to PEs (e.g., PEs 2620 shown in FIG. 26). For example, the scheduler 2785 may use PE information to schedule threads based on a current system priority, policy, or state (e.g., a specified balance between performance, efficiency, power consumption, and/or reliability priorities), based on thread specific characteristics (e.g., whether a thread is defined as a foreground task or a background task) , to control temperature gradients and/or hot spots in PEs, and so forth.” See also paras. 0296-0297.). Chien and Ananthakrishnan are considered to be analogous to the claimed invention because they are in the same field of task scheduling and/or resource allocation. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the monitoring circuitry of Chein with the monitoring circuitry that is a part of a scheduler as taught by Ananthakrishnan to arrive at the claimed invention. This substitution would have been reasonable and yielded predictable results under MPEP § 2143 as both references configure/allocate processing resources for executing tasks. As per claim 9, it is a system claim comprising similar limitations to claim 2, so it is rejected for similar reasons. As per claim 10, it is a system claim comprising similar limitations to claim 3, so it is rejected for similar reasons. As per claim 11, it is a system claim comprising similar limitations to claim 4, so it is rejected for similar reasons. As per claim 12, it is a system claim comprising similar limitations to claim 5, so it is rejected for similar reasons. As per claim 16, it is a method claim comprising similar limitations to claim 2, so it is rejected for similar reasons. As per claim 17, it is a method claim comprising similar limitations to claim 3, so it is rejected for similar reasons. As per claim 18, it is a method claim comprising similar limitations to claim 5, so it is rejected for similar reasons . 07-22-aia AIA Claim (s) 7, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chien as applied to claim s 1, 8, and 15 above, and further in view of Choi (US Patent No. 10,630,294 B1) . As per claim 7, Chien teaches the apparatus of claim 1. Chien teaches disable the execution circuitry (¶ [0041]-[0042], “For the implementation of task scheduler 110, the operating system is arranged to maintain a list of 32-bit and 64-bit pending tasks, and picks up another compatible task from the task queue when a context switch interrupt on a processor core happens. The operating system sets up corresponding registers, updates the user space execution mode, and performs the context switch. Information of the task queue (e.g. the number of pending tasks) and the priority of list maintained by the operating system can be referenced by the processor manager 115 to control or turn on/off the physical processor cores . For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue…In addition, if a 64-bit task requires a lock which is held by a 32-bit task, it is preferable to increase the execution speed of the 32-bit task. For increasing the execution speed, it is preferred to increase the working frequency of processor cores compatible with 32-bit tasks or to turn on more processor cores compatible with 32-bit tasks so that a blocking task has more opportunity to be scheduled.”). Chien fails to teach one or more fuses to disable the execution circuitry. However, Choi teaches wherein the hardware unit off resources comprises one or more fuses to disable the execution circuitry (Col. 6, lines 26-47, “In both embodiments, semiconductor device 10 may include the same circuitry whether configured as a master or a slave. However, the master signal or fuse may disable slave circuitry when semiconductor device 10 is configured as a master and disable master circuitry when semiconductor device 10 is configured as a slave.”). Chien and Choi are considered to be analogous to the claimed invention because they are in the same field of task scheduling and/or resource allocation. Therefore, it would have been obvious to substitute the known technique of using fuses to enable/disable circuitry for the general enabling/disabling of circuitry as taught by Chien to arrive at the claimed invention. The substitution of the enabling/disabling technique would allow for predictable results of resource allocation/configuration as proper under MPEP § 2143 as both references configure/allocate resources for executing tasks. As per claim 14, it is a system claim comprising similar limitations to claim 7, so it is rejected for similar reasons. As per claim 20, it is a method claim comprising similar limitations to claim 7, so it is rejected for similar reasons. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant has amended the claims with new limitations that change the scope of the claimed invention. Therefore, the amended claims necessitate new rejections, as addressed above. The amended claims are not allowable over prior art cited previously along with an additional reference, necessitated by amendment, for reasons indicated above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN ROBERT DAKITA EWALD whose telephone number is (703)756-1845. The examiner can normally be reached Monday-Friday: 9:00-5:30 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lewis Bullock can be reached at (571)272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.D.E./Examiner, Art Unit 2199 /LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199 Application/Control Number: 17/560,622 Page 2 Art Unit: 2199 Application/Control Number: 17/560,622 Page 3 Art Unit: 2199 Application/Control Number: 17/560,622 Page 4 Art Unit: 2199 Application/Control Number: 17/560,622 Page 5 Art Unit: 2199 Application/Control Number: 17/560,622 Page 6 Art Unit: 2199 Application/Control Number: 17/560,622 Page 7 Art Unit: 2199 Application/Control Number: 17/560,622 Page 8 Art Unit: 2199 Application/Control Number: 17/560,622 Page 9 Art Unit: 2199 Application/Control Number: 17/560,622 Page 10 Art Unit: 2199 Application/Control Number: 17/560,622 Page 11 Art Unit: 2199 Application/Control Number: 17/560,622 Page 12 Art Unit: 2199 Application/Control Number: 17/560,622 Page 13 Art Unit: 2199 Application/Control Number: 17/560,622 Page 14 Art Unit: 2199 Application/Control Number: 17/560,622 Page 15 Art Unit: 2199 Application/Control Number: 17/560,622 Page 16 Art Unit: 2199 Application/Control Number: 17/560,622 Page 17 Art Unit: 2199 Application/Control Number: 17/560,622 Page 18 Art Unit: 2199
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