DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-5, 7-12, and 14-20 are pending. Claims 1, 8, and 15 have been amended as per Applicants' request. Claims 6 and 13 have been canceled as per Applicants' request.
Papers Submitted
It is hereby acknowledged that the following papers have been received and placed of record in the file:
Amended Claims as filed on July 07, 2025
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 7, 8, 12, 14, 15, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Deutsch et al. (US 2021/0240638) (hereinafter Deutsch) (published August 05, 2021).
Regarding Claims 1, 8, and 15, taking claim 8 as exemplary, Deutsch discloses a system comprising: non-volatile memory to store data;
“The memory 120 of the computing device 100 may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein” (Deutsch [0076])
a core to execute a memory read instruction for a memory address;
“The processor 102 may be embodied as any type of processor capable of performing the functions described herein. For example, the processor 102 may be embodied as a single-core or multi-core central processing unit (CPU), a multiple-CPU processor or processing/controlling circuit, or multiple diverse processing units or circuits (e.g., CPU and Graphics Processing Unit (GPU), etc.)” (Deutsch [0076])
“When a memory access request (e.g., LOAD, MOV, etc.) is made to an address within the 64B allocation 668, the processor circuitry 530 determines the address of the marker region 652 of the 128B slot 654 to which the 64B allocation 668 is assigned, reads the current data at the determined address of the marker region 652, and compares the current data to the selected initialization marker, which may be stored in the state of a memory manager module (e.g., 144), for example” (Deutsch [0142] the memory access request of LOAD or MOV would read data at a memory address)
a memory controller to interact with the non-volatile memory,
“For example, the I/O subsystem 124 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.) and/or other components and subsystems to facilitate the input/output operations” (Deutsch [0077])
the memory controller to determine, in response to an executed instruction utilizing a memory address, whether the memory address is accessed for a first time using a first read data structure and
“In some embodiments, an initialization marker stored in a marker region 650 is an indication that the memory allocation containing the initialization marker has not been initialized and therefore, does not contain a known value (e.g., zeros) that has been encrypted. Accordingly, a particular value (e.g., all ones, all zeros, a random value, a deterministic value, etc.) may be loaded into a register in response to a memory access request to the uninitialized memory allocation” (Deutsch [0141] the register is the first read data structure and an uninitialized memory allocation would mean it’s being accessed for the first time)
when the memory address is accessed for the first time, to return one of a random value or a zero value, and
“In some embodiments, an initialization marker stored in a marker region 650 is an indication that the memory allocation containing the initialization marker has not been initialized and therefore, does not contain a known value (e.g., zeros) that has been encrypted. Accordingly, a particular value (e.g., all ones, all zeros, a random value, a deterministic value, etc.) may be loaded into a register in response to a memory access request to the uninitialized memory allocation” (Deutsch [0141])
when the memory address is not accessed for the first time, to return a value stored at the memory address; and
“If the marker region does not contain an initialization marker, then this indicates memory allocation is in an initialized state, and the data in the memory location pointed to by the indirect address 204 can be loaded and decrypted by data decrypting logic 165” (Deutsch [0098])
the first read data structure of one of the memory controller or cache to store information regarding a first read of a particular address of non-volatile memory.
“In some embodiments, an initialization marker stored in a marker region 650 is an indication that the memory allocation containing the initialization marker has not been initialized and therefore, does not contain a known value (e.g., zeros) that has been encrypted. Accordingly, a particular value (e.g., all ones, all zeros, a random value, a deterministic value, etc.) may be loaded into a register in response to a memory access request to the uninitialized memory allocation” (Deutsch [0141] the register is the first read data structure and an uninitialized memory allocation would mean it’s being accessed for the first time)
“If the current data of the marker region 652 matches the selected initialization marker, then this indicates that the memory allocation is not initialized. Accordingly, a predetermined value (e.g., all zeros, all ones, etc.) may be loaded into the register, rather than the contents from the 64B allocation 668” (Deutsch [0142] the register would be storing the information regarding the first read, the register is acting as a cache for the memory/allocation)
“In embodiments, the contents of marker regions 650 and bound marker locations 662, 664 may be loaded as a cache line (e.g., a 32-byte block, 64-byte block, or 128-byte block, 256-byte block or more, 512-byte block, or a block size equal to a power of two-bytes) into the cache of processor circuitry 630. In performing memory operations on contents of a marker region stored in the cache of processor circuitry 630, the memory controller circuitry 634 or other logic, e.g., in processor circuitry 630, can decrypt the contents (if the contents were stored in an encrypted form), compare the appropriate reference marker (e.g., security marker, initialization marker, start marker, stop marker) with the contents from the marker region 650 and bound marker locations 662, 664 stored on the cache line containing the requested memory address, and take appropriate action based on the results of the comparison” (Deutsch [0148])
Regarding Claims 5, 12, and 19, Deutsch further discloses wherein the executed instruction utilizing a memory address is a load instruction.
“When a memory access request (e.g., LOAD, MOV, etc.) is made to an address within the 64B allocation 668, the processor circuitry 530 determines the address of the marker region 652 of the 128B slot 654 to which the 64B allocation 668 is assigned, reads the current data at the determined address of the marker region 652, and compares the current data to the selected initialization marker, which may be stored in the state of a memory manager module (e.g., 144), for example” (Deutsch [0142])
Regarding Claims 7, 14, and 20, Deutsch further discloses wherein the executed instruction utilizing a memory address is a non-load instruction having an operand at the memory address.
“When a memory access request (e.g., LOAD, MOV, etc.) is made to an address within the 64B allocation 668, the processor circuitry 530 determines the address of the marker region 652 of the 128B slot 654 to which the 64B allocation 668 is assigned, reads the current data at the determined address of the marker region 652, and compares the current data to the selected initialization marker, which may be stored in the state of a memory manager module (e.g., 144), for example” (Deutsch [0142] MOV instructions would have an operand at the memory address)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4, 9, 11, 16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Deutsch (published August 05, 2021) in view of Idgunji (US 2015/0199176) (hereinafter Idgunji) (published July 16, 2015).
Regarding Claims 2, 9, and 16, Deutsch disclosed the apparatus of claim 1, system of claim 8, and method of claim 15, but does not explicitly state further comprising: a random number generator to generate random values.
Idgunji discloses further comprising: a random number generator to generate random values.
“A random number generator (RNG) is an algorithm or circuit operable to generate a sequence of numbers or symbols that bear no discernable relationship to one another, i.e., appear random. RNGs have many significant uses, including gaming, statistical analysis, simulation and, perhaps most crucially, cryptography” (Idgunji [0002])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of a random number generator in Idgunji with the memory system of Deutsch. The motivation for doing so would be to insure a more reliable and efficient source of randomness as described by Idgunji. “While algorithmic pseudo-random number generators ("PRNG"s) are capable of generating difficult-to-predict numbers, memory limitations force their output eventually to repeat. This compromises and renders them of limited use for particularly demanding applications” (Idgunji [0002]) “Introduced herein are various embodiments of an RO-based TRNG, a method of generating true random numbers and an RO-based TRNG system. In general, the embodiments employ a power supply that may be configured to time-vary the power supplied to the RO, increasing the entropy of its output. Certain of the embodiments employ a power supply having multiple outputs such that different voltages can be supplied to different components in the RO or associated circuitry” (Idgunji [0015])
Regarding Claims 4, 11, and 18, Deutsch disclosed the apparatus of claim 1, system of claim 8, and method of claim 15, but does not explicitly state further comprising: a random number generator circuitry to generate at least one random number to be used.
Idgunji discloses further comprising: a random number generator circuitry to generate at least one random number to be used.
“A random number generator (RNG) is an algorithm or circuit operable to generate a sequence of numbers or symbols that bear no discernable relationship to one another, i.e., appear random. RNGs have many significant uses, including gaming, statistical analysis, simulation and, perhaps most crucially, cryptography” (Idgunji [0002])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of a random number generator in Idgunji with the memory system of Deutsch. The motivation for doing so would be to insure a more reliable and efficient source of randomness as described by Idgunji. “While algorithmic pseudo-random number generators ("PRNG"s) are capable of generating difficult-to-predict numbers, memory limitations force their output eventually to repeat. This compromises and renders them of limited use for particularly demanding applications” (Idgunji [0002]) “Introduced herein are various embodiments of an RO-based TRNG, a method of generating true random numbers and an RO-based TRNG system. In general, the embodiments employ a power supply that may be configured to time-vary the power supplied to the RO, increasing the entropy of its output. Certain of the embodiments employ a power supply having multiple outputs such that different voltages can be supplied to different components in the RO or associated circuitry” (Idgunji [0015])
Claims 3, 10, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Deutsch (published August 05, 2021).
Regarding Claims 3, 10, and 17, Deutsch disclosed the apparatus of claim 1, system of claim 8, and method of claim 15, but does not explicitly state wherein whether to return one of a random value or a zero value is set by an execution of an instruction.
However Deutsch does discloses return one of a random value or a zero value
“In some embodiments, an initialization marker stored in a marker region 650 is an indication that the memory allocation containing the initialization marker has not been initialized and therefore, does not contain a known value (e.g., zeros) that has been encrypted. Accordingly, a particular value (e.g., all ones, all zeros, a random value, a deterministic value, etc.) may be loaded into a register in response to a memory access request to the uninitialized memory allocation” (Deutsch [0141])
and that memory access logic may be embodies as software.
“In other embodiments, portions of the secure memory access logic 150 may be embodied as hardware, firmware, software, or a combination thereof (e.g., as programming code executed by a privileged system component 142 of the computing device 100)” (Deutsch [0060])
However it would have been obvious to one of ordinary skill in the art to use an execution of an instruction to set the return one of a random value or a zero value. Deutsch already discloses that the particular value may be a random value or zero, and that memory access logic may be embodied as software. A POOSITA would know that software would use the execution of an instruction to set which parameters to use. The motivation to combine the use of the execution of an instruction to perform the setting would be increase adaptability and cost effectiveness. Software is easier to modify than hardware and it would be cheap and faster to develop software instructions than hardware to control the setting of the value returned.
Response to Arguments
Claim Rejections - 35 U.S.C. § 102
Applicant's arguments filed July 07, 2025 have been fully considered but they are not persuasive.
Applicant Argues:
a) (page 6 middle) Claim 1 has been amended to include language from claim 6. As such, the rejection for claim 6 is address. Deutsch, as cited, does not appear to at least describe "a first read data structure to store information regarding a first read of a particular address of non-volatile memory." The Office Action asserts that paragraph [0142] describes this clause. This paragraph state that "[w]hen a memory access request (e.g., LOAD, MOV, etc.) is made to an address within the 64B allocation 668, the processor circuitry 530 determines the address of the marker region 652 of the 128B slot 654 to which the 64B allocation 668 is assigned, reads the current data at the determined address of the marker region 652, and compares the current data to the selected initialization marker, which may be stored in the state of a memory manager module (e.g., 144), for example. If the current data of the marker region 652 matches the selected initialization marker, then this indicates that the memory allocation is not initialized." As such, this appears to require reading from memory, but not using a data structure in cache and/or a memory controller to determine a first read. Further, Applicant is not sure what citation the Office is using for the "memory access request" of Deutsch being a "first" memory access request. It appears that any time before the memory is initialized with data the same process of reading from memory occurs. Also, Deutsch appears to require writing a marker to memory which would be unnecessary using the claimed data structure.
With respect to (a), examiner has stated that the register is the “first read data structure” and is noted in the cited paragraphs [0141] and [0142] of the rejection above. Cited paragraph [0141] recites “a memory access request to the uninitialized memory allocation”, this memory request is the “first” memory access request as it is trying to access an uninitialized memory allocation. Paragraphs [0176]-[0177] helps clarify that an memory access to an uninitialized memory access request would cause the allocation to be initialized and for initialized allocations the memory access operations would proceed normally.
Furthermore paragraph [0142] states “a predetermined value (e.g., all zeros, all ones, etc.) may be loaded into the register, rather than the contents from the 64B allocation 668” which shows that the register is used in addressing the memory request and as a cache for the memory allocation if it was initialized. Furthermore paragraph [0148] also shows the loading of the contents of marker region into a cache line and a comparison being performed to determine the appropriate action for the memory access.
Claim Rejections - 35 U.S.C. § 103
No further arguments have been provided besides referring to the above argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137