DETAILED ACTION
Claims 1, 3, 5-8, 10, and 12-14 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 1, 3, 5-8, 10, and 12-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the memory control" in line 11. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of a “memory control” within the claim. For the sake of examination, Examiner will interpret this limitation to be “the memory controller”.
Claim 8 is rejected for the same reasons as claim 1.
Claim 1 recites the limitation “the execution circuitry” in line 12. There is insufficient antecedent basis for this limitation in the claim. It’s unclear if the limitation is referring to “execution circuitry outside of the memory controller” in claim 1, line 11, or “execution circuitry of the memory controller” in claim 1, line 9. For the sake of examination, Examiner will interpret this limitation to be referring to “execution circuitry outside of the memory controller” in claim 1, line 11.
Claim 8 is rejected for the same reasons as claim 1.
Claim 5 recites the limitation “the instruction” in line 1. There is insufficient antecedent basis for this limitation in the claim. It’s unclear if the limitation is referring to an “instance of a single instruction” in claim 1, line 2, or “a variant of the single instruction” in claim 1, lines 11-12. For the sake of examination, Examiner will interpret this limitation to be referring to the “instance of a single instruction” in claim 1, line 2.
Claim 12 is rejected for the same reasons as claim 5.
Claim 6 recites the limitation “the execution circuitry” in line 1. There is insufficient antecedent basis for this limitation in the claim. It’s unclear if the limitation is referring to “execution circuitry outside of the memory controller” in claim 1, line 11, or “execution circuitry of the memory controller” in claim 1, line 9. For the sake of examination, Examiner will interpret this limitation to be referring to “execution circuitry outside of the memory controller” in claim 1, line 11.
Claim 13 is rejected for the same reasons as claim 6.
Claim 7 recites the limitation “the execution circuitry” in line 1. There is insufficient antecedent basis for this limitation in the claim. It’s unclear if the limitation is referring to “execution circuitry outside of the memory controller” in claim 1, line 11, or “execution circuitry of the memory controller” in claim 1, line 9. For the sake of examination, Examiner will interpret this limitation to be referring to “execution circuitry outside of the memory controller” in claim 1, line 11.
Claim 14 is rejected for the same reasons as claim 7.
Claims 3, 5-7, 10, and 12-14 are rejected for inheriting the rejections of the claims in which they depend on.
Claim Rejections - 35 USC § 103
Claim(s) 1, 3, 5-6, 8, 10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. (US 20200264875 A1) in view of Pickett (US 6957322 B1) and Brewer (US 20190340155 A1).
Regarding claim 1, Williams teaches an apparatus (Fig. 1, exemplary data processing system 100) comprising:
decoder circuitry to decode a single instruction ([0006] and [0019]: Processing unit 102 of Fig. 1 may process AMO instructions, including the process of decoding the instruction, and then sends the AMO request to the cache memory or memory controller), the single instruction to include one or more fields for an opcode to indicate an arithmetic or Boolean operation, wherein the arithmetic or Boolean operation is to be performed by a memory controller ([0037], Fig. 3A and 3C: Opcode 102 defines when an AMO operation is to be executed and the opcode is to indicate what kind of operation is to be performed at the cache memory or memory controller), wherein a bit prefix of the single instruction is to indicate the memory controller is to perform the execution ([0037], Fig. 3A and 3B: Both figures contain a IC field 310 which acts as a prefix to indicate whether the memory controller or cache memory is to perform the AMO operations), and one or more fields to identify at least one source location (Fig 3A and 3C: contains a field Address 306);
execution circuitry of the memory controller to execute the decoded single instruction according to the opcode ([0037] and [0005]: to perform AMO operations at the memory controller, there must be an execution circuit located within in order to execute arithmetic operations); and
execution circuitry outside of the memory control .
Williams does not teach that the single instruction’s prefix is a multi-bit prefix.
Pickett teaches a multi-bit prefix that modifies an operation of an instruction (Col. 2, lines 6-11: A prefix byte (i.e., a multi-bit prefix), where each bit of the prefix byte modifies the instruction in which it’s attached to).
It would have been obvious to one of ordinary skill before the effective filing date to have combined the teachings of Williams with the teachings of Pickett to have taken the prefix features of Pickett and implement them on the prefix of Williams to make a multi-bit prefix. An instruction prefix is known in the art to modify the operation of an instruction (see Pickett Col. 2, lines 13-14). Therefore, one of ordinary skill would be inclined to have a longer word prefix to modify the operations of their instruction. For example, PHOSITA could add an additional bit to the prefix to change the address or operand size for the instruction, or to have the additional bit to perform a different basic operation if PHOSITA deems it necessary for the overall implementation of the memory controller.
Williams, in view of Pickett, still does not teach an execution circuitry outside of the memory control to support a variant of the single instruction that is to cause the execution circuitry to perform an arithmetic or Boolean operation based on the opcode regardless of a prefix.
Brewer teaches a processor core to support a variant of the single instruction that is to cause the processor core to perform an arithmetic or Boolean operation based on the opcode regardless of a prefix ([0055, 0205-0208] The HTP 300 may support an AMO instruction to perform floating-point operations (i.e., arithmetic operations), which is a variant of an AMO instruction that’s executable on a processor. Each of the floating point AMO instructions have an opcode and do not use a prefix, therefore the floating point AMOs are performed regardless of a prefix of the instruction that is executed by the memory controller).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Williams, in view of Pickett, with the teachings of Brewer to have the execution circuitry of the processor be able to support a floating point AMO instruction, a variant of an AMO instruction, to perform an arithmetic operation. There may be situations where the memory data may be located in a lower-level memory (e.g., L1 cache in the instance of Williams) rather than in a higher-level memory (e.g., L2 in the instance of Williams). Therefore, by performing the AMO request at the processor, memory data may be easily fetched, modified, and written back to memory faster than by having a memory controller/higher-level memory handle the AMO request, which may be appreciated by one of ordinary skill.
Regarding claim 3, Williams, in view of Pickett and Brewer, teaches the apparatus of claim 1, wherein the one or more fields to identify at least one source location is to identify a memory location (Williams, [0037], Fig. 3A and 3C, Address 306).
Regarding claim 5, Williams, in view of Pickett, teaches the apparatus of claim 1, wherein the instruction further comprises a field for an immediate value to be used during the operation (Williams, [0037], Fig. 3A and 3B: both figures contain a field Parameters 308 which can contain a value depending on the type value the instruction will need to execute, which may be an immediate value).
Regarding claim 6, Williams, in view of Pickett and Brewer, teaches the apparatus of claim 1, wherein the execution circuitry is arithmetic logic unit circuitry ([0034], Fig. 2, ALU 210).
Regarding claims 8, 10, and 12-13, the claim recites a system (Williams, [0018], Fig. 1, exemplary data Processing system 100) comprising: memory to store an instance of a single instruction (Williams, [0019], Fig. 2: Processing unit 102 processes instructions from the memory which stores an instance of AMO instructions), implements the apparatus according to claims 1, 3, and 5-6, respectively, and are therefore rejected on the same premises.
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. (US 20200264875 A1), in view of Pickett (US 6957322 B1), Brewer (US 20190340155 A1), and Nurvitadhi et al. (US 10186011 B2).
Regarding claim 7, Williams, in view of Pickett and Brewer, teaches the apparatus recited in claim 1.
Williams, in view of Pickett and Brewer does not explicitly teach having the execution circuitry be floating point unit circuitry.
Nurvitadhi teaches that the execution circuitry is floating point unit circuitry (Col. 44, lines 52-55: “In one embodiment the memory controller logic can include ALUs and/or FPU logic”).
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to substitute the ALU of Williams for an FPU circuit as disclosed in Nurvitadhi. Both an ALU and an FPU handle arithmetic computations, the only difference being that an ALU only handles natural numbers at a limited range depending on the architecture of the processor, whereas the FPU handles real numbers depending on the architecture. One of ordinary skill in the art who may want to represent their data as floating-point numbers may opt-in to use an FPU instead of an ALU (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Regarding claim 14, the claim recites a system corresponding to the apparatus of claim 7 and is therefore rejected on the same premises.
Response to Arguments
Applicant’s arguments, see page 6, second-to-last paragraph, to page 8, paragraph 3, filed February 4 2026, with respect to the rejections of claims 1, 3, 5-6, 8, 10, and 12-13 under 35 U.S.C. 101 have been fully considered and are persuasive. The rejections of claims 1, 3, 5-6, 8, 10, and 12-1-4 under 101 has been withdrawn.
Applicant’s arguments, see page 8, paragraph 4, filed February 4 2026, with respect to the rejections of claims 1, 3, 5-6, 8, 10, and 12-13 under 35 U.S.C 103 have been fully considered and are mostly persuasive.
Regarding arguments on page 9, paragraph 1, Applicant argues that there is no reason to make the prefix of Williams any longer because “while a PHOSITA certainly could add a bunch of functionality to any instruction, there is not a rationale for a PHOSITA to do so to the description of Williams because it simply is not necessary.”
Examiner respectfully disagrees with this argument. In response to Applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Examiner found the motivation to combine within Pickett as they state the uses of implementing one or more prefix bytes on an instruction (such as an AMO instruction in Williams) as they help define registers used in an instruction (i.e., identifying that a register comprises of a memory address) or set an addressing mode. In an exemplary case, PHOSITA may want one or more additional prefix bits to define one or more addressing modes for AMO instructions, in which these instructions performs operations in memory. Applicant’s motivation of the invention may differ from Examiner’s motivation for the combination of the prior art, but both motivations may produce the same invention and/or end product. Therefore, the remarks regarding lack of motivation to combine is considered not persuasive.
Although Applicant provided non-persuasive arguments, the rejections of claims 1, 3, 5-8, 10, and 12-14 has been withdrawn due to persuasive arguments with respect to the amendments to claim 1 and 8. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference(s) for claims 1, 3, 5-8, 10, and 12-14. See 103 rejections above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20190004810 A1: Jayasimha et al. teaches an atomic memory instruction being performed based on the address area the instructions fetches data from.
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/E.A./Examiner, Art Unit 2183
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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