DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 9/25/2025 is being considered by the examiner.
Specification
The abstract of the disclosure is objected to because the term “implicitly reference” should read “implicitly referenced”. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claims 1-14 are objected to under 37 CFR 1.75(a) for failing to particularly point out and distinctly claim the subject matter which the applicant regards as his invention or discovery.
Claim 1 recites “the random number storage” in line 8. There is insufficient antecedent basis for this limitation in the claim. For the purposes of prior art examination, Examiner is interpreting as “the dedicated random number storage”. Claim 8 is objected to for the same reason. Dependent claims are objected to for the same reason.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Alexander et al. (US 20200210192 A1, herein Alexander) and Pape (US 2016/0328209 A1, herein Pape) in view of Hoshaku (JP 2003114259 A).
Regarding claim 1, Alexander teaches the apparatus of claim 1 comprising:
decode circuitry to decode a single instruction ([0051]: The fetch stage 14 then passes the fetched instruction to the decode stage 16 to be decoded, and the decode stage 16 then passes an indication of the decoded instruction to the execution unit) at least having a field for an opcode, the opcode to indicate execution circuitry ([0064, [0068]: Based on the instruction’s opcode, which specifies its type, each instruction is dispatched via the decoding stage to the appropriate execution unit) is to perform an operation using implicitly referenced can be implicit to the instruction, meaning not requiring an operand to specify, and the location of the source in the WRF is inherent from the opcode) and execution circuitry to execute the decoded single instruction according to the opcode ([0064]: Each instruction is dispatched via the decoding stage to the appropriate execution unit based on the instruction’s opcode).
Alexander does not teach performing an operation using implicitly referenced random data in particular. Alexander does not teach that the random data is to be retrieved from dedicated random number storage that is to store a plurality of random numbers. Alexandar does not teach that the random number storage is part of a processor core.
Pape teaches a core with a dedicated random number storage (Fig. 2) to store random numbers generated by a random number generator (Fig 1 and Fig. 2, Paragraph 38). Pape also teaches random numbers being used for different operations (Paragraph 4).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement a dedicated random number storage in a core, with the random numbers used for different operations. One of ordinary skill in the art would be motivated to do so as the system would now be able to perform cryptographic operations, simulations, statistical sampling with random numbers (Pepe Paragraph 4). Having a dedicated storage in the core would provide quick access to random numbers as compared to accessing random numbers from a random number generator (Pepe Paragraph 5).
Though Pape teaches using random numbers in operations, the combination thus far does not teach performing the operation of Alexandar using implicitly referenced random data, retrieved from the dedicated random number storage.
Hoshaku teaches performing an operation using random data from a storage (Paragraphs 14-17, These paragraphs disclose that when the instruction to be tested by the LSI indicates a memory source operation, it uses random number generating means 102; and Paragraph 31: discloses that previously generated random numbers that are stored can be used as the operands instead of providing the random number generating means 102).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination by incorporating the teachings of Hoshaku to include operations to be performed is to specifically be using random data. Doing so would have provided additional functionality and flexibility to the processor by enabling support for operations involving random data without requiring explicit operands and also improving efficiency in applications such as the LSI test method disclosed in Hoshaku.
Regarding claim 2, Alexandar, Pape and Hoshaku teach the apparatus of claim 1, further comprising:
random number generator circuitry to generate the random data (Pape Figs.1 and 2).
Regarding claim 3, Alexander, Pape and Hoshaku teach the apparatus of claim 3, wherein the instruction is to include one or more fields to explicitly reference a source operand (Alexander Paragraph 69).
Regarding claim 4, Alexander, Pape and Hoshaku teach the apparatus of claim 1, wherein the instruction is to include one or more fields to explicitly reference a destination operand (Alexander Paragraph 69).
Regarding claim 5, Alexander, Pape and Hoshaku teach the apparatus of claim 1, wherein the operation is an arithmetic operation(Alexander paragraph 68).
Regarding claim 6, Alexander, Pape and Hoshaku teach the apparatus of claim 1, wherein the operation is a Boolean operation (Alexander [0068]: The instruction set of the processor 4 includes different types of arithmetic instructions for performing arithmetic operations which includes Boolean logic instructions).
Regarding claim 7, Alexander, Pape and Hoshaku teach the apparatus of claim 1. Although Pape teaches random numbers stored in a storage and Hoshaku teaches storage to store random numbers, the combination thus far does not explicitly teach that the random data is to be stored in a register to be implicitly referenced.
Alexander teaches storing plurality of data items in a register file (Fig. 4).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to store the random numbers in a register file. This would result in the random data being stored in a register to be implicitly referenced. One of ordinary skill in the art would be motivated to do so as registers provide quick access to data enabling better performance.
Claim 8 is a system claim corresponding to system claim 1. The difference is that Claim 8 recites “memory to store an instance of single instruction”. Alexander teaches memory to store an instance of the single instruction (Paragraph 52, instruction memory 12). Claim 8 is rejected for the same reasons as claim 1.
Claim 9-14 are system claims corresponding to system claims 2-7 and are rejected for the same reasons.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Alexander, Pape, Hoshaku and further in view of Charney (US 20180004523 A1).
Regarding claim 15, Alexander teaches a method comprising:
a single instruction at least having a field for an opcode ([0064, [0068]: Based on the instruction’s opcode, which specifies its type, each instruction is dispatched via the decoding stage to the appropriate execution unit), the opcode to indicate execution circuitry is to perform an operation using implicitly referenced single instruction ([0064]: Each instruction is dispatched via the decoding stage to the appropriate execution unit based on the instruction’s opcode).
Alexander does not teach performing an operation using implicitly referenced random data in particular. Alexander does not teach that the random data is to be retrieved from dedicated random number storage that is to store a plurality of random numbers. Alexander does not teach translating an instance of the single instruction from a first instruction set architecture to one or more instructions of a second instruction set architecture that are decoded and executed.
Pape teaches a dedicated random number storage (Fig. 2) to store random numbers generated by a random number generator (Fig 1 and Fig. 2, Paragraph 38). Pape also teaches random numbers being used for different operations (Paragraph 4).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement a dedicated random number storage, with the random numbers used for different operations. One of ordinary skill in the art would be motivated to do so as the system would now be able to perform cryptographic operations, simulations, statistical sampling with random numbers (Pepe Paragraph 4). Having a dedicated storage would provide quick access to random numbers as compared to accessing random numbers from a random number generator (Pepe Paragraph 5).
Though Pape teaches using random numbers in operations, the combination thus far does not teach performing the operation of Alexandar using implicitly referenced random data, retrieved from the dedicated random number storage. The combination thus far does not teach translating an instance of the single instruction from a first instruction set architecture to one or more instructions of a second instruction set architecture that are decoded and executed.
Hoshaku teaches performing an operation using random data from a storage (Paragraphs 14-17, These paragraphs disclose that when the instruction to be tested by the LSI indicates a memory source operation, it uses random number generating means 102; and Paragraph 31: discloses that previously generated random numbers that are stored can be used as the operands instead of providing the random number generating means 102).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination by incorporating the teachings of Hoshaku to include operations to be performed is to specifically be using random data. Doing so would have provided additional functionality and flexibility to the processor by enabling support for operations involving random data without requiring explicit operands and also improving efficiency in applications such as the LSI test method disclosed in Hoshaku.
The combination thus far still does not teach translating an instance of a single instruction from a first instruction set architecture to one or more instructions of a second instruction set architecture.
Charney teaches translating an instance of a single instruction from a first instruction set architecture to one or more instructions of a second instruction set architecture ([0107]: “an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the combination by incorporating the teachings of Charney to provide a method of translating an instance of a single instruction from a first instruction set architecture to one or more instructions of a second instruction set architecture. Doing so would enhance the flexibility and compatibility of a processor by enabling it to support and accommodate non-native instructions which is especially useful for backwards compatibility. Doing so may also result in an improved performance of the processor by allowing for a more efficient and streamlined implementation of the hardware, such as a simplified instruction decoder, which can reduce latency, lower power consumption, and enhance overall execution speed.
Regarding claim 16, Alexander, Pape, Hoshaku and Charney teach the method of claim 15, further comprising generating the random data (Pape Figs.1 and 2).
Regarding claim 17, Alexander, Pape, Hoshaku and Charney teach the method of claim 15, further comprising wherein the instruction includes one or more fields to explicitly reference a source operand (Alexander [0068-0069]: Each instruction includes one or more source operands specifying one or more source registers).
Regarding claim 18, Alexander, Pape, Hoshaku and Charney teach the method of claim 15, wherein the instruction is to include one or more fields to explicitly reference a destination operand (Alexander [0068-0069]: Each instruction includes one or more destination operands specifying one or more destination registers).
Regarding claim 19, Alexander, Pape, Hoshaku and Charney teaches the method of claim 15, wherein the operation is an arithmetic operation ([0049], [0068]).
Regarding claim 20, Alexander in view of Charney and Hoshaku teaches the method of claim 15. Alexander further teaches wherein the operation is a Boolean operation (Alexander [0068], [0049]).
Response to Arguments
The Applicant’s arguments, filed 9/24/2025, have been fully considered.
In view of the amendments to the independent claims, the rejection under 35 USC 101 has been withdrawn. The arguments are thus not applicable.
The Applicant’s argument, that Lie does not teach the limitations in the amended claims, is persuasive. Hence the rejections under Lie have been withdrawn.
The Applicant argues, on page 12, that the combination of Alexander with Hoshaku, is not proper, as the modification with Hoshaku does not improve encoding or efficiency. The Applicant’s argument is not persuasive. Instructions that use random data and implicitly specify the random data would reduce the length of the instruction as compared to instructions with explicitly addressed random data and also the location of the operand is retrieved from the opcode rather than having to decode another operand. The Applicant also argues that there is no evidence that random weights would work in Alexander’s system. This argument is also not persuasive, however, this argument is no longer applicable due to the new grounds of rejection necessitated by the amendments to the independent claims.
The Applicant’s argument that Alexander and Hoshaku do not teach “execution circuitry to execute the decoded instruction according to the opcode, wherein the random number storage is a part of a processor core” is persuasive. Hence the rejection has been withdrawn. Upon further consideration, a new rejection has been made in view of Pape (See rejections above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jyoti Mehta whose telephone number is (571)270-3995. The examiner can normally be reached on Monday-Thursday 8 am-6 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached on (571) 272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183