DETAILED ACTION
This office action is in response to an Request for Continued Examination filed 11/24/2025 for application 17/560,665 filed 12/23/2021.
Claims 1-2, 4-9, 12-16, and 19 have been amended. Claim 20 has been cancelled. Claim 21 is new. Thus, claims 1-19 and 21 have been examined.
The IDS sent 5/21/2025 has been considered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/28/2025 has been entered.
Allowable Subject Matter
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not teach ‘The apparatus of claim 1, wherein the proper subset of memory is a level of memory as indicated by at least one of an opcode or an immediate’.
Consistent with paragraph [0035] of the instant application, an opcode is a field in a request that identifies an operation to perform. Consistent with paragraph [0052] of the instant application, and immediate may be a value that indicts a level of memory to initialize, for example Lo = LO cache, L1 = L1 cache, L2=L2 cache, LLC = LLC cache, LM = random access, LVM = non-volatile memory’ sent in a command to the apparatus. Thus the “immediate” value might indicate the type of memory, as identified by a memory level, in a command received by an apparatus to initialize addressable memory to a random value or to zeros, where the apparatus comprises random number generator circuitry.
The closest prior art is Lasser that teaches in [0054] that each address is associated with a level of memory, thus the write command may send an address that identifies the proper subset of memory to initialize. But it does not teach an opcode or an immediate that identifies the proper subset of memory to initialize. The address of Lasser does not identify the operation to perform. Instead it contains an opcode that identifies the operation to perform for a range of data, and a separate field (an address) that indirectly identifies the level of the addressable memory. Thus Lasser does not teach ‘wherein the proper subset of memory is a level of memory as indicated by at least one of an opcode or an immediate’ within the context of claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-19 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Lasser (LASSER US 2016/0099065 A1).
Regarding claim 1, Lasser teaches An apparatus comprising: (Lasser [0096] discloses the invention may be embedded within an apparatus such as mobile telephone, a computer, a music player, etc.)
random number generator circuitry to generate a random number; (Lasser [0047] discloses the memory die 103 may generate random bit sequence of logic “0” bits and logic “1” bits. Lease [0023] discloses the random sequence in the memory die may be implemented as hardware, thus the random number generator is an example of circuitry (i.e. hardware).)
and a memory controller, (Lasser [0021]-[0022] discloses a memory controller manages the memory initialization an may determine if the pattern is initialized to all bits of a common value or to a random pattern or to a common value.) in response to a command, to initialize at least a proper subset of addressable memory to be one of all zeros or at least one random number (Examiner notes that the instant application does not have an explicit definition for the term ‘proper subset of memory’. Under broadest reasonable interpretation, Examiner has interpreted the phrase ‘proper subset of memory’ to be subset of memory affected by the command containing random data or 1s or 0s. Lasser [Abstract] and [0005]-[0006] discloses the system initializes data in a latch to a random pattern or common value in response to a write command, overwrites a portion of the latch data (leaving some of the data as either a random pattern or common value, and writes the latch data to memory. As noted in Lasser [0014] the latch data is a page of data that comprises a head, a portion overwritten, and a tail. The Head and Tail not overwritten is an example of the proper subset of addressable memory. Lasser [0048-[0049] discloses initialization circuitry 114 performs the initialization to random data or common value in response to a write command directed to an address that identifies a page and page offset within the page. See Lasser [0012]. )
to be generated by the random number generator circuitry. (Lasser [0047] discloses the memory die 103 may generate random bit sequence of logic “0” bits and logic “1” bits. Lease [0023] discloses the random sequence in the memory die may be implemented as hardware, thus the random number generator is an example of circuitry (i.e. hardware).)
Regarding claim 2, Lasser teaches all of the limitations of claim 1 above. Lasser further teaches wherein the command is to indicate whether the proper subset of addressable memory is to be initialized to be one of all zeros or at least one random number. (Lasser [0046]-[0049] and [0022] discloses the initialization circuitry 114 may be configured to load a set of “0” bits, to load at set of “1” bits, or to load random bits during initialization based on a write to an address that may be a page index and an opcode, where the opcode may identify what values to set the random or common value bits. Lasser [0049] discloses initialization circuitry 114 performs the initialization using operations (i.e. commands) that indicate if the memory is to be loaded with “0’s”, “1’s”, or random numbers.)
Regarding claim 3, Lasser teaches all of the limitations of claim 1 above. Lasser further teaches wherein the command is to be generated in response to an execution of an instruction. (Lasser [Abstract] and [0011] the initialization circuit issues a command to initialize the memory in response to a write operation, where the write operation is an example of an instruction.)
Regarding claim 4, Lasser teaches all of the limitations of claim 3 above. Lasser further teaches wherein the instruction is to have a field for an opcode to indicate execution circuitry is to generate the command to provide to the memory controller. (Lasser [0011] discloses the write process sends a write opcode. Lasser [0022] discloses the system may select between the two options using a write opcode.)
Regarding claim 5, Lasser teaches all of the limitations of claim 4 above. Lasser further teaches wherein the opcode is further to indicate whether the proper subset of addressable memory is to be initialized to be one of all zeros or at least one random number. (Lasser [0011] discloses the write process sends a write opcode. Lasser [0022] discloses the system may select between the two options using a write opcode. Lasser [0048]-[0049] and [0022] discloses the target is an address of the write command, thus the proper subset initialized and not overwritten in the word affected by the address in the write command is initialized as the proper subset of addressable memory.)
Regarding claim 6, Lasser teaches all of the limitations of claim 5 above. Lasser further teaches wherein the instruction further comprises an indication of an operand that is to store an indication of whether the proper subset of addressable memory is to be initialized to be one of all zeros or at least one random number. (Lasser [0011] discloses the write process sends a write opcode. Lasser [0021]-[0022] discloses the system may select between the two options (a random pattern and common value)using a write opcode. Lasser [0061] discloses a common value may be a set of “0” bits or a set of “1” bits. Lasser [0048][0049] discloses the write command may indicate an address associated with the write operation that is the target of the write. Thus the write operands indicate if the system is to store to a random pattern or a common value of a set of “0” bits (i.e. all zeros).)
Regarding claim 7, Lasser teaches all of the limitations of claim 5 above. Lasser further teaches wherein the instruction further comprises an immediate that is to encode an indication of whether the proper subset of addressable memory is to be initialized to be one of all zeros or at least one random number. (Examiner notes that the instant application does not contain an explicit definition of “an immediate”. Consistent with paragraphs [0048]-[0049] an immediate is a value that identifies if the memory is to be initialized to all zeros or at least one random number and further discloses the write contains an address to be written. Lasser [0011] discloses the write process sends a write opcode. Lasser [0021]-[0022] discloses the system may select between the two options (a random pattern and common value)using a write opcode. Lasser [0061] discloses a common value may be a set of “0” bits or a set of “1” bits. Thus the write operands indicate if the system is to store to a random pattern or a common value of a set of “0” bits (i.e. all zeros). Thus the write opcode of Lasser is an example of an immediate that indicates if the memory is to be initialized to one of all zeros or at least one random number according to the address sent in the write command, which identifies addressable memory.)
Regarding claim 8, Lasser teaches A system (Lasser [0034] discloses the inventio is directed to a system.) comprising: addressable memory to store data; (Lasser Fig. 1 and supporting para [0027] discloses the system contains Memory 104. Lasser [0048]-[0049] discloses it is addressable memory.)
The remainder of claim 8 recites limitations described in claim 1 above and thus is rejected based on the teaching and rationale of claim 1 above.
Regarding claim 9, Lasser teaches all of the limitations of claim 8 above.
The remainder of claim 9 recites limitations described in claim 2 above and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 10, Lasser teaches all of the limitations of claim 8 above.
The remainder of claim 10 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale of claim 3 above.
Regarding claim 11, Lasser teaches all of the limitations of claim 10 above.
The remainder of claim 11 recites limitations described in claim 4 above and thus is rejected based on the teaching and rationale of claim 4 above.
Regarding claim 12, Lasser teaches all of the limitations of claim 11 above.
The remainder of claim 12 recites limitations described in claim 5 above and thus is rejected based on the teaching and rationale of claim 5 above.
Regarding claim 13, Lasser teaches all of the limitations of claim 11 above.
The remainder of claim 13 recites limitations described in claim 6 above and thus is rejected based on the teaching and rationale of claim 6 above.
Regarding claim 14, Lasser teaches all of the limitations of claim 11 above.
The remainder of claim 14 recites limitations described in claim 7 above and thus is rejected based on the teaching and rationale of claim 7 above.
Regarding claim 15, Lasser teaches A method (Lasser [Abstract] discloses the invention is directed to method of processing write commands)
comprising: generating a command to indicate to a memory controller to initialize at least a proper subset of addressable memory (Examiner notes that the instant application does not have an explicit definition for the term ‘proper subset of memory’. Under broadest reasonable interpretation, Examiner has interpreted the phrase ‘proper subset of memory’ to be subset of memory affected by the command containing random data or 1s or 0s. Lasser [Abstract] and [0005]-0006] discloses the system initializes data in a latch to a random pattern or common value in response to a write command, overwrites a portion of the latch data (leaving some of the data as either a random pattern or common value, and then writing the latch data to memory. As noted in Lasser [0014] the latch data is a page of data that comprises a head, a portion overwritten, and a tail. The Head and Tail not overwritten is an example of the proper subset of addressable memory. Lasser [0048-[0049] discloses initialization circuitry 114 performs the initialization to random data or common value in response to a write command directed to an address that identifies a page and page offset within the page. See Lasser [0012]. )
to be one of all zeros or at least one random number; (Lasser [0046]-[0049] and [0022] discloses the initialization circuitry 114 may be configured to load a set of “0” bits, to load at set of “1” bits, or to load random bits during initialization based on a write to an address that may be a page index and an opcode, where the opcode may identify what values to set the random or common value bits. Lasser [0049] discloses initialization circuitry 114 performs the initialization using operations (i.e. commands) that indicate if the memory is to be loaded with “0’s”, “1’s”, or random numbers.)
in the memory controller, in response to a command, initializing at least a proper subset of addressable memory to be one of all zeros or at least one random number. (Lasser [0031] discloses that the memory controller selects a pattern to write to the memory and the pattern may be a random pattern or a common value, thus to at least one random number. Lasser [0048]-[0049] discloses the target that is initialized is addressable memory.)
Regarding claim 16, Lasser teaches all of the limitations of claim 15 above.
The remainder of claim 16 recites limitations described in claim 2 above and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 17, Lasser teaches all of the limitations of claim 15 above.
The remainder of claim 17 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale of claim 3 above.
Regarding claim 18, Lasser teaches all of the limitations of claim 17 above.
The remainder of claim 18 recites limitations described in claim 4 above and thus is rejected based on the teaching and rationale of claim 4 above.
Regarding claim 19, Lasser teaches all of the limitations of claim 18 above.
The remainder of claim 19 recites limitations described in claim 5 above and thus is rejected based on the teaching and rationale of claim 5 above.
Response to Remarks
Examiner thanks Applicant for their Remarks of 11/24/2025. They have been fully considered. However, Applicant’s remarks with respect to claims 1-20 are not persuasive in light of the rejection above and remarks detailed below.
Applicant argues on page 5 of their remarks ‘First, Applicant is a bit confused as to the Response to Office Action section. The rejection for these claims is based on Lasser, and Lasser alone. Discussions of slides from a processor are not relevant to the rejection. Applicant notes that if the rejection is to be a combination, then the Office Action is not consistent with the interest of compact prosecution and the Office would be engaging in "piecemeal examination" which the MPEP says is to be avoided (see, e.g., MPEP 707.07(g).)”
Examiner agrees that the rejection is based on Lasser, and Lasser alone. Examiner included Mutlu to show analogous art that a POSITA would understand and that the data in the temporary buffer is indeed written to memory. This is in response to applicant’s argument ‘what Lasser is initializing is the latch (not memory)’. However, Mutlu is not required and Examiner will limit the response to Lasser along.
Applicant argues on page 5 of their remarks ‘Second, Applicant does not understand the Office's rationale that a "latch" may be considered memory and Lasser does not share the Office's opinion. For example, cited paragraph [0005] states that a "memory die may include a memory, a latch, and initialization circuitry that initializes the latch for a write operation that writes information to the memory." Lasser is clearly not equating a latch to memory as he lists them as separate components of a memory die. As noted by MPEP 2141.02, "[a] prior art reference must be considered in its entirety" and Lasser does not agree with the Office's "BRI" and the Office does not get to override the reference it is citing.’
Examiner respectfully disagrees. As noted by the underlined text provided by Applicant in their remarks “memory die… initialization circuitry that initializes the latch for a write operation that writes information to the memory”. Thus while the latch and memory are separate components, the purpose of the latch is to temporarily hold data to be written to memory. Applicant is misrepresenting Examiners remarks when Applicant states ‘a “latch” may be considered memory”. The latch of Lasser is a temporary storage area for data that is then written to memory. The latch contains the claimed random data or the claimed sequence of “1”s and “0”s.
Applicant further argues on page 5 of their remarks ‘Third, the Office Action is mixing-and-matching the prior art discussed in Lasser with what Lasser teaches. For example, the Office Action cites paragraph [0019] which is a discussion of prior art. Paragraphs [0021], etc. are discussing the invention. Lasser does not appear to want the prior art to be his invention and provides no rationale for combing his discussion of the prior art with his invention.’
Examiner respectfully notes that paragraph [0019] is not, and has not previously been, cited as prior art in the rejection. Paragraph [0019] is not within the Background section which is paragraphs [0002]-[0004]. Paragraph [0019] is within the “Detailed Description” section of Lasser. The paragraph summarizes inventive concepts of the application and states ‘Some memory controllers insert randomized “dummy” data within user data so that unused portions of a page are programmed with the dummy data (instead of programming a common state to the unused portions of the page). For example, an unused head or tail of a page may be programmed with dummy data (instead of being programmed based on the initialized state of the latch). The dummy data may be latched into the latch and programmed’. This text summarizes inventive concepts of Lasser.
This is restating portions of the Abstract ‘The memory die includes a memory and a latch. A method may include receiving a command corresponding to a write operation to write information to the memory. The method may further include loading a set of bits into the latch prior to receiving the information at the memory die…. The method further includes receiving the information at the memory die and overwriting at least a portion of the set of bits at the latch with the information’. Examiner notes that the text describes that for some examples only a portion of the latch is overwritten. The portion not overwritten (the head or tail portion) is written to the memory.
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What Lasser is doing is:
Receiving a write command
In response to the write command, initializing a latch to random data or 0s or 1s
Overwriting a portion of the data in the latch with data from the write command based on the offset within the page address and the length of the data to write. For example the middle portion in the diagram above.
Write the full page to memory.
Thus, when Lasser writes the page as shown above, it is writing random data and/or a sequence of 0s or 1s in the header and trail data section of the page, which forms the ‘proper subset of addressable data’ which is addressed on a page basis.
This is again summarized in [0023] ‘In accordance with the present disclosure, data stored in any unwritten portion of a page (such as a head portion or a tail portion of the page) may be randomized without requiring sending dummy data into the memory die and without consuming energy and time associated with transferring the dummy data. Certain examples are described below for illustration and are not intended to be limiting.’ Thus Lasser teaches The memory die may include hardware and/or instructions to generate and/or to store a random sequence of bits that are to be inserted into the input latch as needed given the data to write may be only a part of the page to be written in order to offload the process of inserting random bits or constant bits such as 0s or s in the head and tail of the page from the host to the memory device.
This concept is reiterated in paragraph [0059] ‘In any of the foregoing examples, the initialization circuitry 114 may be configured to initialize the latch 110 by loading the set of bits 116 into the latch 110 in response to receiving the command 120. After the initialization circuitry 114 initializes the latch 110 (e.g., after completion of the initialization process), the controller 130 may initiate a write operation at the memory die 103.… The controller 130 may initiate the write operation by sending the information 122 to the memory die 103. The information 122 may overwrite at least a portion of the set of bits 116 in the latch 110 (e.g., by altering one or more values)’, where per [0048] the information 122 may be data from the write request.’
See also Fig. 4 that discloses the system receives a write command. Prior to receiving the data from the write command the system initializes the latch (with random or controlled data), the system receives the data to write at step 406, and overwrites a portion of the data in the latch at step 408. This data containing the head, the overwritten portion, and the tail is then written to the memory.
Applicant further argues on page 5 of their remarks ‘Fourth, Applicant believes
there is a misunderstanding of what Lasser is describing. Lasser describes that prior to receiving information to write at the memory die, a latch is set. In other words, the latch is initialized. However, the information from the initialized latch is NOT what is written to memory, at least not in its entirety. This is clear from the claims (e.g., "overwriting at least a portion of the set of bits at the latch with the information."), figure 4.
Examiner respectfully notes that cited paragraph makes clear that “a portion of the set of bits” in the page are overwritten and the head and tail as detailed in the arguments above are written to the memory where the head and tail represent “a proper subset of a addressable memory” that is page addressable.
Applicant further argues on page 6 of their remarks ‘overwriting at least a portion of the set of bits at the latch with the information, at 408" and "After loading the information 122 in the latch 110, the memory die 103 may program the information 122 to the memory 104, such as by causing the read/write circuitry 112 to write values stored in the latch 110 to storage elements of the memory 104 (e.g., based on a physical address indicated by the command 120)."), and other discussions in Lasser (e.g., "After the set of bits is loaded into the latch, the information to be written to the memory may be provided to the latch (e.g., to overwrite the set of bits) by a controller of the data storage device or by a host device."). Simply put, Lasser initializes a latch, overwrites at least portion of the latch, and then writes the latch (with the overwritten data) into memory. At no point does Lasser describe simply writing the latch to memory.’
Examiner respectfully notes applicant is arguing a limitation not claimed. The claims do not recite “simply writing the data to memory” as if the data goes directly to memory without any temporary storage. The claims require writing ‘a proper subset’ of addressable memory that may be one of all zeros, or at least one random number. As noted in the response, under broadest reasonable interpretation, Examiner has interpreted the phrase ‘proper subset of memory’ to be a subset of memory affected by the command containing random data or 1s or 0s. The memory may be accessed using an address such as a page address. Lasser teaches the claimed limitations when it writes the header and tail portions of the page.
Applicant further argues on page 6 of their remarks ‘For example, Lasser does not at least describe "a memory controller, in response to a command, to initialize at least a proper subset of addressable memory to be one of all zeros or at least one random number to be generated by the random number generator circuitry." As noted above, and discussed at length in Lasser, Lasser writes a set of bits to a latch (which is not addressable memory or considered memory by Lasser), at least a portion of this set of bits is overwritten with information (information 122), and then the overwritten latch is written to memory. That is not initializing addressable memory to be a particular value. Rather, that is simply describing Lasser's particular write technique.’
Examiner respectfully disagrees. As detailed above, Lasser is:
Receiving a write command
In response to the write command, initializing a latch to random data or 0s or 1s
Overwriting a portion of the data in the latch with data from the write command based on the offset within the page address and the length of the data to write.
Write the full page to memory.
Thus Lasser creates a page in memory similar to the diagram below, and write the page to memory at the page address associated with the data to be written that was received in a write command.
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This is initializing addressable memory to be a particular value as claimed.
Applicant’s arguments with respect to independent claims 8 and 15 all rely upon perceived errors in claim 1 and thus have been addressed with the rejection and remarks relating to claim 1 above.
Applicant’s arguments with respect to dependent claims 2-7, 9-14, and 16-19 all reply upon perceived errors in their respective base claims and have been addressed with the rejection and remarks relating to their base claims above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
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/JANICE M. GIROUARD/Examiner, Art Unit 2138