DETAILED ACTION
This office action is in response to an Amendment/Request for Reconsideration-After Non-Final Rejection filed 5/28/2026 for application 17/560,665 filed 12/28/2021.
Claim 20 has been cancelled. No claims are new. Thus, claims 1-19 and 21 have been examined.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Allowable Subject Matter
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not teach ‘The apparatus of claim 1, wherein the proper subset of memory is a level of memory as indicated by at least one of an opcode or an immediate’.
Consistent with paragraph [0035] of the instant application, an opcode is a field in a request that identifies an operation to perform. Consistent with paragraph [0052] of the instant application, an immediate may be a value that indicts a level of memory to initialize, for example L0 = LO cache, L1 = L1 cache, L2=L2 cache, LLC = LLC cache, LM = random access, LVM = non-volatile memory’ sent in a command to the apparatus. Thus the “immediate” value might indicate the type of memory, as identified by a memory level, in a command received by an apparatus to initialize addressable memory to a random value or to zeros, where the apparatus comprises random number generator circuitry.
The closest prior art is Lasser that teaches in [0054] that each address is associated with a level of memory, thus the write command may send an address that identifies the proper subset of memory to initialize. But it does not teach an opcode or an immediate value within the command that identifies the proper subset of memory to initialize. The address of Lasser does not identify the operation to perform. Instead it contains an opcode that identifies the operation to perform for a range of data, and a separate field (an address) that indirectly identifies the level of the addressable memory. Thus Lasser does not teach ‘wherein the proper subset of memory is a level of memory as indicated by at least one of an opcode or an immediate’ within the context of claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-19 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Lasser (LASSER US 2016/0099065 A1).
Regarding claim 1, Lasser teaches An apparatus comprising: (Lasser [0096] discloses the invention may be embedded within an apparatus such as mobile telephone, a computer, a music player, etc.)
random number generator circuitry to generate a random number; (Lasser [0047] discloses the memory die 103 may generate random bit sequence of logic “0” bits and logic “1” bits. Lease [0023] discloses the random sequence in the memory die may be implemented as hardware, thus the random number generator is an example of circuitry (i.e. hardware).)
and a memory controller, (Lasser [0021]-[0022] discloses a memory controller manages the memory initialization an may determine if the pattern is initialized to all bits of a common value or to a random pattern or to a common value.) in response to a command, to initialize at least a proper subset of addressable memory to be one of all zeros or at least one random number (Examiner notes that the instant application does not have an explicit definition for the term ‘proper subset of memory’. Under broadest reasonable interpretation, Examiner has interpreted the phrase ‘proper subset of memory’ to be subset of memory affected by the command containing random data or 1s or 0s. Lasser [Abstract] and [0005]-[0006] discloses the system initializes data in a latch to a random pattern or common value in response to a write command, overwrites a portion of the latch data (leaving some of the data as either a random pattern or common value, and writes the latch data to memory. As noted in Lasser [0014] the latch data is a page of data that comprises a head, a portion overwritten, and a tail. The Head and Tail not overwritten is an example of the proper subset of addressable memory. Lasser [0048]-[0049] discloses initialization circuitry 114 performs the initialization to random data or common value in response to a write command directed to an address that identifies a page and page offset within the page. See Lasser [0012] that discloses the write command is to an address, thus to addressable memory. )
to be generated by the random number generator circuitry. (Lasser [0047] discloses the memory die 103 may generate random bit sequence of logic “0” bits and logic “1” bits. Lease [0023] discloses the random sequence in the memory die may be implemented as hardware, thus the random number generator is an example of circuitry (i.e. hardware).)
Regarding claim 2, Lasser teaches all of the limitations of claim 1 above. Lasser further teaches wherein the command is to indicate whether the proper subset of addressable memory is to be initialized to be one of all zeros or at least one random number. (Lasser [0046]-[0049] and [0022] discloses the initialization circuitry 114 may be configured to load a set of “0” bits, to load at set of “1” bits, or to load random bits during initialization based on a write to an address that may be a page index and an opcode, where the opcode may identify what values to set the random or common value bits. Lasser [0049] discloses initialization circuitry 114 performs the initialization using operations (i.e. commands) that indicate if the memory is to be loaded with “0’s”, “1’s”, or random numbers.)
Regarding claim 3, Lasser teaches all of the limitations of claim 1 above. Lasser further teaches wherein the command is to be generated in response to an execution of an instruction. (Lasser [Abstract] and [0011] the initialization circuit issues a command to initialize the memory in response to a write operation, where the write operation is an example of an instruction.)
Regarding claim 4, Lasser teaches all of the limitations of claim 3 above. Lasser further teaches wherein the instruction is to have a field for an opcode to indicate execution circuitry is to generate the command to provide to the memory controller. (Lasser [0011] discloses the write process sends a write opcode. Lasser [0022] discloses the system may select between the two options using a write opcode.)
Regarding claim 5, Lasser teaches all of the limitations of claim 4 above. Lasser further teaches wherein the opcode is further to indicate whether the proper subset of addressable memory is to be initialized to be one of all zeros or at least one random number. (Lasser [0011] discloses the write process sends a write opcode. Lasser [0022] discloses the system may select between the two options using a write opcode. Lasser [0048]-[0049] and [0022] discloses the target is an address of the write command, thus the proper subset initialized and not overwritten in the word affected by the address in the write command is initialized as the proper subset of addressable memory.)
Regarding claim 6, Lasser teaches all of the limitations of claim 5 above. Lasser further teaches wherein the instruction further comprises an indication of an operand that is to store an indication of whether the proper subset of addressable memory is to be initialized to be one of all zeros or at least one random number. (Lasser [0011] discloses the write process sends a write opcode. Lasser [0021]-[0022] discloses the system may select between the two options (a random pattern and common value)using a write opcode. Lasser [0061] discloses a common value may be a set of “0” bits or a set of “1” bits. Lasser [0048][0049] discloses the write command may indicate an address associated with the write operation that is the target of the write. Thus the write operands indicate if the system is to store to a random pattern or a common value of a set of “0” bits (i.e. all zeros).)
Regarding claim 7, Lasser teaches all of the limitations of claim 5 above. Lasser further teaches wherein the instruction further comprises an immediate that is to encode an indication of whether the proper subset of addressable memory is to be initialized to be one of all zeros or at least one random number. (Examiner notes that the instant application does not contain an explicit definition of “an immediate”. Consistent with paragraphs [0048]-[0049] an immediate is a value that identifies if the memory is to be initialized to all zeros or at least one random number and further discloses the write contains an address to be written. Lasser [0011] discloses the write process sends a write opcode. Lasser [0021]-[0022] discloses the system may select between the two options (a random pattern and common value)using a write opcode. Lasser [0061] discloses a common value may be a set of “0” bits or a set of “1” bits. Thus the write operands indicate if the system is to store to a random pattern or a common value of a set of “0” bits (i.e. all zeros). Thus the write opcode of Lasser is an example of an immediate that indicates if the memory is to be initialized to one of all zeros or at least one random number according to the address sent in the write command, which identifies addressable memory.)
Regarding claim 8, Lasser teaches A system (Lasser [0034] discloses the inventio is directed to a system.) comprising: addressable memory to store data; (Lasser Fig. 1 and supporting para [0027] discloses the system contains Memory 104. Lasser [0048]-[0049] discloses it is addressable memory.)
The remainder of claim 8 recites limitations described in claim 1 above and thus is rejected based on the teaching and rationale of claim 1 above.
Regarding claim 9, Lasser teaches all of the limitations of claim 8 above.
The remainder of claim 9 recites limitations described in claim 2 above and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 10, Lasser teaches all of the limitations of claim 8 above.
The remainder of claim 10 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale of claim 3 above.
Regarding claim 11, Lasser teaches all of the limitations of claim 10 above.
The remainder of claim 11 recites limitations described in claim 4 above and thus is rejected based on the teaching and rationale of claim 4 above.
Regarding claim 12, Lasser teaches all of the limitations of claim 11 above.
The remainder of claim 12 recites limitations described in claim 5 above and thus is rejected based on the teaching and rationale of claim 5 above.
Regarding claim 13, Lasser teaches all of the limitations of claim 11 above.
The remainder of claim 13 recites limitations described in claim 6 above and thus is rejected based on the teaching and rationale of claim 6 above.
Regarding claim 14, Lasser teaches all of the limitations of claim 11 above.
The remainder of claim 14 recites limitations described in claim 7 above and thus is rejected based on the teaching and rationale of claim 7 above.
Regarding claim 15, Lasser teaches A method (Lasser [Abstract] discloses the invention is directed to method of processing write commands)
comprising: generating a command to indicate to a memory controller to initialize at least a proper subset of addressable memory (Examiner notes that the instant application does not have an explicit definition for the term ‘proper subset of memory’. Under broadest reasonable interpretation, Examiner has interpreted the phrase ‘proper subset of memory’ to be subset of memory affected by the command containing random data or 1s or 0s. Lasser [Abstract] and [0005]-0006] discloses the system initializes data in a latch to a random pattern or common value in response to a write command, overwrites a portion of the latch data (leaving some of the data as either a random pattern or common value, and then writing the latch data to memory. As noted in Lasser [0014] the latch data is a page of data that comprises a head, a portion overwritten, and a tail. The Head and Tail not overwritten is an example of the proper subset of addressable memory. Lasser [0048-[0049] discloses initialization circuitry 114 performs the initialization to random data or common value in response to a write command directed to an address that identifies a page and page offset within the page. See Lasser [0012]. )
to be one of all zeros or at least one random number; (Lasser [0046]-[0049] and [0022] discloses the initialization circuitry 114 may be configured to load a set of “0” bits, to load at set of “1” bits, or to load random bits during initialization based on a write to an address that may be a page index and an opcode, where the opcode may identify what values to set the random or common value bits. Lasser [0049] discloses initialization circuitry 114 performs the initialization using operations (i.e. commands) that indicate if the memory is to be loaded with “0’s”, “1’s”, or random numbers.)
in the memory controller, in response to a command, initializing at least a proper subset of addressable memory to be one of all zeros or at least one random number. (Lasser [0031] discloses that the memory controller selects a pattern to write to the memory and the pattern may be a random pattern or a common value, thus to at least one random number. Lasser [0048]-[0049] discloses the target that is initialized is addressable memory.)
Regarding claim 16, Lasser teaches all of the limitations of claim 15 above.
The remainder of claim 16 recites limitations described in claim 2 above and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 17, Lasser teaches all of the limitations of claim 15 above.
The remainder of claim 17 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale of claim 3 above.
Regarding claim 18, Lasser teaches all of the limitations of claim 17 above.
The remainder of claim 18 recites limitations described in claim 4 above and thus is rejected based on the teaching and rationale of claim 4 above.
Regarding claim 19, Lasser teaches all of the limitations of claim 18 above.
The remainder of claim 19 recites limitations described in claim 5 above and thus is rejected based on the teaching and rationale of claim 5 above.
Response to Remarks
Examiner thanks Applicant for their Remarks of 5/28/2026. They have been fully considered. However, they are not persuasive in light of the rejection above and remarks detailed below.
Applicant argues on page 5 of their remarks ‘The Examiner's rejection relies on Lasser's technique of writing a page where a head or tail portion contains dummy data (e.g., random bits or zeros) and the middle portion contains user data. The Examiner asserts that this constitutes "initializing" a proper subset of addressable memory. Applicant respectfully submits that this stretches the term "initialize" beyond its broadest reasonable interpretation. As understood in the art, initializing memory refers to priming or setting a block of memory to a known state (e.g., all zeros or random data) prior to its use (such as allocating a memory chunk for a program). It does not mean simply performing a conventional write operation where user data is padded with dummy bits to fill a page boundary. Lasser explicitly describes its method as a "write operation to write information to a memory" (Lasser at paragraph [0005]). Because Lasser merely writes user data to memory with dummy data padding, it does not disclose a memory controller that initializes addressable memory as claimed.”
Examiner respectfully disagrees. Examiner notes that Lasser is initializing memory, as Lasser states numerous times. The text “initializ” appears 122 times in a review of the Lasser application. See Lasser [0005] “initialization circuitry that initializes the latch for a write operation that writes information to the memory”. Lasser [0048] “The initialization circuitry 114 may be configured to perform the initialization process in response to receiving a command 120 from the controller 130. The command 120 indicates that a write process that writes the information 122 to the memory 104 is to occur. For example, the command 120 may indicate that the write process is scheduled to occur and that the memory die 103 is to initialize the latch 110 to receive the information 122. The command 120 may indicate an address associated with the write operation that is to write the information 122 to the memory 104 (e.g., a physical address of a page of the memory 104, such as a page index associated with the page). Alternatively or in addition, the command 120 may indicate a write opcode associated with the write operation.” Thus Lasser performs an initialization process that places information 122 that may contain portions with randomized data per Lasser [0023] or is filled with “0”s or “1”s per Lasser [0047] and is directed to addressable memory.
Clearly Lasser is initializing addressable memory associated with a write command. This is not stretching the meaning of the term “initialization” beyond its reasonable interpretation. This is simply recognizing that Lasser states it is performing an initialization process, that includes initializing a proper subset of addressable memory with either random data or “0”s or “1”s.
Applicant’s claim language does not preclude writing data. To the contrary, the instant application paras [0055]-[0058] discloses the instant application is writing to the memory. The step of writing to memory does not mean the system is not initializing memory. A write command may store the desired data (such as zeros or random data) that is written to memory. Performing a write does not negate the fact that Lasser is initializing addressable memory, which applicant appears to suggest with their argument “Lasser merely writes user data to memory with dummy data padding”.
Applicant further argues on page 5 of their remarks ‘Second, Lasser discloses initializing a latch, which is structurally and functionally distinct from the claimed "addressable memory." The Office relies on Lasser's initialization of a latch (e.g., Lasser at paragraph [0005]: "initialization circuitry that initializes the latch"). However, Lasser explicitly distinguishes between the latch and the memory, stating that "[a] data storage device includes a memory die. The memory die may include a memory, a latch, and initialization circuitry..." (Lasser at paragraph [0005]). The latch in Lasser is a temporary, non- addressable buffer used during the write process. While the Office argues that the latch's contents are subsequently written to the memory, this subsequent write is a standard programming operation, not an initialization of the addressable memory itself. A prior art reference must be considered in its entirety, and the Office cannot redefine Lasser's latch as the claimed addressable memory when Lasser itself maintains them as separate, distinct components.’
Examiner respectfully notes that, as applicant acknowledges, writing to the latch is writing to a temporary location, and the data in the temporary location is written to the memory at the address of the write command, thus to addressable memory. Thus the addressable memory is initialized as claimed. The office action does not redefine Lasser’s latch as the claimed addressable memory as applicant argues. The office action discloses writing the data to the addressable memory, based on the address of the write command.
Applicant further argues on page 6 of their remarks ‘In other words, while the latch is initialized with some data per Lasser that is the only thing initialized. Yes, that data may be written to memory”.
Examiner respectfully notes applicants remarks are contradictory. Applicant acknowledges that the data from the latch is written to memory. Writing the “initialized” data in the latch to memory is initializing the memory with the “initialized” latch data. It is not true “while the latch is initialized with some data per Lasser that is the only thing initialized”.
Applicant further argues on page 6 of their remarks ‘but there is no evidence that a PHOSITA would ever consider initializing a first component (a latch) to also be initializing a second component (memory coupled to the latch).
Examiner respectfully notes it is not required to argue a POSITA would initialize a first component (a latch) to also be initializing a second component (memory coupled to the latch) at Lasser directly teaches this step. Thus Lasser teaches the claimed “initialize at least a proper subset of addressable memory to be one or all zeros or at least one random number”.
Furthermore, Examiner notes a POSITA would indeed envision initializing a first temporary component before storing the data from a temporary component into the memory. As noted in the Final Rejection of 5/22/2025, DRAM devices do not directly write data into the memory without going through a temporary buffer, often referred to as a row buffer. This is detailed in slides presented by Professor Onur Mutlu for class 18-447 titled “18-447 Computer Architecture Lecture 21: Main Memory” attached to this application 5/22/2025 which is a presentation that is to explain main memory/DRAM memory operations. Thus a POSITA would have taken a course similar to that offered by Professor Onur Mutlu and would understand that data is first be stored in a temporary row buffer and then written to the DRAM memory. This is the normal process of writing to DRAM memory. Again, evidence is not required ‘that a PHOSITA would ever consider initializing a first component (a latch) to also be initializing a second component (memory coupled to the latch).’. However, if it was required, it is disclosed by Onur Mutlu in the slides attached to this office action 5/22/2025.
Applicant argues on page 6 of their remarks ‘And as the Office noted, not even all of the latched data is written from the latch to memory. How can the alleged "initialization" use different data?”
Examiner respectfully disagrees. Applicant has not provided a page reference to where applicant believes Examiner argues “not even all of the latched data is written from the latch to memory”. Examiner has not made this argument. Instead, on page 15 of the office action, Examiner notes prior to populating the latch with data from a write request, sections of a page before and after the write data are populated with random numbers or 0s or 1s and then the portion of the write data is placed in a center portion of the latch. Then the entire latch is written to the memory page.
Applicant further argues on page 6 of their remarks ‘Third, Lasser's command is a standard write command, not an initialization command as claimed. Claim 1 requires that the memory controller acts "in response to a command, to initialize at least a proper subset of addressable memory to be one of all zeros or at least one random number." This requires the command itself to trigger the initialization of the memory to zeros or a random number. In contrast, the command in Lasser (e.g., write command 120) is a command to write user information (e.g., information 122) to the memory. The fact that Lasser's system autonomously adds dummy data to the head or tail of a page during a write operation does not mean the system received a command to initialize the memory to dummy data. Therefore, Lasser fails to teach the claimed relationship between the command and the initialization operation.’
Examiner respectfully disagrees. Applicant is arguing a limitation not claimed. The claim recites “a memory controller, in response to a command, to initialize at least a proper subset of addressable memory”. The claim does not recite “an initialization command”. It recites a command, which may be any command that results in initializing a proper subset of addressable memory. As detailed above Lasser teaches a write command that triggers initializing a proper subset of addressable memory.
Applicant further argues on page 6 of their remarks ‘Fourth, with respect to paragraph [0019], Applicant would like to understand the Office's position with respect to the background. Text in the detailed description can be prior art as there is nothing special about the detailed description that makes everything in it not qualify as prior art just because it is not in the background. This is clear from legal precedent and the Office has myriad examples of this in patent applications and issued patents (see, e.g., any application or patent that says "Prior Art" in a figure that is not in the background). In this instance, paragraph [0019] describes "some memory controllers" which is clearly not referring to what Lasser invented.”
Examiner respectfully disagrees that paragraph [0019] is not relevant to Lasser’s inventive concepts. Applicant appears to argue that Lasser [0019] that discloses ‘some memory controllers insert randomized “dummy” data’ is applicable only to other controllers and not to the inventive concepts of Lasser. Examiner notes that claim 2 of Lesser clarifies “wherein the set of bits includes a random or a pseudorandom bit sequence”. Thus Lasser is directed to inserting random data and Lasser is indeed one of “some memory controllers”. Additionally, Lasser [0019] discloses inserting the random data into the latch and programmed to the memory, which is at the heart of the inventive concepts of Lasser. Paragraph [0019] is in the DETAILED DESCRIPTION section of Lasser, and is not limiting its description to previous memory controllers. In other words, paragraph [0019] indicates Lasser is not the only art that discloses inserting randomized dummy data.
Applicant’s remarks with respect to independent claims 8 and 15 all rely upon perceived errors in claim 1 and thus have been addressed by the claim rejection and remarks relating to claim 1 above.
Applicant’s remarks with respect to dependent claims 2-7, 9-14, and 16-29 all reply upon perceived errors in their respective base claims and thus have been addressed by the claim rejection and remarks of their respective base claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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