DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: There is no mention of at least the second multiplier circuit; the second plurality of multiplication operations; the third multiplier circuit, and the third plurality of multiplication operations in the descriptive portion of the specification.
Claim Objections
Claims 1-6 and 8-21 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 1 line 7, “values having the first precision” should read “the values having the first precision” instead because values having a first precision is already introduced in line 3. Claims 11 and 17 recite a similar limitation in line 8 and line 10 respectively and are objected to for the same reason. Claims 2-6 and 8-10 inherit the same deficiency as claim 1 by reason of dependence. Claims 12-16 inherit the same deficiency as claim 11 by reason of dependence. Claims 18-21 inherit the same deficiency as claim 17 by reason of dependence.
B. In claim 2 lines 1-2, the commas after one-half and one-quarter has been changed to periods. Examiner suggest replacing the periods with commas.
C. In claim 10 lines 2 and 4, “addition/subtraction circuitry” should read “addition or subtraction circuitry” instead for consistency of claim terminologies.
Claim Interpretation
“Soft logic” is interpreted as portion that are programmable and “Hard logic” are interpreted as portions that are not programmable as disclosed in paragraph [0059].
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-6 and 8-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under Step 1, Claims 1-6 and 8-10 recite a circuitry and, therefore, is a machine. Claims 11-16 recite a device and, therefore, is a machine. Claims 17-21 recites a system and, therefore, is a machine.
Under Step 2A prong 1, claim 1 recites
Multiplier circuitry comprising:
a first buffer communicatively coupled to a first multiplier circuit, the first buffer being configurable to store a first portion of values having a first precision;
a second buffer communicatively coupled to the first multiplier circuit, the second buffer being configurable to store a second portion of the values having the first precision;
the first multiplier circuit configurable to generate a plurality of subproducts by performing a first plurality of multiplication operations involving values having the first precision using a recursive multiplication process in which a second multiplier circuit of the first multiplier circuit performs a second plurality of multiplication operations involving values having a second precision that are derived from the values having the first precision; and
addition or subtraction circuitry configurable to add at least a portion of the plurality of subproducts.
The above underlined limitations of generating subproducts by performing multiplication operations and adding the subproducts amounts to processing mathematical calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. The steps of “generate”, “perform” and “add” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “a first multiplier circuit”, “a second multiplier circuit of the first multiplier circuit”, and “addition or subtraction circuitry”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “a first multiplier circuit”, “a second multiplier circuit of the first multiplier circuit”, and “addition or subtraction circuitry” language, the claim encompasses multiplying two values using Equation (3) disclosed in paragraph [0071] using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: a first buffer communicatively coupled to a first multiplier circuit, the first buffer being configurable to store a first portion of values having a first precision; a second buffer communicatively coupled to the first multiplier circuit, the second buffer being configurable to store a second portion of the values having the first precision; the first multiplier circuit configurable to, a second multiplier circuit, and addition or subtraction circuitry configurable to. However, the additional elements of “a first buffer”, “a second buffer”, “a first multiplier circuit”, “a second multiplier circuit” and “addition or subtraction circuitry” are recited at a high-level of generality (i.e., as generic buffers for storing data; a generic multiplier and as a generic sub-multiplier of the multiplier for performing multiplication operations; and as a generic adder/subtractor for performing addition) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 1 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first buffer”, “a second buffer”, “a first multiplier circuit”, “a second multiplier circuit” and “addition or subtraction circuitry” are recited at a high-level of generality (i.e., as generic buffers for storing data; a generic multiplier and as a generic sub-multiplier of the multiplier for performing multiplication operations; and as a generic adder/subtractor for performing addition) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 2-6 and 8-10 recite the same abstract idea as claim 1 by reason of dependence. Claims 2-4 and 8 recite further details of the abstract idea. In particular, claim 2 recites “wherein the second precision is one-half, one-quarter, one-eighth, or one-sixteenth of the first precision”; claim 3 recites “wherein the values having the first precision are polynomials”; claim 4 recites “implement a Karatsuba-Ofman algorithm for performing multiplication”; and claim 8 recites “wherein the first precision corresponds to 32 bits, 64 bits, or 128 bits”. Claim 5 recites further abstract idea of “perform a third plurality of multiplication operations involving having have a third precision that are derived from the values having the second precision”. Claim 6 recites recite further abstract idea of “operate in accordance with a modulo schedule”. Claim 9 recites further abstract idea of “generate a first subproduct of the plurality of subproducts by multiplying a first portion of a first value of the values having the first precision and a first portion of a second value of the values having the first precision; and a second subproduct of the plurality of subproducts by multiplying a second portion of the first value of the values having the first precision and a second portion of the second value of the values having the first precision”. Claim 10 recites further abstract idea of “generate a partial product by combining the first subproduct and the third value, generate the partial product; and generate a second partial product by combining the fourth value and the fifth value” which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular, claims 2-4, 6 and 8-9 do not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 5 recites the following additional elements: a third multiplier circuit. Claim 10 recites the following additional elements: receive the first subproduct and a third value, a first adder/subtractor communicatively coupled to the first multiplier circuit and configurable to: receive the first subproduct and the third value; and a second adder/subtractor communicatively coupled to the first multiplier circuit and the first adder/subtractor, wherein the second adder/subtractor is configurable to: receive a fourth value from the first multiplier circuit and a fifth value. However, the additional elements of “a third multiplier circuit” in claim 5; and “a first adder/subtractor”, and “a second adder/subtractor” in claim 10 are recited at a high-level of generality (i.e., as a generic multiplier capable of performing multiplication operations; and as generic adders/subtractors capable of performing addition/subtraction operations) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional elements of “receive the first subproduct and a third value”, “receive the first subproduct and the third value”, and “receive a fourth value from the first multiplier circuit and a fifth value” are merely adding insignificant extra-solution activities, i.e. mere data gathering to obtain the inputs for the addition/subtraction operations. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under step 2B, claims 5 and 10 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a third multiplier circuit” in claim 5; and “a first adder/subtractor”, and “a second adder/subtractor” in claim 10 are recited at a high-level of generality (i.e., as a generic multiplier capable of performing multiplication operations; and as generic adders/subtractors capable of performing addition/subtraction operations) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional elements of “receive the first subproduct and a third value”, “receive the first subproduct and the third value”, and “receive a fourth value from the first multiplier circuit and a fifth value” are merely adding insignificant extra-solution activities, i.e. mere data gathering to obtain the inputs for the addition/subtraction operations. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims do not amount to significantly more than the abstract idea.
Under Step 2A prong 1, claim 11 recites
An integrated circuit device comprising multiplier circuitry, the multiplier circuitry comprising:
a first buffer communicatively coupled to a first multiplier circuit, the first buffer being configurable to store a first portion of values having a first precision;
a second buffer communicatively coupled to the first multiplier circuit, the second buffer being configurable to store a second portion of the values having the first precision;
the first multiplier circuit configurable to generate a plurality of subproducts by performing a first plurality of multiplication operations involving values having the first precision using a recursive multiplication process in which a second multiplier circuit of the first multiplier circuit performs a second plurality of multiplication operations involving values having a second precision that are derived from the values having the first precision; and
adder circuitry configurable to add at least a portion of the plurality of subproducts.
The above underlined limitations of generating subproducts by performing multiplication operations and adding the subproducts amounts to processing mathematical calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. The steps of “generate”, “perform” and “add” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “a first multiplier circuit”, “a second multiplier circuit of the first multiplier circuit”, and “adder circuitry”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “a first multiplier circuit”, “a second multiplier circuit of the first multiplier circuit”, and “adder circuitry” language, the claim encompasses multiplying two values using Equation (3) disclosed in paragraph [0071] using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: multiplier circuitry, the multiplier circuitry comprising: a first buffer communicatively coupled to a first multiplier circuit, the first buffer being configurable to store a first portion of values having a first precision; a second buffer communicatively coupled to the first multiplier circuit, the second buffer being configurable to store a second portion of the values having the first precision; the first multiplier circuit configurable to, a second multiplier circuit, and adder circuitry configurable to. However, the additional elements of “multiplier circuitry “, “a first buffer”, “a second buffer”, “a first multiplier circuit”, “a second multiplier circuit” and “adder circuitry” are recited at a high-level of generality (i.e., as a generic multiplier circuitry that comprises generic buffers for storing data; a generic multiplier and a generic sub-multiplier of the multiplier for performing multiplication operations; and as a generic adder for performing addition) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 11 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “multiplier circuitry “, “a first buffer”, “a second buffer”, “a first multiplier circuit”, “a second multiplier circuit” and “adder circuitry” are recited at a high-level of generality (i.e., as a generic multiplier circuitry that comprises generic buffers for storing data; a generic multiplier and a generic sub-multiplier of the multiplier for performing multiplication operations; and a generic adder for performing addition) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 12-16 recite the same abstract idea as claim 11 by reason of dependence. Claims 13-15 recite further details of the abstract idea. In particular, claim 13 recites “wherein each of the plurality of subproducts is associated with a corresponding offset of a plurality of offsets, wherein each offset of the plurality of offsets corresponds to a relative significance of a subproduct of the plurality of subproducts”; claim 14 recites “add the plurality of subproducts while accounting for the plurality of offsets”; and claim 15 recites “perform the plurality of multiplication operations by performing one or more stages of polynomial expansion in accordance with a predetermined control schedule or a counter based control schedule” which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular, claims 13-15 do not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 12 recites the following additional elements: a register configurable to store the values having the first precision and the plurality of subproducts. Claim 16 recites the following additional elements: a programmable logic device. However, the additional elements of “a register” in claim 12; and “programmable logic device” in claim 16 are recited at a high-level of generality (i.e., as a generic computer component for storing data; and as a generic programmable logic device) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional element of “store the values having the first precision and the plurality of subproducts” is merely adding insignificant extra-solution activity. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under step 2B, claims 12 and 16 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a register” in claim 12; and “programmable logic device” in claim 16 are recited at a high-level of generality (i.e., as a generic computer component for storing data; and as a generic programmable logic device) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional element of “store the values having the first precision and the plurality of subproducts” is merely adding insignificant extra-solution activity. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims do not amount to significantly more than the abstract idea.
Under Step 2A prong 1, claim 17 recites
A system comprising:
a first integrated circuit device comprising multiplier circuitry, the multiplier circuitry comprising;
a first buffer communicatively coupled to a first multiplier circuit, the first buffer being configurable to store a first portion of values having a first precision;
a second buffer communicatively coupled to the first multiplier circuit, the second buffer being configurable to store a second portion of the values having the first precision;
the first multiplier circuit configurable to generate a plurality of subproducts by performing a first plurality of multiplication operations involving values having the first precision using a recursive multiplication process in which a second multiplier circuit of the first multiplier circuit performs a second plurality of multiplication operations involving values having a second precision that are derived from the values having the first precision; and
addition or subtraction circuitry configurable to add at least a portion of the plurality of subproducts; and
a second integrated circuit device communicatively coupled to the first integrated circuit device.
The above underlined limitations of generating subproducts by performing multiplication operations and adding the subproducts amounts to processing mathematical calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. The steps of “generate”, “perform” and “add” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “a first multiplier circuit”, “a second multiplier circuit of the first multiplier circuit”, and “addition or subtraction circuitry”, nothing in the claim element precludes the steps from practically being performed in the human mind. For example, but for the “a first multiplier circuit”, “a second multiplier circuit of the first multiplier circuit”, and “addition or subtraction circuitry” language, the claim encompasses multiplying two values using Equation (3) disclosed in paragraph [0071] using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: a first integrated circuit device comprising multiplier circuitry, the multiplier circuitry comprising; a first buffer communicatively coupled to a first multiplier circuit, the first buffer being configurable to store a first portion of values having a first precision; a second buffer communicatively coupled to the first multiplier circuit, the second buffer being configurable to store a second portion of the values having the first precision; the first multiplier circuit configurable to, a second multiplier circuit, addition or subtraction circuitry configurable to, and a second integrated circuit device communicatively coupled to the first integrated circuit device. However, the additional elements of “first integrated circuit device “, “multiplier circuitry “, “a first buffer”, “a second buffer”, “a first multiplier circuit”, “a second multiplier circuit”, “addition or subtraction circuitry”, and “ a second integrated circuit device” are recited at a high-level of generality (i.e., as a generic multiplier circuitry that comprises generic buffers for storing data; a generic multiplier and a generic sub-multiplier of the multiplier for performing multiplication operations; and a generic adder/subtractor circuit for performing addition; and as generic IC devices connected to each other) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. At most, the additional element of “a second integrated circuit device communicatively coupled to the first integrated circuit device” is merely generally linking the use of a judicial exception to a particular technological environment or field of use (by limiting the multiplication operations to a system that includes a first and second IC devices). The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 17 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “first integrated circuit device “, “multiplier circuitry “, “a first buffer”, “a second buffer”, “a first multiplier circuit”, “a second multiplier circuit”, “addition or subtraction circuitry”, and “ a second integrated circuit device” are recited at a high-level of generality (i.e., as a generic multiplier circuitry that comprises generic buffers for storing data; a generic multiplier and a generic sub-multiplier of the multiplier for performing multiplication operations; and a generic adder/subtractor circuit for performing addition; and as generic IC devices connected to each other) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. At most, the additional element of “a second integrated circuit device communicatively coupled to the first integrated circuit device” is merely generally linking the use of a judicial exception to a particular technological environment or field of use (by limiting the multiplication operations to a system that includes a first and second IC devices). The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 18-21 recite the same abstract idea as claim 17 by reason of dependence. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 18 recites the following additional elements: wherein the second integrated circuit device comprises a processor. Claim 19 recites the following additional elements: the first integrated circuit device comprises a programmable logic device. Claim 20 recites the following additional elements: a substrate, wherein the first integrated circuit device and the second integrated circuit device are mounted on the substrate. Claim 21 recites the following additional elements: wherein the multiplier circuitry is implemented partially in soft logic circuitry of the programmable logic device and partially in hard logic circuitry of the programmable logic device. However, the additional elements of “wherein the second integrated circuit device comprises a processor” in claim 18; “the first integrated circuit device comprises a programmable logic device” in claim 19; “a substrate, wherein the first integrated circuit device and the second integrated circuit device are mounted on the substrate” in claim 20; and “wherein the multiplier circuitry is implemented partially in soft logic circuitry of the programmable logic device and partially in hard logic circuitry of the programmable logic device” in claim 21 are recited at a high-level of generality (i.e., as a generic processor; as a generic programmable logic device; as a generic substrate; and as a generic multiplier circuitry implementation without reciting which specific structural component(s) is/are implemented in the soft logic and which specific structural component(s) is/are implemented in the hard logic of the PLD) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. At most, the additional elements of “wherein the second integrated circuit device comprises a processor” in claim 18; “the first integrated circuit device comprises a programmable logic device” in claim 19; “a substrate, wherein the first integrated circuit device and the second integrated circuit device are mounted on the substrate” in claim 20; and “wherein the multiplier circuitry is implemented partially in soft logic circuitry of the programmable logic device and partially in hard logic circuitry of the programmable logic device” in claim 21 are merely generally linking the use of a judicial exception to a particular technological environment or field of use (by limiting the multiplication operations to a system where the second IC is a processor; the first IC is a programmable logic device; the first and second IC devices are mounted on a substrate; and where in the multiplier circuitry is implemented in both soft and hard logic of the PLD). The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under step 2B, claims 18-21 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “wherein the second integrated circuit device comprises a processor” in claim 18; “the first integrated circuit device comprises a programmable logic device” in claim 19; “a substrate, wherein the first integrated circuit device and the second integrated circuit device are mounted on the substrate” in claim 20; and “wherein the multiplier circuitry is implemented partially in soft logic circuitry of the programmable logic device and partially in hard logic circuitry of the programmable logic device” in claim 21 are recited at a high-level of generality (i.e., as a generic processor; as a generic programmable logic device; as a generic substrate; and as a generic multiplier circuitry implementation without reciting which specific structural component(s) is/are implemented in the soft logic and which specific structural component(s) is/are implemented in the hard logic of the PLD) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. At most, the additional elements of “wherein the second integrated circuit device comprises a processor” in claim 18; “the first integrated circuit device comprises a programmable logic device” in claim 19; “a substrate, wherein the first integrated circuit device and the second integrated circuit device are mounted on the substrate” in claim 20; and “wherein the multiplier circuitry is implemented partially in soft logic circuitry of the programmable logic device and partially in hard logic circuitry of the programmable logic device” in claim 21 are merely generally linking the use of a judicial exception to a particular technological environment or field of use (by limiting the multiplication operations to a system where the second IC is a processor; the first IC is a programmable logic device; the first and second IC devices are mounted on a substrate; and where in the multiplier circuitry is implemented in both soft and hard logic of the PLD). The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims do not amount to significantly more than the abstract idea.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 9, 11, 16-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Langhammer et al. (US 20190310828 A1), hereinafter Langhammer, in view of Gopal et al. (US 20080140753 A1), hereinafter Gopal.
Regarding claim 1, Langhammer teaches a multiplier circuitry comprising:
the first multiplier circuit configurable to generate a plurality of subproducts by performing a first plurality of multiplication operations involving values having the first precision using a recursive multiplication process in which a second multiplier circuit of the first multiplier circuit performs a second plurality of multiplication operations involving values having a second precision that are derived from the values having the first precision (Langhammer Figs. 3-5 and paragraphs [0031-0035] “Inputs A and B are each split into upper halves AH and BH and lower halves AL and BL, respectively. The two upper halves AH and BH are multiplied using multiplier circuit 103 to generate product PH, whereas the two lower halves AL and BL are multiplied using multiplier circuit 106 to generate product PL … Multiplier circuit 107 may then compute the product of the sum from adder 104 and the sum from adder 105 to generate product PM … The Karatsuba multiplication scheme can be recursively decomposed. In other words, each of multipliers 103, 106, and 107 may itself be implemented using the entire structure of multiplier 400, and the process iterated for each level of decomposition that is desired. FIG. 5 is a diagram of illustrative multiplier circuitry 500 with a flat (unrolled) decomposition of four levels”; first multiplier circuit – multiplier circuitry 400 or multipliers in the level #1 decomposition; plurality of subproducts – products PM, PH, PL; values having a first precision – inputs A and B; recursive multiplication process - Karatsuba multiplication scheme; second multiplier circuit – multipliers 103, 106 and/or 107 at a further decomposition level than first multiplier circuit; values having a second precision – segments of A and B) ; and
addition or subtraction circuitry configurable to add at least a portion of the plurality of subproducts (Langhammer Figs. 3-4 and paragraphs [0031-0032] addition or subtraction circuitry – subtraction circuit 108 and/or adder circuit 109).
Langhammer does not explicitly teach a first buffer communicatively coupled to a first multiplier circuit, the first buffer being configurable to store a first portion of values having a first precision; a second buffer communicatively coupled to the first multiplier circuit, the second buffer being configurable to store a second portion of the values having the first precision.
However, on the same field of endeavor, Gopal discloses a multiplier circuitry comprising a first buffer communicatively coupled to a first multiplier circuit, the first buffer configured to store a first portion of values having a first precision; and a second buffer communicatively coupled to the first multiplier circuit, the second buffer configured to store a second portion of the values having the first precision (Gopal Fig. 1 and paragraphs [0013-0014] “As shown in FIG. 1, the multiplier 120 operates on two operands A 100a and B 100b. FIG. 1 shows operands A 100a and B 100b as composed of sets of segments ai, and bj … For example, for a 512-bit A 100a and B 100b, x may be set to 2128 yielding uniform 128-bit sized segments … The values of A 100a and B 100b may be stored in respective FIFO (First-In-First-Out) queues that buffer the operands 100a, 100b”; first and second buffer - respective FIFO buffers; values – A and B; first portion – ai; second portion – bj; first precision – precision of A and B).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Langhammer using Gopal and configure the multiplier circuity to include a first and second buffers upstream of the three multipliers for buffering the respective input operands A and B, i.e., the segments of A and B in order to increase the efficiency of the multiplier circuitry. By storing each segment in an entry of the buffers, the multipliers can simultaneously perform multiplication operations on multiple segments which increases performance of the multiplier circuitry (Gopal paragraphs [0005, 0012, 0014]).
Therefore, the combination of Langhammer as modified in view of Gopal teaches a first buffer communicatively coupled to a first multiplier circuit, the first buffer being configurable to store a first portion of values having a first precision; a second buffer communicatively coupled to the first multiplier circuit, the second buffer being configurable to store a second portion of the values having the first precision.
Regarding claim 2, Langhammer as modified in view of Gopal teaches all the limitations of claim 1 as stated above. Further, Langhammer as modified in view of Gopal teaches wherein the second precision is one-half, one-quarter, one-eighth, or one-sixteenth of the first precision (Langhammer Fig. 5 and paragraphs [0033-0034] “Assuming inputs A and B are each 2048 bits wide, the adders at the first level (or the first decomposition stage) can be 1024-bit adders (with carry out) since adders 104 and 105 only need to sum together half portions of each input”).
Regarding claim 4, Langhammer as modified in view of Gopal teaches all the limitations of claim 1 as stated above. Further, Langhammer as modified in view of Gopal teaches wherein the first multiplier circuit, the second multiplier circuit, or both implement a Karatsuba-Ofman algorithm for performing multiplication (Langhammer Figs. 3-5 and paragraph [0031, 0033] “FIG. 4 is a block diagram of illustrative multiplier circuitry 400 implementing the Karatsuba decomposition process … The Karatsuba multiplication scheme can be recursively decomposed”).
Regarding claim 5, Langhammer as modified in view of Gopal teaches all the limitations of claim 1 as stated above. Further, Langhammer teaches wherein the second multiplier circuit comprises a third multiplier circuit configurable to perform a third plurality of multiplication operations involving values having a third precision that are derived from the values having the second precision (Langhammer Figs. 4-5 and paragraphs [0033] “The Karatsuba multiplication scheme can be recursively decomposed. In other words, each of multipliers 103, 106, and 107 may itself be implemented using the entire structure of multiplier 400, and the process iterated for each level of decomposition that is desired. FIG. 5 is a diagram of illustrative multiplier circuitry 500 with a flat (unrolled) decomposition of four levels”; third multiplier circuit - multipliers 103, 106 and/or 107 at a further decomposition level than the second multiplier circuit; values having a third precision - further decomposed segments of A and B at the decomposition level of the third multiplier circuit).
Regarding claim 9, Langhammer as modified in view of Gopal teaches all the limitations of claim 1 as stated above. Further, Langhammer as modified in view of Gopal teaches wherein the first multiplier circuit is configurable to generate:
a first subproduct of the plurality of subproducts by multiplying a first portion of a first value of the values having the first precision and a first portion of a second value of the values having the first precision (Langhammer Figs. 3-4 and paragraph [0031] “The two upper halves AH and BH are multiplied using multiplier circuit 103 to generate product PH”; first subproduct – PH; first portion of a first value – AH; first portion of a second value – BH); and
a second subproduct of the plurality of subproducts by multiplying a second portion of the first value of the values having the first precision and a second portion of the second value of the values having the first precision (Langhammer Figs. 3-4 and paragraph [0031] “the two lower halves AL and BL are multiplied using multiplier circuit 106 to generate product PL”; second subproduct – PL; second portion of the first value – AL; second portion of the second value - BL).
Regarding claim 11, Langhammer teaches an integrated circuit device comprising multiplier circuitry, the multiplier circuitry comprising (Langhammer Figs. 4-5 multiplier circuitry – multiplier circuitry 400):
the first multiplier circuit configurable to generate a plurality of subproducts by performing a first plurality of multiplication operations involving values having the first precision using a recursive multiplication process in which a second multiplier circuit of the first multiplier circuit performs a second plurality of multiplication operations involving values having a second precision that are derived from the values having the first precision (Langhammer Figs. 3-5 and paragraphs [0031-0035] “Inputs A and B are each split into upper halves AH and BH and lower halves AL and BL, respectively. The two upper halves AH and BH are multiplied using multiplier circuit 103 to generate product PH, whereas the two lower halves AL and BL are multiplied using multiplier circuit 106 to generate product PL … Multiplier circuit 107 may then compute the product of the sum from adder 104 and the sum from adder 105 to generate product PM … The Karatsuba multiplication scheme can be recursively decomposed. In other words, each of multipliers 103, 106, and 107 may itself be implemented using the entire structure of multiplier 400, and the process iterated for each level of decomposition that is desired. FIG. 5 is a diagram of illustrative multiplier circuitry 500 with a flat (unrolled) decomposition of four levels”; first multiplier circuit – multiplier circuitry 400 or multipliers in the level #1 decomposition; plurality of subproducts – products PM, PH, PL; values having a first precision – inputs A and B; recursive multiplication process - Karatsuba multiplication scheme; second multiplier circuit – multipliers 103, 106 and/or 107 at a further decomposition level than the multiplier; values having a second precision – segments of A and B);
adder circuitry configurable to add at least a portion of the plurality of subproducts (Langhammer Figs. 3-4 and paragraphs [0031-0032] addition or subtraction circuitry – subtraction circuit 108 and/or adder circuit 109).
Langhammer does not explicitly teach a first buffer communicatively coupled to a first multiplier circuit, the first buffer being configurable to store a first portion of values having a first precision; a second buffer communicatively coupled to the first multiplier circuit, the second buffer being configurable to store a second portion of the values having the first precision.
However, on the same field of endeavor, Gopal discloses a multiplier circuitry comprising a first buffer communicatively coupled to a first multiplier circuit, the first buffer configured to store a first portion of values having a first precision; and a second buffer communicatively coupled to the first multiplier circuit, the second buffer configured to store a second portion of the values having the first precision (Gopal Fig. 1 and paragraphs [0013-0014] “As shown in FIG. 1, the multiplier 120 operates on two operands A 100a and B 100b. FIG. 1 shows operands A 100a and B 100b as composed of sets of segments ai, and bj … For example, for a 512-bit A 100a and B 100b, x may be set to 2128 yie