Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 – 12 and 14 - 17 are rejected under 35 U.S.C. 103 as being unpatentable over by Ganapathy et al. (US Pat. No. 7464197), hereinafter referred to as Ganapathy in view of Kilgard (US Pat. No. 8698837) and in further view of Bibikar et al. (US Pat. No. 9620088), hereinafter referred to as Bibikar.
Referring to claim 1, Ganapathy discloses a system comprising:
a discrete graphics system-on-chip (SoC) (a system-on-chip (SoC) implementing distributed direct memory access (DMA) across multiple functional modules (Abstract, FIG. 1, col. 1, lines 40-50)) to couple to a host processor unit (host processor unit, FIG. 2), the SoC comprising:
a memory bridge (a global buffer memory connected via a system bus, enabling direct memory access by different functional blocks (col. 3, lines 5-25, FIG. 2)) comprising:
a first port (via a system bus) to receive requests sent by a compute engine (direct memory access by different functional blocks) of the discrete graphics SoC through a first path to graphics memory (dedicated DMA controllers interfacing with processing units (DSPs, cores) via a system bus (col. 3, lines 25-40, FIG. 3));
and a second port (multiple functional modules) to receive requests sent by a plurality of agents of the SoC through a second path to the memory (multiple functional modules (network interfaces, host controllers) accessing memory through independent DMA controllers (col. 4, lines 10-30, FIG. 7)).
Kilgard discloses, what Ganapathy lacks, a host processor unit (CPU 102, FIG. 2A); and
different path to the graphics memory (graphics subsystem 112 to memory bridge 105 to memory controller 104, Fig. 2A; and I/O bridge 107 to memory bridge 105 to memory controller 104, Fig. 2A; the compute engine and other system agents issue memory requests via entirely separate structural pathways through the memory bridge, each using a different origin and dedicated interface).
Ganapathy and Kilgard are analogous art because they are from the same field of endeavor of graphics processing architectures and memory interface subsystems.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ganapathy and Kilgard before him or her, to modify the SoC memory architecture of Ganapathy to include the explicit host CPU connection and the dual memory access paths through structurally distinct agents of Kilgard because Kilgard teaches an implementation wherein both a compute engine (graphics subsystem 112) and other system agents (e.g., I/O bridge 107) issue memory access requests to a shared memory bridge through entirely separate interfaces, enabling improved arbitration and bandwidth management.
The suggestion/motivation for doing so would have been to enable more efficient memory access arbitration between heterogeneous SoC components, and to isolate bandwidth-heavy compute engines from general I/O traffic, thereby improving overall system throughput (Kilgard; col. 4, lines 53–63).
Therefore, it would have been obvious to combine Kilgard with Ganapathy to obtain the invention as specified in the instant claim.
Bibikar discloses, what Ganapathy and Kilgard lack, wherein during a low power state of the SoC, the first path to the graphics memory is not active (processor 120 and other SoC components powered down, during low-power standby mode, non-critical components including processor cores and I/O fabric are powered down, disabling compute-related memory access paths, Fig. 1; Fig. 3A–3B) and the second path to the graphics memory is active (while display controller 140 remains active accessing display buffer 134 via transaction router 128, Fig. 1; Fig. 3A–3B).
The modified system of Ganapathy and Bibikar are analogous art because they are from the same field of endeavor of system-on-chip (SoC) memory access architectures and power management for shared memory systems.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ganapathy and Bibikar before him or her, to modify the memory access architecture of Ganapathy to include the selective activation and deactivation of memory access paths during a low power state as taught by Bibikar because Bibikar teaches that, during a low-power standby mode, non-critical components of the SoC (including processor cores and other functional units that generate compute-related memory requests) are powered down, while a display controller remains active and continues to access memory (e.g., display buffer) via a transaction router, thereby inherently disabling one class of memory request paths while maintaining another path active to memory for continued operation such as display refresh .
The suggestion/motivation for doing so would have been to reduce power consumption of the SoC while maintaining essential functionality, such as display refresh, by disabling high-power compute-related paths and maintaining only the necessary memory access path, which is explicitly taught by Bibikar (powering down processor cores and non-critical components while keeping display controller, display buffer, and transaction router active, col. corresponding to Fig. 3A–3B; see also description of powering down unused components while maintaining display refresh functionality) .
Therefore, it would have been obvious to combine Bibikar with Ganapathy and Kilgard to obtain the invention as specified in the instant claim.
As to claim 3, Ganapathy discloses the system of claim 2, wherein during the low power state of the SoC, the second path to the graphics memory is to transport data associated with debugging operations (a microcontroller that orchestrates data transfers even in low-power states (col. 6, lines 15-30). Debugging and control information can be routed through dedicated DMA channels).
As to claim 4, Ganapathy discloses the system of claim 1, wherein the first path to the graphics memory has a higher maximum bandwidth than the second path to the graphics memory (differentiates between high-speed DMA channels for data-intensive operations and low-bandwidth channels for control tasks (col. 4, lines 30-50)).
As to claim 5, Ganapathy discloses the system of claim 1, further comprising a memory port, the memory port to queue requests from the plurality of agents of the SoC (a bus arbitration system that queues requests from multiple DMA controllers before accessing memory (col. 7, lines 5-20)).
As to claim 6, Ganapathy discloses the system of claim 5, the memory port further to translate requests from the plurality of agents of the SoC into a protocol used by the memory bridge (protocol translation for memory access (col. 7, lines 30-45), where different bus interfaces interact with the global buffer memory).
As to claim 7, Ganapathy discloses the system of claim 5, further comprising an interconnect fabric in the first path to the memory, the interconnect fabric comprising a routing table specifying forwarding of traffic from the SoC agents to the memory port (bus arbitration and routing logic, including a routing table for managing memory access priorities (col. 8, lines 10-35)).
As to claim 8, Ganapathy discloses the system of claim 1, the memory bridge comprising arbitration logic to arbitrate between requests received through the first path to the memory and requests received through the second path to the memory (arbitration logic managing multiple memory paths and DMA controllers (col. 9, lines 5-25)).
As to claim 9, Ganapathy discloses the system of claim 1, the memory bridge comprising a third port to receive requests sent by an isochronous agent through a third path to the memory (priority-based DMA access for real-time data streams, which is analogous to isochronous agents (col. 10, lines 5-20)).
As to claim 10, Ganapathy discloses the system of claim 9, the memory bridge further comprising arbitration logic to give priority to requests sent by the isochronous agent over requests sent by the agents of the SoC (DMA arbitration that prioritizes real-time data transfers over standard memory requests (col. 11, lines 5-30)).
As to claim 11, Ganapathy discloses the system of claim 1, further comprising the compute engine (processing cores that request memory access via DMA controllers (FIG. 2, col. 3, lines 10-20)).
As to claim 12, Ganapathy discloses the system of claim 1, further comprising the memory (a global buffer memory managing system data (col. 3, lines 5-15)).
As to claim 14, Ganapathy discloses the system of claim 12, further comprising a battery communicatively coupled to the host processor unit, a display communicatively coupled to the host processor unit, or a network interface communicatively coupled to the host processor unit (power management systems, display interfaces, and network interfaces connected to the SoC (col. 12, lines 5-30)).
Claims 15 - 17 recite the corresponding limitation of claims 1 and 3 - 4. Therefore, they are rejected accordingly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Subramanian et al. (US Pub. No. 20230298124) discloses a circuit for processing images and, more particularly, an image signal processor that uses a dynamically shared buffer.
Response to Arguments
Applicant's arguments filed 2/9/2026 have been fully considered but they are not persuasive.
Applicant’s amendment incorporating the low-power state limitation into independent claim 1 has been fully considered. While Ganapathy was previously relied upon in the Final Action as teaching power-aware memory management in which different DMA controllers operate independently and may selectively remain active during reduced power conditions (col. 5, lines 5–25), the Examiner recognizes that the disclosure in Ganapathy is more implicit with respect to the specific requirement that one memory access path is inactive while another remains active during a low power state. Accordingly, in the interest of clarity and to provide a more explicit and robust evidentiary basis, the Examiner now relies on Bibikar (US 9,620,088 B2), which clearly discloses that, during a low-power standby mode, non-critical components of the SoC (including processor cores and associated memory access paths) are powered down, while a display controller remains active and continues to access memory to refresh the display.
The Examiner has carefully considered whether the present amendment would place the application in condition for allowance. However, such a determination cannot be made at this time because the added limitation does not impart a structural distinction over the prior art, but rather recites an operational state or intended use of known components. Under the broadest reasonable interpretation, selectively disabling one class of memory access paths while maintaining another during a low-power state constitutes a well-understood and routine power management technique in SoC and graphics architectures, as evidenced by Bibikar. Thus, the amendment does not overcome the combined teachings of the prior art.
This updated reliance does not represent a change in position regarding the patentability of the claimed subject matter, but rather strengthens the rejection by providing a reference that more directly and expressly teaches the claimed selective activation of distinct memory access paths during a low power state. As such, the combination of Ganapathy, Kilgard and Bibikar more clearly renders the amended limitation obvious, and the claims remain unpatentable.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.B/ Assistant Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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