Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Amendment filed 02/12/2026. In the instant amendment, claims 1, 9, 16 and 20 are amended; claims 1, 9 and 16 are independent claims. Claims 1-20 are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/12/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 9 and 16 in regard to the limitation “and in response to the indication, performing a mitigation action by throttling instruction execution for instructions associated with the thread identifier within a processor pipelined,” have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments filed 02/12/2026 have been fully considered but they are not persuasive.
Applicant argues that on (pages 7-9): that the cited prior art fails to explicitly disclose or suggest “receiving, an indication that a number of accesses of a memory region exceeds a threshold number of accesses for a time period, the indication including a thread identifier of a thread that may be performing an attack on the memory region; and in response to the indication, performing a mitigation action by throttling instruction execution for instructions associated with the thread identifier within a processor pipeline to decrease a frequency at which memory access instructions of the thread are issued to a memory subsystem until the number of accesses at the memory region is below the threshold number of accesses for the time period or a timeout has occurred in regard to claim 1.
The Examiner respectfully disagrees with applicant. Yaglikci discloses tracking row activation/access rate against a RowHammer threshold over a time period, identifies an attacker thread, and applies per-thread throttling which is a quota on in-flight requests for a determined time period to reduce the attacker’s effective memory request issue rate. Blockhammer discloses tracking activation/access rate versus a RowHammer threshold and acting when the threshold is approached/exceeded, using time-bound tracking. Blockhammer’s AttackThrottler is explicitly thread-based such as attacker thread versus benign threads and applies per-thread control based on the thread’s behavior/metric (RHLI). The AttackThrottler reduces the memory bandwidth usage of an attacker thread by applying a quota to the thread’s in-flight memory requests by reducing how many memory requests the thread can have outstanding or issued into the memory system. BlockHammer’s control is inherently time-period bounded from determined time period quotas and/or windowing, matching the timeout/time period release concept. Blockhammer is an implementable hardware mechanism with tracking structures and a throttler that maps on to the second circuit configured to. Blockhammer supplies a thresholded access or activation detection in a time period, attacker thread and throttling to reduce an attacker’s memory request rate for a determined time period, (See Yaglikci Pages 345-357)
Applicant argues that on (pages 7-9): that the cited prior art fails to explicitly disclose or suggest “a processor core comprising: a first circuit configured to execute a thread issuing accesses of a memory region; and at least one second circuit configured to: receive an indication that a number of accesses of the memory region by the thread exceeds a threshold number of accesses for a time period, the indication including a thread identifier of that the thread that may be performing an attack on the memory region; and in response to the indication, perform a mitigation action by throttling instruction execution for instructions associated with the thread identifier to decrease a frequency at which memory access instructions of the thread are issued to a memory subsystem in regard to claim 9.”
The Examiner respectfully disagrees with applicant. Yaglikci discloses tracking row activation/access rate against a RowHammer threshold over a time period, identifies an attacker thread, and applies per-thread throttling which is a quota on in-flight requests for a determined time period to reduce the attacker’s effective memory request issue rate. Blockhammer discloses tracking activation/access rate versus a RowHammer threshold and acting when the threshold is approached/exceeded, using time-bound tracking. Blockhammer’s AttackThrottler is explicitly thread-based such as attacker thread versus benign threads and applies per-thread control based on the thread’s behavior/metric (RHLI). The AttackThrottler reduces the memory bandwidth usage of an attacker thread by applying a quota to the thread’s in-flight memory requests by reducing how many memory requests the thread can have outstanding or issued into the memory system. BlockHammer’s control is inherently time-period bounded from determined time period quotas and/or windowing, matching the timeout/time period release concept. Blockhammer is an implementable hardware mechanism with tracking structures and a throttler that maps on to the second circuit configured to. Blockhammer supplies a thresholded access or activation detection in a time period, attacker thread and throttling to reduce an attacker’s memory request rate for a determined time period, (See Yaglikci Pages 345-357)
Applicant argues that on (pages 7-9): that the cited prior art fails to explicitly disclose or suggest “a detection circuit configured to generate an indication when a number of accesses of a memory region exceeds a threshold number of accesses for a time period, the indication including a thread identifier of a thread that may be performing an attack on the memory region; and a control circuit coupled with the detection circuit and configured to, in response to receiving the indication, perform a mitigation action by throttling execution of instructions associated with a thread identifier within a processor to decrease a frequency at which memory access instructions of the thread are issued to a memory subsystem until the number of accesses for the time period or a timeout has elapsed in regard to claim 16.
The Examiner respectfully disagrees with applicant. Yaglikci discloses tracking row activation/access rate against a RowHammer threshold over a time period, identifies an attacker thread, and applies per-thread throttling which is a quota on in-flight requests for a determined time period to reduce the attacker’s effective memory request issue rate. Blockhammer discloses tracking activation/access rate versus a RowHammer threshold and acting when the threshold is approached/exceeded, using time-bound tracking. Blockhammer’s AttackThrottler is explicitly thread-based such as attacker thread versus benign threads and applies per-thread control based on the thread’s behavior/metric (RHLI). The AttackThrottler reduces the memory bandwidth usage of an attacker thread by applying a quota to the thread’s in-flight memory requests by reducing how many memory requests the thread can have outstanding or issued into the memory system. BlockHammer’s control is inherently time-period bounded from determined time period quotas and/or windowing, matching the timeout/time period release concept. Blockhammer is an implementable hardware mechanism with tracking structures and a throttler that maps on to the second circuit configured to. Blockhammer supplies a thresholded access or activation detection in a time period, attacker thread and throttling to reduce an attacker’s memory request rate for a determined time period, (See Yaglikci Pages 345-357)
Applicant's arguments (page 9): Additionally, as to the dependent claims 2-8, 10-15 and 17-20 the Applicant argues that the claims are dependent directly or indirectly from a respective one of claims of independent claims 1, 9 and 16 and are therefore distinguished from the cited art at least by virtue OR allowable at least based on of their additionally recited patentable subject matter.
The Examiner disagrees with the Applicant. The Examiner respectfully submits that dependent claims 2-8, 10-15 and 17-20 are rejected at least based on the rationale and resource presented to the argument for their respective based claims, and the reference applied to the dependent claims 2-8, 10-15 and 17-20. Therefore, in view of the above reasons, the Examiner maintains the rejection with the cited prior art references.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yaglikci et al (“Yaglikci,” “BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Pages 345-358, April 22, 2021) in view of Kang et al (“Kang,” US 7,886,131).
Regarding claim 1, Yaglikci discloses a method, comprising:
receiving, an indication that a number of accesses of a memory region exceeds a threshold number of accesses for a time period, (Yaglikci discloses receiving, an indication (Page 350, Left Column and Right Column Under Section 3.2 Attack Throttler describes an internal trigger to AttackThrottler and RowBlocker logic) that a number of accesses (Page 347, Right Column Under Section 3 Blockhammer describes row activations) of a memory region (Page 347, Right Column Under Section 3 Blockhammer describes a DRAM row) exceeds a threshold number of accesses for a time period (Page 348, Left Column Under Section High-Level Overview of RowBloacker and Right Column, Under Combining UBF and CBF for blacklisting describes an exceeding a threshold for activations per time window; also see Pages 345-357)
the indication including a thread identifier of a thread that may be performing an attack on the memory region; (Yaglikci discloses the indication including a thread identifier of a thread (Page 347, Under Section 3. Blockhammer describes attacker threads; Page 350 Section 3.2.1 Under Identifying Ongoing RowHammer Attacks describes a per-thread metric RHLI and differentiates a benign thread and an attacker thread) that may be performing an attack on the memory region (Page 350, Left Column, Under 3.2 Under AttackThrottler describes an attack; Page 347, Right Column Under Section 3 Blockhammer describes a DRAM row; also see Pages 345-357)
and in response to the indication, performing a mitigation action by throttling instruction execution for instructions associated with the thread identifier within a processor to decrease a frequency at which memory access instructions of the thread are issued to a memory subsystem until the number of accesses at the memory region is below the threshold number of accesses for the time period or a timeout has elapsed, (Yaglikci, Page 350, Left Column, Last Paragraph under 3.2 Attack Throttler, Page 355, Under Section 8.3, Left and Right Column & Section 9, Table 6, Page 346, describe and in response to the indication, performing a mitigation action by throttling instruction execution associated with the thread identifier within a processor to decrease a frequency at which memory access instructions of the thread are issued to a memory subsystem until the number of accesses at the memory region is below the threshold number of accesses for the time period or a timeout has elapsed; also see Pages 345-357)
Yaglikci fails to explicitly disclose and in response to the indication, performing a mitigation action by throttling instruction execution for instructions associated with the thread identifier within a processor pipelined.
However, in an analogous art, Kang discloses and in response to the indication, performing a mitigation action by throttling instruction execution for instructions associated with the thread identifier within a processor pipelined, (Kang discloses and in response to the indication, performing a mitigation action by throttling instruction execution (Col. 1, Lines 35-46) for instructions associated with the thread identifier (Col. 4, Lines 18-27) within a processor pipelined (Col. 7, Lines 14-23))
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kang with Yaglikci to include and in response to the indication, performing a mitigation action by throttling instruction execution for instructions associated with the thread identifier within a processor pipelined. One would have been motivated to provide a multithreaded processor with thread based throttling capability (Kang, Col. 1, Lines 15-18).
Regarding claim 9, Yaglikci discloses a processing device comprising:
a processor core comprising: (Yaglikci discloses on Page 352, Right Column, Under Section 6.1 Main Components of Blockhammer describes a 28 core Intel Xeon Processor; also see Pages 345-357)
a first circuit configured to execute a thread issuing accesses of a memory region; (Yaglikci discloses on Page 347, Left column Second Paragraph circuitry; Page 346, Right Column describes threads; Page 347, Right Column Under Section 3 Blockhammer describes row activations; Page 347, Right Column Under Section 3 Blockhammer describes a DRAM row; also see Pages 345-357)
and at least one second circuit configured to: (Yaglikci discloses on Page 347, Left column Second Paragraph circuitry; also see Pages 345-357)
receive an indication that a number of accesses of the memory region by the thread exceeds a threshold number of accesses for a first time period, (Yaglikci discloses receiving, an indication (Page 350, Left Column and Right Column Under Section 3.2 Attack Throttler describes an internal trigger to AttackThrottler and RowBlocker logic) that a number of accesses (Page 347, Right Column Under Section 3 Blockhammer describes row activations) of a memory region (Page 347, Right Column Under Section 3 Blockhammer describes a DRAM row) exceeds a threshold number of accesses for a time period (Page 348, Left Column Under Section High-Level Overview of RowBloacker and Right Column, Under Combining UBF and CBF for blacklisting describes an exceeding a threshold for activations per time window; also see Pages 345-357)
the indication including a thread identifier of that the thread that may be performing an attack on the memory region; (Yaglikci, Page 356, Left Column, First Paragraph; Page 346, Left Column Under Key Mechanism, Page 347, Right Column, Under Section 3. BlockHammer describes receiving an indication that the number of accesses of a memory region exceeds a threshold number of accesses for a time interval [period], the indication identifying an attacker thread that is performing an attack on the memory region; also see Pages 345-357)
and in response to the indication, perform a mitigation action by throttling instruction execution for instructions associated with the thread identifier to decrease a frequency at which memory access instructions of the thread are issued to a memory subsystem until the number of accesses at the memory region is below the threshold number of accesses for the time period or timeout has elapsed, (Yaglikci, Page 350, Left Column, Last Paragraph under 3.2 Attack Throttler, Page 355, Under Section 8.3, Left and Right Column & Section 9, Table 6, Page 346, describe and in response to the indication, perform a mitigation action by throttling instruction execution for instructions with the thread identifier to decrease a frequency at which memory access instructions of the thread are issued to a memory subsystem until the number of accesses at the memory region is below the threshold number of accesses for the time period or timeout has elapsed; also see Pages 345-357)
Yaglikci fails to explicitly disclose and in response to the indication, perform a mitigation action by throttling instruction execution for instructions associated with the thread identifier.
However, in an analogous art, Kang discloses and in response to the indication, perform a mitigation action by throttling instruction execution for instructions associated with the thread identifier, (Kang discloses and in response to the indication, performing a mitigation action by throttling instruction execution (Col. 1, Lines 35-46) for instructions associated with the thread identifier (Col. 4, Lines 18-27))
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kang with Yaglikci to include and in response to the indication, perform a mitigation action by throttling instruction execution for instructions associated with the thread identifier. One would have been motivated to provide a multithreaded processor with thread based throttling capability (Kang, Col. 1, Lines 15-18).
Regarding claim 16, Yaglikci discloses computing system, comprising:
a detection circuit configured to generate an indication when a number of accesses of a memory region exceeds a threshold number of accesses for a time period, (Yaglikci discloses a detection circuit (Page 347, Left column Second Paragraph circuitry) configured to generate an indication (Page 350, Left Column and Right Column Under Section 3.2 Attack Throttler describes an internal trigger to AttackThrottler and RowBlocker logic) that a number of accesses (Page 347, Right Column Under Section 3 Blockhammer describes row activations) of a memory region (Page 347, Right Column Under Section 3 Blockhammer describes a DRAM row) exceeds a threshold number of accesses for a time period (Page 348, Left Column Under Section High-Level Overview of RowBloacker and Right Column, Under Combining UBF and CBF for blacklisting describes an exceeding a threshold for activations per time window; also see Pages 345-357)
the indication including a thread identifier of a thread that may be performing an attack on the memory region; (Yaglikci, Page 356, Left Column, First Paragraph; Page 346, Left Column Under Key Mechanism, Page 347, Right Column, Under Section 3. BlockHammer describes receiving an indication that the number of accesses of a memory region exceeds a threshold number of accesses for a time interval [period], the indication identifying an attacker thread that is performing an attack on the memory region; also see Pages 345-357)
and a control circuit coupled with the detection circuit and configured to, in response to receiving the indication, perform a mitigation action by throttling execution of instructions associated with the thread identifier within a processor to decrease a frequency at which memory access instructions of the thread are issued to a memory subsystem until the number of accesses at the memory region is below the threshold number of accesses for the time period or a timeout has elapsed, (Yaglikci, Page 350, Left Column, Last Paragraph under 3.2 Attack Throttler, Page 355, Under Section 8.3, Left and Right Column & Section 9, Table 6, Page 346, describe and a control circuit coupled with the detection circuit and configured to, in response to receiving the indication, perform a mitigation action by throttling execution of instructions associated with the thread identifier within a processor to decrease a frequency at which memory access instructions of the thread are issued to a memory subsystem until the number of accesses at the memory region is below the threshold number of accesses for the time period or a timeout has elapsed; also see Pages 345-357)
Yaglikci fails to explicitly disclose and a control circuit coupled with the detection circuit and configured to, in response to receiving the indication, perform a mitigation action by throttling execution of instructions associated with the thread identifier within a processor pipeline.
However, in an analogous art, Kang discloses and a control circuit coupled with the detection circuit and configured to, in response to receiving the indication, perform a mitigation action by throttling execution of instructions associated with the thread identifier within a processor pipeline, (Kang discloses and a control circuit (Col. 3, Line 28; Col. 4, Lines 1-5) coupled to the detection circuit (Col. 4, Lines 1-5; Col. 8, Line 35) and configured to, in response to the indication, performing a mitigation action by throttling instruction execution (Col. 1, Lines 35-46) for instructions associated with the thread identifier (Col. 4, Lines 18-27) within a processor pipelined (Col. 7, Lines 14-23))
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kang with Yaglikci to include and a control circuit coupled with the detection circuit and configured to, in response to receiving the indication, perform a mitigation action by throttling execution of instructions associated with the thread identifier within a processor pipeline. One would have been motivated to provide a multithreaded processor with thread based throttling capability (Kang, Col. 1, Lines 15-18).
Claims 2 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yaglikci et al (“Yaglikci,” “BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Pages 345-358, April 22, 2021) in view of Kang et al (“Kang,” US 7,886,131) and further in view of Saroiu et al (“Saroiu,” US 20220050793).
Regarding claim 2, Yaglikci and Kang disclose the method of claim 1.
Yaglikci and Kang fail to explicitly disclose wherein: the memory region is a memory row in a dynamic random access memory module; and the method further comprises: in response to detecting that the number of accesses is greater than the threshold number of accesses for the time period, communicating the thread identifier of the thread to a processor core executing the thread.
However, in an analogous art, Saroiu discloses wherein: the memory region is a memory row in a dynamic random access memory module; (Saroiu, [0030], describes a memory row; [0033] describes a DRAM module)
and the method further comprises:
in response to detecting that the number of accesses is greater than the threshold number of accesses for the time period, (Saroiu, [0030], If a number of accesses is greater than a threshold, or a frequency of accesses is greater than another threshold, the row may be identified as a potential aggressor row and the potential aggressor row may be moved to a random memory location. The identification of a potential aggressor row may be performed for each row, or performed at a predetermined time (e.g., rows accessed at a specific time may be identified as a potential aggressor row))
communicating the thread identifier of the thread to a processor core executing the thread, (Saroiu, [0065], [0054], [0064] describes communicating a thread identifier of the thread to a processor core executing a thread)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saroiu with the method and system of Yaglikci and Kang include wherein: the memory region is a memory row in a dynamic random access memory module; and the method further comprises: in response to detecting that the number of accesses is greater than the threshold number of accesses for the time period, communicating the thread identifier of the thread to a processor core executing the thread. One would have been motivated to prevent induced charge leakage in random-access memory (RAM) which may cause data corruption (Saroiu, [0004]).
Regarding claim 19, Yaglikci and Kang disclose the computing system of claim 16.
Yaglikci and Kang fail to explicitly disclose wherein the detection circuit is further configured to: count the number of accesses of the memory region during the time period; associate the number of accesses with the thread identifier of the thread; and
communicate the thread identifier to a processing unit when the number of accesses exceeds the threshold number of accesses for the time period.
However, in an analogous art, Saroiu discloses wherein the detection circuit is further configured to: (Saroiu, [0004], [0051], [0074] describes circuitry used for detection)
count the number of accesses of the memory region during the time period; (Saroiu, [0037], [0055], describes counting the number of row accesses of the memory region during a period of time)
associate the number of accesses with the thread identifier of the thread; (Saroiu, [0037], [0065], [0067], [0064], describes associating the number of row accesses with a thread identifier of the thread)
and communicate the thread identifier to the processing unit when the number of accesses exceeds the threshold number of accesses for the time period, (Saroiu, [0030], [0055], [0065], [0037] describes communicating the thread identifier to the processor when the number of row accesses exceeds the threshold number of accesses for the time period)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saroiu with the method and system of Yaglikci and Kang to include wherein the detection circuit is further configured to: count the number of accesses of the memory region during the time period; associate the number of accesses with the thread identifier of the thread; and communicate the thread identifier to the processing unit when the number of accesses exceeds the threshold number of accesses for the time period. One would have been motivated to prevent induced charge leakage in random-access memory (RAM) which may cause data corruption (Saroiu, [0004]).
Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yaglikci et al (“Yaglikci,” “BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Pages 345-358, April 22, 2021) in view of Kang et al (“Kang,” US 7,886,131) and further in view of Ferholl et al (“CN101452378,” See Translation of CN101452378B, Pages 1-17, 2011).
Regarding claim 3, Yaglikci and Kang disclose the method of claim 1.
Yaglikci and Kang fail to explicitly disclose further comprising: throttling instruction execution for the thread by reducing an instruction fetch rate of the thread by lowering a rate of branch predictions for the thread.
However, in an analogous art, Ferholl discloses further comprising: throttling instruction execution for the thread by reducing an instruction fetch rate of the thread by lowering a rate of branch predictions for the thread (Ferholl, [0005], [0014], [0032], [0035], describes sending a THROTTLE signal for instruction execution for the thread by reducing the instruction fetch rate of the tread by lower the branch predictions for the thread)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ferholl with the method and system of Yaglikci and Kang to include further comprising: throttling instruction execution for the thread by reducing an instruction fetch rate of the thread by lowering a rate of branch predictions for the thread. One would have been motivated to reduce the power consumption of the processor in the information handling system (Ferholl, [0004]).
Regarding claim 10, Yaglikci and Kang disclose the processing device of claim 9.
Yaglikci and Kang fail to explicitly disclose wherein the at least one second circuit includes: a branch prediction circuit configured to throttle the instruction execution for the thread by lowering a rate of branch predictions for the thread.
However, in an analogous art, Ferholl discloses wherein the at least one second circuit includes: a branch prediction circuit configured to throttle the instruction execution for the thread by lowering a rate of branch predictions for the thread, (Ferholl, [0013] describes a branch prediction circuit; [0005], [0014], [0032], [0035], describes sending a THROTTLE signal for instruction execution for the thread by reducing the instruction fetch rate of the tread by lower the branch predictions for the thread)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ferholl with the method and system of Yaglikci and Kang to include wherein the at least one second circuit includes: a branch prediction circuit configured to throttle the instruction execution for the thread by lowering a rate of branch predictions for the thread. One would have been motivated to reduce the power consumption of the processor in the information handling system (Ferholl, [0004]).
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yaglikci et al (“Yaglikci,” “BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Pages 345-358, April 22, 2021) in view of Kang et al (“Kang,” US 7,886,131) and further in view of Roberts et al (“Roberts,” US 20220058132).
Regarding claim 4, Yaglikci and Kang disclose the method of claim 1,
Yaglikci and Kang fail to explicitly disclose further comprising:
throttling instruction execution for the thread by reducing an instruction fetch rate of the thread by converting at least one instruction cache hit to an instruction cache miss.
However, in an analogous art, Roberts discloses further comprising: throttling instruction execution for the thread by reducing an instruction fetch rate of the thread by converting at least one instruction cache hit to an instruction cache miss, (Roberts, [0040] describes controlling instruction execution [throttling]; [0109], [0035]-[0036], [0049], [0087] describes reducing a prefetch rate [instruction fetch rate] by changing a cache hit rate to an instruction cache miss; [0020] describes a program [thread])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Roberts with the method and system of Yaglikci and Kang to include further comprising:
throttling instruction execution for the thread by reducing an instruction fetch rate of the thread by converting at least one instruction cache hit to an instruction cache miss. One would have been motivated to efficiently handle different prefetching environments, (Roberts, [0038]).
Regarding claim 11, Yaglikci and Kang disclose the processing device of claim 9.
Yaglikci and Kang fail to explicitly disclose wherein the at least one second circuit includes: instruction fetch circuitry configured to throttle the instruction execution for the thread by converting at least one instruction cache hit to an instruction cache miss.
However, in an analogous art, Roberts discloses wherein the at least one second circuit includes: instruction fetch circuitry configured to throttle the instruction execution for the thread by converting at least one instruction cache hit to an instruction cache miss, (Roberts, [0044], circuitry for prefetch; [0040] describes controlling instruction execution [throttling]; [0109], [0035]-[0036], [0049], [0087] describes reducing a prefetch rate [instruction fetch rate] by changing a cache hit rate to an instruction cache miss; [0020] describes a program [thread])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Roberts with the method and system of Yaglikci and Kang to include wherein the at least one second circuit includes: instruction fetch circuitry configured to throttle the instruction execution for the thread by converting at least one instruction cache hit to an instruction cache miss. One would have been motivated to efficiently handle different prefetching environments, (Roberts, [0038]).
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yaglikci et al (“Yaglikci,” “BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Pages 345-358, April 22, 2021) in view of Kang et al (“Kang,” US 7,886,131) and further in view of Busaba et al (“Busaba,” US 20140082626)
Regarding claim 5, Yaglikci and Kang disclose the method of claim 1.
Yaglikci and Kang fail to explicitly disclose further comprising:
throttling instruction execution for the thread by delaying dispatch of one or more instructions in the thread.
However, in an analogous art, Busaba discloses further comprising:
throttling instruction execution for the thread by delaying dispatch of one or more instructions in the thread (Busaba, [0039] describes throttling; [0032] describes throttling instruction execution by delaying the dispatch of the instruction for the low-priority thread).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Busaba with the method and system of Yaglikci and Kang to include further comprising: throttling instruction execution for the thread by delaying dispatch of one or more instructions in the thread. One would have been motivated to manage resources within the computing environment to be used in execution of threads (Busaba, [0002]).
Regarding claim 12, Yaglikci and Kang disclose the processing device of claim 9.
Yaglikci and Kang fail to explicitly disclose wherein the at least one second circuit includes: a dispatch circuit configured to throttle the instruction execution for the thread by delaying dispatch of one or more instructions in the thread.
However, in an analogous art, Busaba discloses wherein the at least one second circuit includes: a dispatch circuit configured to throttle the instruction execution for the thread by delaying dispatch of one or more instructions in the thread, (Busaba, [0044] describes circuitry; [0039] describes throttling; [0032] describes throttling instruction execution by delaying the dispatch of the instruction for the low-priority thread).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Busaba with the method and system of Yaglikci and Kang to include wherein the at least one second circuit includes: a dispatch circuit configured to throttle the instruction execution for the thread by delaying dispatch of one or more instructions in the thread. One would have been motivated to manage resources within the computing environment to be used in execution of threads (Busaba, [0002]).
Claims 6-7 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yaglikci et al (“Yaglikci,” “BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Pages 345-358, April 22, 2021) in view of Kang et al (“Kang,” US 7,886,131) and further in view of Ingram et al (“Ingram,” US 20220188038).
Regarding claim 6, Yaglikci and Kang disclose the method of claim 1.
Yaglikci and Kang fail to explicitly disclose further comprising:
throttling instruction execution for the thread by delaying generation of a virtual address for at least one memory access instruction in the thread.
However, in an analogous art, Ingram discloses further comprising:
throttling instruction execution for the thread by delaying generation of a virtual address for at least one memory access instruction in the thread (Ingram, [0026]-[0028], [0032], [0048], [0084] describes throttling for the thread by delaying the creation of a virtual memory address for at least one memory access instruction in the thread using a retention policy)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ingram with the method and system of Yaglikci and Kang to include further comprising: throttling instruction execution for the thread by delaying generation of a virtual address for at least one memory access instruction in the thread. One would have been motivated to trigger prefetching of memory address translations for memory access requests to be issued by a memory access component of a processor in a data processing system to a memory management function in the data processing system (Ingram, [0008]).
Regarding claim 7, Yaglikci and Kang disclose the method of claim 1.
Yaglikci and Kang fail to explicitly disclose further comprising:
throttling instruction execution for the thread by delaying a memory address translation for at least one memory access instruction in the thread.
However, in an analogous art, Ingram discloses further comprising:
throttling instruction execution for the thread by delaying a memory address translation for at least one memory access instruction in the thread, (Ingram, [0026]-[0028], [0032] describes throttling for the thread by delaying a memory address translation for at least one memory access instruction in the thread using a retention policy)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ingram with the method and system of Yaglikci and Kang to include further comprising:
throttling instruction execution for the thread by delaying a memory address translation for at least one memory access instruction in the thread. One would have been motivated to trigger prefetching of memory address translations for memory access requests to be issued by a memory access component of a processor in a data processing system to a memory management function in the data processing system (Ingram, [0008]).
Regarding claim 13, Yaglikci and Kang disclose the processing device of claim 9.
Yaglikci and Kang fail to explicitly disclose wherein the at least one second circuit includes: an instruction picker circuit configured to throttle the instruction execution for the thread by delaying generation of a virtual address for at least one memory access instruction in the thread.
However, in an analogous art, Ingram discloses wherein the at least one second circuit includes: an instruction picker circuit configured to throttle the instruction execution for the thread by delaying generation of a virtual address for at least one memory access instruction in the thread (Ingram, [0009] describes circuitry; [0026]-[0028], [0032], [0048], [0084] describes throttling for the thread by delaying a the creation of a virtual memory address for at least one memory access instruction in the thread using a retention policy)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ingram with the method and system of Yaglikci and Kang to include wherein the at least one second circuit includes: throttling instruction execution for the thread by delaying generation of a virtual address for at least one memory access instruction in the thread. One would have been motivated to trigger prefetching of memory address translations for memory access requests to be issued by a memory access component of a processor in a data processing system to a memory management function in the data processing system (Ingram, [0008]).
Regarding claim 14, Yaglikci and Kang disclose the processing device of claim 9.
Yaglikci and Kang fail to explicitly disclose wherein the at least one second circuit includes: an address translation circuit configured to throttle the instruction execution for the thread by delaying a memory address translation for at least one memory access instruction in the thread.
However, in an analogous art, Ingram discloses wherein the at least one second circuit includes: an address translation circuit configured to throttle the instruction execution for the thread by delaying a memory address translation for at least one memory access instruction in the thread, (Ingram, [0009] describes circuitry; [0026]-[0028], [0032] describes throttling for the thread by delaying a memory address translation for at least one memory access instruction in the thread using a retention policy)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ingram with the method and system of Yaglikci and Kang to include wherein the at least one second circuit includes: throttling instruction execution for the thread by delaying a memory address translation for at least one memory access instruction in the thread. One would have been motivated to trigger prefetching of memory address translations for memory access requests to be issued by a memory access component of a processor in a data processing system to a memory management function in the data processing system (Ingram, [0008]).
Claims 8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yaglikci et al (“Yaglikci,” “BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Pages 345-358, April 22, 2021) in view of Kang et al (“Kang,” US 7,886,131) and further in view of Gendler et al (“Gendler,” US 20200310511)
Regarding claim 8, Yaglikci and Kang disclose the method of claim 1.
Yaglicki and Kang fail to explicitly disclose further comprising: throttling instruction execution for the thread by decreasing a clock frequency of at least one circuit executing the thread or a processor core executing the thread
However, in an analogous art, Gendler discloses further comprising: throttling instruction execution for the thread by decreasing a clock frequency of at least one circuit executing the thread or a processor core executing the thread (Gendler, [0267], [0306], [0058] describes in response to the indication, throttling instruction execution for a thread issuing accesses at least in part by lowering [decreasing] the operating frequency [clock frequency] of a processor core executing the thread)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Gendler with the method and system of Yaglikci and Kang to include further comprising: throttling instruction execution for the thread by decreasing a clock frequency of at least one circuit executing the thread or a processor core executing the thread. One would have been motivated to provide power management in computer processors (Gendler, [0001]).
Regarding claim 15, Yaglikci and Kang disclose the processing device of claim 9.
Yaglicki and Kang fail to explicitly disclose a dynamic voltage a frequency scaling control circuit configured to wherein the at least one second circuit includes: throttle the instruction execution for the thread by operating a processor core at a lower clock frequency
However, in an analogous art, Gendler discloses a dynamic voltage a frequency scaling control circuit configured to wherein the at least one second circuit includes: throttle the instruction execution for the thread by operating a processor core at a lower clock frequency (Gendler, [0047] describes a dynamic voltage frequency scaling (DVFS) hardware; [0267], [0306], [0058] describes in response to the indication, throttling instruction execution for a thread issuing accesses at least in part by lowering [decreasing] the operating frequency [clock frequency] of a processor core executing the thread)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Gendler with the method and system of Yaglikci and Kang to include a dynamic voltage a frequency scaling control circuit configured to wherein the at least one second circuit includes: throttle the instruction execution for the thread by operating a processor core at a lower clock frequency. One would have been motivated to provide power management in computer processors (Gendler, [0001]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yaglikci et al (“Yaglikci,” “BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Pages 345-358, April 22, 2021) in view of Kang et al (“Kang,” US 7,886,131) and further in view of Hall et al (“Hall,” US 20190034628).
Regarding claim 17, Yaglikci and Kang disclose the computing system of claim 16.
Yaglikci and Kang fail to explicitly disclose further comprising: a memory controller comprising the detection circuit, wherein the memory controller is configured to transmit the indication via an interconnect to a processing unit.
However, in an analogous art, Hall discloses further comprising: a memory controller comprising the detection circuit, (Hall, [0057] describes circuitry; [0033] describes detection; [0034] describes a memory controller [all of these components work together where the memory controller comprises a circuitry for detection]).
wherein the memory controller is configured to transmit the indication via an interconnect to a processing unit (Hall, FIG 2 shows a memory controller 204A that transmits an indication by CHIP Interconnect 206 to the processor core 212)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hall with the method and system of Yaglikci and Kang to include further comprising: a memory controller comprising the detection circuit, wherein the memory controller is configured to transmit the indication via an interconnect to a processing unit. One would have been motivated to provide secure memory implementation for secure execution of virtual machines (Hall, [0003]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yaglikci et al (“Yaglikci,” “BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Pages 345-358, April 22, 2021) in view of Kang et al (“Kang,” US 7,886,131) and further in view of Calciu et al (“Calciu,” US 20230022096).
Regarding claim 18, Yaglikci and Kang disclose the computing system of claim 16.
Yaglikci and Kang fail to explicitly disclose wherein for each access of the accesses: the detection circuit is further configured to count the number of accesses prior to transmission of a memory request for performing the accesses to a memory device via an interconnect.
However, in an analogous art, Calciu wherein for each access of the accesses: the detection circuit is further configured to count the number of accesses prior to transmission of a memory request for performing the accesses to a memory device via an interconnect, (Calciu, [0014], hardware [circuitry], [0026], [0032], [0020], [0023], describes counting the number of accesses prior to transmitting the memory request to perform the accesses to the memory device by the interconnect)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Calciu with the method and system of Yaglikci and Kang to wherein for each access of the accesses: the detection circuit is further configured to count the number of accesses prior to transmission of a memory request for performing the accesses to a memory device via an interconnect. One would have been motivated to provide a method and system for detecting a security threat in a computer system while an application program is executed on a processor of the computer system (Calciu, [0003]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yaglikci et al (“Yaglikci,” “BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Pages 345-358, April 22, 2021) in view of Kang et al (“Kang,” US 7,886,131) and further in view of Brandl et al (“Brandl,” US 20150221358).
Regarding claim 20, Yaglikci and Kang disclose the computing system of claim 16.
Yaglikci further discloses wherein: the memory region is a memory row; (Yaglikci, Page 346, Left Column, Third Paragraph, Right Column, Lines 1-67 under Our Goal and Key Mechanism describes memory with rows)
and the detection circuit is further configured to: (Yaglikci, Page 346, Left Column, Third Paragraph, Right Column, Lines 1-67 under Our Goal and Key Mechanism describes circuitry for detection)
calculate a hash based on the thread identifier of the thread and a row identifier of the memory row, (Yaglikci, Page 352, Right Column, Under Section 6.1, Main Components of Blockhammer describes calculating the hash based on the thread identifier and a row ID of the memory row; also see Page 349, Under Section Implementing RowBlocker-HB; Page 348, Under Section RowBlocker-BL Mechanism which describes hashing in detail)
Yaglikci and Kang fail to explicitly disclose and associate the hash with a count value representing the number of accesses of the memory region.
However, in an analogous art, Brandl discloses and associate the hash with a count value representing the number of accesses of the memory region, (Brandl, [0049]-[0052], describes associating the hash with a count value that represents the number of accesses of the memory region of a hashed row in a timed window)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Brandl with the method and system of Yaglikci and Kang include wherein: the memory region is a memory row; and the detection circuit is further configured to: calculate a hash based on the thread identifier of the thread and a row identifier of the memory row, and associate the hash with a count value representing the number of accesses of the memory region. One would have been motivated to provide a memory controller for semiconductor memories (Brandl, [0001]).
Conclusion
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/JAMES J WILCOX/ Examiner, Art Unit 2439
/LUU T PHAM/ Supervisory Patent Examiner, Art Unit 2439