DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 27-29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 27, the limitation “a thermoelectric cooler layer adjacent a back side of the silicon substrate” is unclear. As explained by Applicant in the response filed 10/16/2025 the term "adjacent" refers to layers or components that are in physical contact with each other as defined in the instant specification (see para [0028 ] of US 20230207421 A1). Applicant explains that there is no layer or component between the stated adjacent layers or components. For example, a layer X that is adjacent to a layer Y refers to a layer that is in physical contact with layer Y.
Applicant elected Fig. 3, drawn to Species B-2 reproduced below in their response on 5/13/2025.
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It is noted that in Fig. 3 of Applicant’s own specification there is a plane of material, layer 304, which separates the thermoelectric cooler (110) in layer (130 please see Fig. 2 which shows analogous layer) from the silicon substrate (132 please see Fig. 2 which shows analogous layer). So it is unclear how given the definition above the thermoelectric cooler is adjacent a back side of the silicon substrate in Applicant’s own elected embodiment of Fig. 3.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 8, 9, 11, 15, 17 and 31 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Hsu (US 2010/0176506 A1).
Regarding claims 1 and 17, Hsu discloses a system comprising:
an integrated circuit package(3D chip stack see Figs. 1 and 2a-2k, including any of elements 140 and/or 110 and/or 120 and/or 130) comprising an integrated circuit die comprising (see 100, see Figs. 1 and 2a-2k [0002]):
one or more electronic components (upper chip 120 or lower chip 110, see active device structures shown in layer 120/110 [0013] and/or can include 102c/102a) in a top side of the integrated circuit die (100); and a thermoelectric cooler (see 130 [0013] and 132a or 132b, see Figure below) in a back side of the integrated circuit die (100). Note that top side is relative since no fixed reference is claimed, therefore either 110 or 120 can be considered top.
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Regarding claim 2, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses wherein the one or more electronic components (see active devices in 120) are in a substrate (120), wherein the thermoelectric cooler is in a layer (130) different from the substrate.
Regarding claim 3, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses wherein the substrate comprises silicon (through silicon vias are formed in 120, therefore substrate, 120, is silicon, [0013]), wherein the layer different from the substrate comprises polysilicon (thermoelectric elements are formed of doped polysilicon and are part of layer [0016]).
Regarding claim 8, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses a heat sink (140 [0013]), is attached to a back side of an integrated circuit die to dissipate heat from the thermoelectric cooler (130).
Regarding claim 9, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses further comprising one or more vias (102c, 102b, and or 102a) extending from the thermoelectric cooler to the one or more electronic components [0013].
Regarding claim 11, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses further comprising wherein the one or more vias are
filled with copper ([0014]).
Regarding claim 15, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses wherein the one or more electronic components comprise power delivery circuitry (102c/102b, [0013]).
Regarding claim 31, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses that integrated circuit die comprises a substrate (110) and that the thermoelectric cooler layer (132a, 132b, and 130) is directly formed on the substrate (110) in a monolithic fashion (see Figs. 2a-2k) and is formed by backside processing.
It is noted that the embodiment shown in Fig. 3 of Applicant’s specification includes a thermoelectric cooler with components which are constructed directly on a substrate (see Figs. 10-13).
Hsu discloses that the components of the thermoelectric cooler components are constructed directly on the substrate (see Figs. 2A-2k) and therefore are “monolithic” with the substrate as instantly claimed and shown in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17 and 31 above and in further view of Ibaraki (US 20100219525 A1).
Regarding claim 6, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose where the one or more electronic components comprise power circuitry, wherein the power circuitry is a power amplifier or a voltage regulator.
Ibaraki discloses that electronic components that are integrated with thermoelectric elements in semiconductor chips can include voltage controllers to regulate the amount of cooling provided by the thermoelectric ([0031]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hsu to further include a voltage regulator as the one or more power circuitry components because it will allow for regulating the amount of cooling as disclosed by Ibaraki.
However, modified Hsu does not disclose wherein a distance between the power circuitry and the thermoelectric cooler is less than 200 micrometers.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the distance between the power circuitry and the thermoelectric device of modified Hsu to be within the range claimed because doing so will allow for optimization of device size and layout.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17 and 31 above and in further view of Gu (US 20090321909 A1).
Regarding claim 30, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose wherein a thickness of the substrate is less than 100 micrometers.
Gu discloses that stacked IC devices can comprise IC circuits semiconductor substrates with thicknesses that range from 6-100 microns ([0002]) and that thicknesses can be chosen to optimize the balance between power density and lateral thermal conductivity ([0002][0014][0015]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the thicknesses of the substrate of Hsu to be within the range claimed because Gu discloses that this is an appropriate thickness for a substrate within an IC device and furthermore because it will allow for one to optimize power density and lateral thermal conductivity.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim(s) 10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17 and 31 above and in further view of Yan (US 2019/0164866 A1).
Regarding claims 10 and 12, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose that the thermal vias (102a [0013]) which are used to dissipate heat are filled with aluminum nitride or diamond and instead discloses that they are filled with copper ([0014]).
Yan discloses that in an integrated circuit structure thermal vias which are used to dissipate heat (128, 130) can filled with high thermal conductivity materials such as aluminum nitride or diamond ([0030]) instead of copper.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the filling materials of the thermal vias (102a) of Hsu to use aluminum nitride or diamond instead of copper as disclosed by Yan to optimize different properties of the via such as thermal conductivity and/or thermal expansion properties of the material.
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17 and 31 above and in further view of Dasgupta (US 2017/0221999 A1).
Regarding claim 13, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose wherein the one or more electronic components comprise a compound semiconductor radio-frequency amplifier, wherein the compound semiconductor comprises elements from Group III and Group V of the periodic table.
Dasgupta discloses a III-V RF power amplifier can be an electronic device integrated onto silicon wafer ([0042]) as part of a circuit ([0004]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the integrated circuit die of Hsu by having the electronic device in the silicon wafer be a III-V RF power amplifier because Dasgupta because Dasgupta discloses that these devices allow for high voltage applications ([0003]).
Claim(s) 14, 16, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17 and 31 above and in further view of Jeng (US 2021/0193637 A1).
Regarding claim 14, 16, and 19, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose:
wherein the one or more electronic components comprise logic, memory, and control circuitry
wherein the one or more electronic components comprise analog and mixed signal circuitry
wherein the system is a system-on-a-chip
Jeng discloses that electronic components (50) that are integrated onto a chip can include multiple electronic components (50) to form a system on a chip ([0027]) and furthermore that the one or more electronic components comprise logic (CPU [0027]), memory (RAM [0027]), and control circuitry (signal processing ports is considered control circuitry [0027]) or wherein the one or more electronic components comprise analog and mixed signal circuitry (The single device die may also integrate contain digital, analog, mixed-signal, and sometimes radio frequency signal processing functions [0027]) .
It would have been obvious to one of ordinary skill in the art at the time of the filing to modify the system of Hsu to include multiple electronic devices of the type disclosed by Jeng so as to form a system on a chip because Jeng discloses it was known in the art that multiple electronic devices can be integrated onto a substrate to be form a system on a chip.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17 and 31 above and in further view of Jeng (US 2021/0193637 A1) and in view of Dogiamis (US 2019/0334227 A1).
Regarding claim 18, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose wherein the integrated circuit package is a processor, further comprising one or more memory devices communicatively coupled to the processor.
Jeng discloses that an integrated circuit package can comprises a processor and memory devices and input and output ports ([0027]), however, does not disclose that the processor and memory are communicatively coupled.
Dogiamis discloses that a processor is a device that a “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory ([0041]).
It would have been obvious to one of ordinary skill in the art at the time of the filing to modify the system of Hsu to include an integrated circuit package that comprises a processor with memory as disclosed by Jeng which are communicatively coupled as disclosed by Dogiamis because Jung discloses it was known in the art to have an integrated circuit package that comprises a processor with memory and Dogiamis discloses it was known in the art to have them be communicatively coupled.
Claim(s) 27-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) in view of Dasgupta (US 2017/0221999 A1).
Regarding claim 27, Hsu discloses an integrated circuit die comprising (see 100, see Figs. 1 and 2a-2k [0002]):
a silicon substrate (120/110, through silicon vias are formed in 120/110, therefore substrate, 120/110, is silicon, [0013])
one or more electronic components disposed on a top side of the silicon substrate (active devices are shown within layer 120/110 which can be considered on top side of silicon substrate 120 or 110); and a thermoelectric cooler (see 130 [0013] and 132a or 132b) adjacent to a back side of silicon substrate (120/110) wherein the thermoelectric cooler is defined in the thermoelectric cooler layer (130 including substrate layers 132a or 132b). Note that top side is relative since no fixed reference is claimed, therefore either 110 or 120 can be considered top.
However, Hsu does not disclose wherein the one or more electronic components comprise a compound semiconductor radio-frequency power amplifier, wherein the compound semiconductor comprises elements from Group III and Group V of the periodic table.
Dasgupta discloses a III-V RF power amplifier can be an electronic device integrated onto silicon wafer ([0042]) as part of a circuit ([0004]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the integrated circuit die of Hsu by having the electronic device in the silicon wafer be a III-V RF power amplifier because Dasgupta because Dasgupta discloses that these devices allow for high voltage applications ([0003]).
Regarding claims 28 and 29, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses that the thermoelectric cooler layer is directly formed on the substrate (110) in a monolithic fashion (see Figs. 2a-2k) and is formed by backside processing (Note that top side and/or bottom side is relative since no fixed reference is claimed, therefore either 110 or 120 can be considered top or bottom).
It is noted that the embodiment shown in Fig. 3 of Applicant’s specification includes a thermoelectric cooler with components which are constructed directly on a substrate (see Figs. 10-13).
Hsu discloses that the components of the thermoelectric cooler components are constructed directly on the substrate (see Figs. 2A-2k) and therefore are “monolithic” with the substrate as instantly claimed and shown in the specification.
Furthermore, with respect to “backside processing” the cited prior art teaches all of the positively recited structure of the claimed apparatus or product. The determination of patentability is based upon the apparatus structure itself. The patentability of a product or apparatus does not depend on its method of production or formation. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. See In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (see MPEP § 2113).
Response to Arguments
Applicant argues Hsu does not teach a thermoelectric cooler in a back side of the integrated circuit die, as required by the claim. Rather, Hsu clearly teaches that the TEC plate 130 is a separate component from the "two chips 110, 120." Hsu, [0013]. While each of the chips 110, 120" may correspond to the "integrated circuit die" of the claim, neither of the chips 110, 120 includes the TEC plate 130 in a back side of the die itself.
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Applicant elected Fig. 3 please see reply 5/13/2025 drawn to Fig. 3. As noted in Applicant’s own specification the integrated circuit die (102) and shows a thermoelectric cooler (110) and an active device (104) reproduced in Fig. 3 below. The thermoelectric device (110) is embedded within semiconducting layer (130).
Hsu discloses a substantially similar structure (See below) and given the interpretation above and the guidance provided in the specification Hsu teaches a thermoelectric cooler in a back side of the integrated circuit die.
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No specific structure was recited for die or side. Therefore, the front side and back side of the die (100) of Hsu can be interpreted as presented below:
Furthermore, the definition of side is “a place, space, or direction with respect to a center or to a line of division”. Broadly and reasonable Hsu discloses “a thermoelectric cooler in a back side of the integrated circuit die.”
Applicant further argues the thermoelectric cooler of Hsu is not adjacent to the silicon substrate (i.e., the chips 110, 120). Applicant notes that as used herein, the term "adjacent" refers to layers or components that are in physical contact with each other. That is, there is no layer or component between the stated adjacent layers or components. For example, a layer X that is adjacent to a layer Y refers to a layer that is in physical contact with layer Y.
It is noted that in Fig. 3 of Applicant’s own specification there is a plane of material, layer 304, which separates the thermoelectric cooler (110) in layer (130) from the silicon substrate (132). Please see Figure below. So it is unclear how given the definition above the thermoelectric cooler is adjacent in Applicant’s own elected embodiment of Fig. 3.
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Examiner notes that layers 132a and/or 132b can be a part of the thermoelectric cooler. Since layers 132a and/or 132b are part of the thermoelectric cooler, the thermoelectric cooler is adjacent to the silicon substrate (110/120).
During the interview Examiner noted that claim 28 which required that the substrate and the thermoelectric layer are monolithic was not present in Hsu. However, after careful reconsideration and discussion with SPE Jeffrey Barton it was found that Hsu does disclose “wherein the substrate and the thermoelectric cooler are monolithic” in light of Applicant’s specification. Applicant’s specification discloses that the thermoelectric cooler is directly formed on the substrate (please see Figs. 8-13). In a similar manner Hsu’s device is directly formed on the substrate see Figs. 2A-2K. Therefore, Hsu discloses wherein the substrate and the thermoelectric cooler are monolithic.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVINA PILLAY whose telephone number is (571)270-1180. The examiner can normally be reached Monday-Friday 9:30-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey T Barton can be reached at 517-272-1307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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DEVINA PILLAY
Primary Examiner
Art Unit 1726
/DEVINA PILLAY/ Primary Examiner, Art Unit 1726