DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-3, 8, 9, 11, 15, 17, 31 and 32 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Hsu (US 2010/0176506 A1).
Regarding claims 1 and 17, Hsu discloses a system comprising:
an integrated circuit package(3D chip stack see Figs. 1 and 2a-2k, including any of elements 140 and/or 110 and/or 120 and/or 130) comprising an integrated circuit die comprising (see 100, see Figs. 1 and 2a-2k [0002]):
one or more electronic components (upper chip 120 or lower chip 110, see active device structures shown in layer 120/110 [0013] and/or can include 102c/102a) in a top side of the integrated circuit die (100); and a thermoelectric cooler (see 130 [0013] and 132a or 132b, see Figure below) in a back side of the integrated circuit die (100). Note that top side is relative since no fixed reference is claimed, therefore either 110 or 120 can be considered top.
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Regarding claim 2, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses wherein the one or more electronic components (see active devices in 120) are in a substrate (120), wherein the thermoelectric cooler is in a layer (130) different from the substrate.
Regarding claim 3, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses wherein the substrate comprises silicon (through silicon vias are formed in 120, therefore substrate, 120, is silicon, [0013]), wherein the layer different from the substrate comprises polysilicon (thermoelectric elements are formed of doped polysilicon and are part of layer [0016]).
Regarding claim 8, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses a heat sink (140 [0013]), is attached to a back side of an integrated circuit die to dissipate heat from the thermoelectric cooler (130).
Regarding claim 9, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses further comprising one or more vias (102c, 102b, and or 102a) extending from the thermoelectric cooler to the one or more electronic components [0013].
Regarding claim 11, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses further comprising wherein the one or more vias are
filled with copper ([0014]).
Regarding claim 15, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses wherein the one or more electronic components comprise power delivery circuitry (102c/102b, [0013]).
Regarding claim 31, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses that integrated circuit die comprises a substrate (110) and that the thermoelectric cooler layer (132a, 132b, and 130) is directly formed on the substrate (110) in a monolithic fashion (see Figs. 2a-2k) and is formed by backside processing.
It is noted that the embodiment shown in Fig. 3 of Applicant’s specification includes a thermoelectric cooler with components which are constructed directly on a substrate (see Figs. 10-13).
Hsu discloses that the components of the thermoelectric cooler components are constructed directly on the substrate (see Figs. 2A-2k) and therefore are “monolithic” with the substrate as instantly claimed and shown in the specification.
Regarding claim 32, Hsu discloses all of the claim limitations as set forth above.
In addition Hsu discloses wherein the integrated circuit die (100) comprises a substrate (all of layers which comprise 120 other than those which form electronic device and electrical interconnections and all of layers which comprise 130 other than those which form thermoelectric p and n type elements and metallic connectors and/or all of layers which comprise 110 other than those which form electronic device and metallic portions) wherein the one or more electronic components (upper chip 120 or lower chip 110, see active device structures shown in layer 120/110 [0013] and/or can include 102c/102a) and semiconductor portions of thermoelectric elements (portions which form p and n-type elements) are defined in the substrate (all of layers which comprise 120 other than those which form electronic device and electrical interconnections and all of layers which comprise 130 other than those which form thermoelectric p and n type elements and metallic connectors and/or all of layers which comprise 110 other than those which form electronic device and metallic portions).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17, 31 and 32 above and in further view of Ibaraki (US 20100219525 A1).
Regarding claim 6, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose where the one or more electronic components comprise power circuitry, wherein the power circuitry is a power amplifier or a voltage regulator.
Ibaraki discloses that electronic components that are integrated with thermoelectric elements in semiconductor chips can include voltage controllers to regulate the amount of cooling provided by the thermoelectric ([0031]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hsu to further include a voltage regulator as the one or more power circuitry components because it will allow for regulating the amount of cooling as disclosed by Ibaraki.
However, modified Hsu does not disclose wherein a distance between the power circuitry and the thermoelectric cooler is less than 200 micrometers.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the distance between the power circuitry and the thermoelectric device of modified Hsu to be within the range claimed because doing so will allow for optimization of device size and layout.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17 and 31 above and in further view of Gu (US 20090321909 A1).
Regarding claim 30, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose wherein a thickness of the substrate is less than 100 micrometers.
Gu discloses that stacked IC devices can comprise IC circuits semiconductor substrates with thicknesses that range from 6-100 microns ([0002]) and that thicknesses can be chosen to optimize the balance between power density and lateral thermal conductivity ([0002][0014][0015]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the thicknesses of the substrate of Hsu to be within the range claimed because Gu discloses that this is an appropriate thickness for a substrate within an IC device and furthermore because it will allow for one to optimize power density and lateral thermal conductivity.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim(s) 10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17 and 31 above and in further view of Yan (US 2019/0164866 A1).
Regarding claims 10 and 12, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose that the thermal vias (102a [0013]) which are used to dissipate heat are filled with aluminum nitride or diamond and instead discloses that they are filled with copper ([0014]).
Yan discloses that in an integrated circuit structure thermal vias which are used to dissipate heat (128, 130) can filled with high thermal conductivity materials such as aluminum nitride or diamond ([0030]) instead of copper.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the filling materials of the thermal vias (102a) of Hsu to use aluminum nitride or diamond instead of copper as disclosed by Yan to optimize different properties of the via such as thermal conductivity and/or thermal expansion properties of the material.
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17 and 31 above and in further view of Dasgupta (US 2017/0221999 A1).
Regarding claim 13, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose wherein the one or more electronic components comprise a compound semiconductor radio-frequency amplifier, wherein the compound semiconductor comprises elements from Group III and Group V of the periodic table.
Dasgupta discloses a III-V RF power amplifier can be an electronic device integrated onto silicon wafer ([0042]) as part of a circuit ([0004]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the integrated circuit die of Hsu by having the electronic device in the silicon wafer be a III-V RF power amplifier because Dasgupta because Dasgupta discloses that these devices allow for high voltage applications ([0003]).
Claim(s) 14 and16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17 and 31 above and in further view of Jeng (US 2021/0193637 A1).
Regarding claim 14 and 16, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose:
wherein the one or more electronic components comprise logic, memory, and control circuitry
wherein the one or more electronic components comprise analog and mixed signal circuitry
Jeng discloses that electronic components (50) that are integrated onto a chip can include multiple electronic components (50) to form a system on a chip ([0027]) and furthermore that the one or more electronic components comprise logic (CPU [0027]), memory (RAM [0027]), and control circuitry (signal processing ports is considered control circuitry [0027]) or wherein the one or more electronic components comprise analog and mixed signal circuitry (The single device die may also integrate contain digital, analog, mixed-signal, and sometimes radio frequency signal processing functions [0027]) .
It would have been obvious to one of ordinary skill in the art at the time of the filing to modify the system of Hsu to include multiple electronic devices of the type disclosed by Jeng so as to form a system on a chip because Jeng discloses it was known in the art that multiple electronic devices can be integrated onto a substrate to be form a system on a chip.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) as applied to claims 1-3, 8, 9, 11, 15, 17 and 31 above and in further view of Jeng (US 2021/0193637 A1) and in view of Dogiamis (US 2019/0334227 A1).
Regarding claim 18, Hsu discloses all of the claim limitations as set forth above.
However, Hsu does not disclose wherein the integrated circuit package is a processor, further comprising one or more memory devices communicatively coupled to the processor.
Jeng discloses that an integrated circuit package can comprises a processor and memory devices and input and output ports ([0027]), however, does not disclose that the processor and memory are communicatively coupled.
Dogiamis discloses that a processor is a device that a “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory ([0041]).
It would have been obvious to one of ordinary skill in the art at the time of the filing to modify the system of Hsu to include an integrated circuit package that comprises a processor with memory as disclosed by Jeng which are communicatively coupled as disclosed by Dogiamis because Jung discloses it was known in the art to have an integrated circuit package that comprises a processor with memory and Dogiamis discloses it was known in the art to have them be communicatively coupled.
Claim(s) 27-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2010/0176506 A1) in view of Dasgupta (US 2017/0221999 A1).
Regarding claim 27, Hsu discloses an integrated circuit die comprising (see 100, see Figs. 1 and 2a-2k [0002]):
a silicon substrate (120/110, through silicon vias are formed in 120/110, therefore substrate, 120/110, is silicon, [0013])
one or more electronic components disposed on a top side of the silicon substrate (active devices are shown within layer 120/110 which can be considered on top side of silicon substrate 120 or 110); and a thermoelectric cooler (see 130 [0013] and 132a or 132b) adjacent to a back side of silicon substrate (120/110) wherein the thermoelectric cooler is defined in the thermoelectric cooler layer (130 including substrate layers 132a or 132b). Note that top side is relative since no fixed reference is claimed, therefore either 110 or 120 can be considered top.
However, Hsu does not disclose wherein the one or more electronic components comprise a compound semiconductor radio-frequency power amplifier, wherein the compound semiconductor comprises elements from Group III and Group V of the periodic table.
Dasgupta discloses a III-V RF power amplifier can be an electronic device integrated onto silicon wafer ([0042]) as part of a circuit ([0004]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the integrated circuit die of Hsu by having the electronic device in the silicon wafer be a III-V RF power amplifier because Dasgupta because Dasgupta discloses that these devices allow for high voltage applications ([0003]).
Regarding claims 28 and 29, Hsu discloses all of the claim limitations as set forth above.
In addition, Hsu discloses that the thermoelectric cooler layer is directly formed on the substrate (110) in a monolithic fashion (see Figs. 2a-2k) and is formed by backside processing (Note that top side and/or bottom side is relative since no fixed reference is claimed, therefore either 110 or 120 can be considered top or bottom).
It is noted that the embodiment shown in Fig. 3 of Applicant’s specification includes a thermoelectric cooler with components which are constructed directly on a substrate (see Figs. 10-13).
Hsu discloses that the components of the thermoelectric cooler components are constructed directly on the substrate (see Figs. 2A-2k) and therefore are “monolithic” with the substrate as instantly claimed and shown in the specification.
Furthermore, with respect to “backside processing” the cited prior art teaches all of the positively recited structure of the claimed apparatus or product. The determination of patentability is based upon the apparatus structure itself. The patentability of a product or apparatus does not depend on its method of production or formation. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. See In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (see MPEP § 2113).
Claim(s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Griebenow (US 20110291269 A1).
Regarding claim 33, Griebenow discloses an integrated circuit die comprising (see Figs. 1k and Fig. 1l, 120 [0030]):
one or more electronic components (devices shown as 123B, 123C, 123D in Fig. 1k, which are embedded in layer 123B shown in Fig. 1l [0046]-[0048][0030]) in a top side of the integrated circuit die(see Figs. 1k and Fig. 1l, 120 [0030]):; and
a thermoelectric cooler (128B, 130A and 135 [0039][0040], Peltier elements) in a back side of the integrated circuit die (120) wherein the integrated circuit die comprises a substrate (121, 122, 123A, 123B), wherein the one or more electronic components (devices shown as 123B, 123C, 123D in Fig. 1k, which are embedded in layer 123B shown in Fig. 1l [0046]-[0048][0030]) and semiconductor portions (128B, 130A[0039][0040]) of the thermoelectric cooler are defined in the substrate (121, 122, 123A, 123B).
However, Griebenow does not disclose wherein the substrate is a single crystal of silicon, and wherein the semiconductor portions of the thermoelectric cooler are doped regions of the single crystal of silicon.
Griebenow discloses the semiconductor material in the device level 123, in combination with the buried insulating material 122, may form an SOI (semiconductor- or silicon-on-insulator) configuration, while, in other cases, the material 122 may be omitted and the crystalline semiconducting material of the device level 123 may represent a crystalline portion of the substrate 121, thereby forming a bulk configuration ([0030]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the substrate of Griebenow to include a bulk configuration which would include the device layers 123 and layer 121 both being part of a bulk crystalline semiconducting material forming a bulk configuration because Griebenow teaches it is appropriate to do so.
Modified Griebenow discloses that the substrate is a single bulk semiconducting material and discloses the semiconducting material can be silicon ([0030] the plurality of devices 120 may be provided as a single wafer and crystalline portion of the substrate 121, the device 120 may comprise a substrate 121, such as a semiconductor material, for instance in the form of silicon and the like..).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the crystalline silicon bulk substrate of Griebenow to be monocrystalline silicon because Griebenow discloses that semiconducting wafer and silicon materials are appropriate for use.
Modified Griebenow discloses wherein the semiconductor portions (128A and 130B [0040]) of the thermoelectric cooler are doped regions of the single crystal of silicon.
Response to Arguments
With regards to claim 1, Applicant argues Hsu does not teach a thermoelectric cooler in a back side of an integrated circuit die, as required by claim 1. If either chip 110 or chip 120 is the alleged integrated circuit die, then Hsu does not teach that TEC plate 130 is in a back side of that integrated circuit die. Instead, the TEC plate 130 is a separate structure outside the chip and separated from the chip by at least one coupling layer.
As noted in the rejection above the integrated circuit dies is defined by Hsu as set forth in the rejection above as an integrated circuit package(3D chip stack see Figs. 1 and 2a-2k, including any of elements 140 and/or 110 and/or 120 and/or 130). The definition of side is “a place, space, or direction with respect to a center or to a line of division”.
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Given the broadest and reasonable interpretation for the limitation in claim 1 of “a thermoelectric cooler in a back side of the integrated circuit die” Hsu discloses a thermoelectric cooler in a back side of the integrated circuit die (see drawing below for back side interpretation).
With regards to claim 1, Applicant argues that the Office Action has not identified any disclosure in Hsu that structure 100 as a whole is an integrated circuit die.
As noted in the rejection of claim 1 Hsu discloses all of the structural components required for the claimed integrated circuit die of claim 1. Hsu discloses that the integrated circuit die (see 100, see Figs. 1 and 2a-2k [0002]) comprises: one or more electronic components (upper chip 120 or lower chip 110, see active device structures shown in layer 120/110 [0013] and/or can include 102c/102a) in a top side of the integrated circuit die (100); and a thermoelectric cooler (see 130 [0013] and 132a or 132b, see Figure below) in a back side of the integrated circuit die (100). Since Hsu discloses all of the structural components required for the integrated circuit die, Hsu broadly and reasonably discloses the claimed integrated circuit die.
Furthermore, Hsu discloses in paragraph [0001]-[0002] "The disclosure relates generally to integrated circuits (ICs), and, more particularly, to a structure and method for cooling a three dimensional (3D) chip stack "and "A 3D chip stack allows designers or assemblers greater flexibility to stack various chip technologies into small, high performance functional blocks. For example, flash memories combined with SRAM, DRAM, DSP, or microprocessors are all candidates for this 3D chip stack technique." A microprocessor necessarily has an integrated circuit, therefore Hsu discloses a die with an integrated circuit.
With regards to claim 6, Applicant argues Ibaraki does not disclose a voltage regulator. Ibaraki states that "control of heat conduction" may include measuring and monitoring the temperature of each semiconductor chip and "controlling of a voltage applied to the Peltier element using an associated control circuit based on the result of the measuring and monitoring." Applicant argues that controlling a voltage applied to a Peltier element is not the same as disclosing a voltage regulator.
A regulator is defined as "a device for maintaining a designated characteristic, as voltage or current, at a predetermined value, or for varying it according to a predetermined plan" as defined by dictionary.com. Ibraki discloses a device form maintaining a designated characteristic, a voltage, according to a predetermined plan (temperature setting) see paragraph [0031] of Ibraki. The device controlling the voltage of Ibraki broadly and reasonably reads on the claimed “voltage regulator”.
With regards to claim 6, Applicant argues that the Office Action further asserted on p. 8 that it would have been obvious to modify the distance between the power circuitry and the thermoelectric device to be less than 200 micrometers as a matter of device-size and layout optimization. Applicant respectfully disagrees.
Applicant argues that the Office Action does not identify any power amplifier or voltage regulator in the asserted Hsu-Ibaraki combination, much less identify a power amplifier or voltage regulator having a distance of less than 200 micrometers from the thermoelectric cooler.
As noted above Ibraki discloses a voltage regular. As noted in the rejection of claim 6 there is motivation to optimize the size of wiring between elements because doing so will allow for optimization of device size and layout. Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
With regards to claim 27, Applicant argues that Hsu does not teach "a thermoelectric cooler layer adjacent a back side of the silicon substrate," as required by claim 27 since Hsu does not describe coupling layers 132a and 132b as part of the TEC plate. Applicant argues to the contrary, Hsu distinguishes the TEC plate 130 from the coupling layers 132a and 132b, and states that the coupling layers are placed between the TEC plate and the chips. Hsu,[0014]. Applicant argues Hsu further explains that coupling layer 132a is deposited first, followed by conducting layer 234 and thermoelectric material 236. Hsu [0016]. Applicant argues that description again distinguishes the coupling layer from the thermoelectric material and from the TEC plate structure.
Claim 27 recites "a thermoelectric cooler layer adjacent a back side of the silicon substrate". Given the structure for the thermoelectric cooler recited in claim 27, layers 132a and/or 132b of Hsu can be considered to be a part of the thermoelectric cooler. Since layers 132a and/or 132b are part of the thermoelectric cooler, the thermoelectric cooler is adjacent to the silicon substrate (110/120).
Applicant argues that Hsu does not disclose claim 28 which recites "wherein the substrate and the thermoelectric cooler layer are monolithic."
The definition of monolithic is "consisting of or constituting a single unit" according to merriam-webster.com. Additionally, the word monolithic in the art is known to include, for example, monolithic 3D integration, in which stacks of circuits are sequentially fabricated on top of each other (see Sachid "Monolithic 3D CMOS Using Layered Semiconductors" left column, pg. 1). Hsu discloses that the thermoelectric cooler layer is directly formed on the substrate (110) (see Figs. 2a-2k) and is formed by backside processing (Note that top side and/or bottom side is relative since no fixed reference is claimed, therefore either 110 or 120 can be considered top or bottom) on the substrate (110) to form a single unit. Therefore Hsu broadly and reasonable recites the claim limitation "wherein the substrate and the thermoelectric cooler layer are monolithic."
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVINA PILLAY whose telephone number is (571)270-1180. The examiner can normally be reached Monday-Friday 9:30-6:00.
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DEVINA PILLAY
Primary Examiner
Art Unit 1726
/DEVINA PILLAY/Primary Examiner, Art Unit 1726
Prosecution Insights