DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 26, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Response to Amendment
The amendment filed February 24, 2026 has been entered. Claims 1-20 remain pending in the instant application.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 5, 12, and 19 are objected to because of the following informalities:
Claim 5 recites “determine the power estimation model converges,” which should be corrected to “determine that the power estimation model converges.”
Claims 12 and 19 recite substantially similar limitations to Claim 5, and should be corrected accordingly.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-11, and 15-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sankaralingam (U.S. Pat. No. 8,201,121 B1), hereinafter Sankaralingam.
Regarding Claim 1, Sankaralingam teaches A processor comprising: circuitry configured to: access a memory storing structural data describing an integrated circuit (“Referring now to FIG. 6, a computing system 600 is illustrated that may be used to perform some or all of the processes in accordance with a number of embodiments of the invention. In one embodiment of the invention, the computing system 600 includes a processor 610, a memory 620, a removable media drive 630, and a hard disk drive 640.”) (e.g., column 13, lines 23-28).
generate power analysis results for a subset of portions of the integrated circuit (“At process block 304, the integrated circuit is partitioned 15 into N-partitions having a maximum of K generic logic gates while spreading out the synchronous circuits among the N partitions […] At process block 306, a predetermined number (X) of the N partitions are selected in the circuit for further analysis to determine the average power correction ratio […] At process block 318, a reasonably accurate power consumption (C) is calculated using the given selected synthesized partition.”) (e.g., column 6, lines 14-17 and 29-33; column 7, lines 43-45).
create, based on the power analysis results for the subset, a power estimation model configured to estimate power for other portions of the integrated circuit (“At process block 323, a determination of the average power correction ratio (Rave) for the integrated circuit is determined. The average power correction ratio (Rave) is used to estimate the power consumption for the entire integrated circuit.” The average power correction ratio is a power estimation model based on the partitions.) (e.g., column 8, lines 11-14).
and produce a power characterization of the integrated circuit using the power analysis results for the selected subset and power estimates generated by the power estimation model for the other portions (“The average power correction ratio (Rave) is used to estimate the power consumption for the entire integrated circuit.”) (e.g., column 8, lines 13-14).
and wherein creation of the power estimation model excludes power analysis results for at least one of the other portions during training (“The X partitions are a subset of the N-partitions such that the value of X is less than the value of N.”) (e.g., column 6, lines 35-36).
Regarding Claim 2, Sankaralingam teaches The processor as recited in claim 1. Sankaralingam further teaches wherein the circuitry is further configured to use capacitance related values corresponding to nodes of the integrated circuit as inputs to the power estimation model (“The static power consumption and dynamic switching power consumption of a mapped logic gate are calculated based on the propagated signal activity and the power characteristic information found in the technology library for the given gate. The power characteristic information from the library includes capacitance, supply voltage, power table, state dependent/independent power, etc.”) (e.g., column 6, lines 47-53).
Regarding Claim 3, Sankaralingam teaches The processor as recited in claim 1. Sankaralingam further teaches wherein: the power analysis results correspond to a first portion of the integrated circuit (“At process block 306, a predetermined number (X) of the N partitions are selected in the circuit for further analysis to determine the average power correction ratio.”) (e.g., column 6, lines 29-33).
and the power estimates generated by the power estimation model correspond to a second, different portion of the integrated circuit that is excluded from training of the power estimation model (“At process block 323, a determination of the average power correction ratio (Rave) for the integrated circuit is determined. The average power correction ratio (Rave) is used to estimate the power consumption for the entire integrated circuit.” The average power correction ratio is a power estimation model, which captures power estimates for partitions that have not been synthesized or analyzed.) (e.g., column 8, lines 11-14).
Regarding Claim 4, Sankaralingam teaches The processor as recited in claim 1. Sankaralingam further teaches wherein the power analysis results and the power estimates correspond to a pre-silicon model of the integrated circuit (“The embodiments of the invention solve the problem of early power consumption estimation of an integrated circuit design that is represented as a generic netlist ( e.g., an RTL netlist generated from RTL source) of generic logic gates.” An RTL netlist is a pre-silicon model of a digital circuit.) (e.g., column 2, lines 19-24).
Regarding Claims 8-11, the claims recite substantially similar limitations to Claims 1-4, respectively, and the claims are rejected under 35 U.S.C 102(a)(1) for the same reasons.
Regarding Claim 15, Sankaralingam teaches A computing system comprising: a memory configured to store: structural data describing functionality of an integrated circuit; a power estimation model (“Referring now to FIG. 6, a computing system 600 is illustrated that may be used to perform some or all of the processes in accordance with a number of embodiments of the invention. In one embodiment of the invention, the computing system 600 includes a processor 610, a memory 620, a removable media drive 630, and a hard disk drive 640.”) (e.g., column 13, lines 23-28).
The remaining limitations of Claim 15 recite substantially similar material to Claim 1, and the claim is rejected under 35 U.S.C 102(a)(1) for the same reasons.
Regarding Claims 16-18, the claims recite substantially similar limitations to Claims 2-4, respectively, and the Claims are rejected under 35 U.S.C 102(a)(1) for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5, 12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaralingam in view of Naffziger (U.S. Pub. No. 2009/0259869 A1), hereinafter Naffziger.
Regarding Claim 5, Sankaralingam teaches The processor as recited in claim 1. However, Sankaralingam does not appear to specifically teach wherein during the training, the circuitry is configured to: compare output values of the power estimation model with the power analysis results for the subset of portions; and determine the power estimation model converges based on an error satisfying convergence criteria.
On the other hand, Naffziger, which relates similarly to power estimation in ICs, does teach wherein during the training, the circuitry is configured to: compare output values of the power estimation model with the power analysis results for the subset of portions (“In block 612, the real-time power estimate generated from the sum of the weights of sampled signals is compared to the power estimate generated from the power model for each application in a predetermined application suite.”) (e.g., paragraph [0064]).
and determine the power estimation model converges based on an error satisfying convergence criteria (“If the difference between these two values is less than or equal to a predetermined minimum accuracy (conditional block 614), then design of the power estimate circuitry is complete and the chip may tape-out with the Monitor Control in the core in block 616.”) (e.g., paragraph [0064]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant's claimed invention to combine Sankaralingam with Naffziger. The claimed invention is considered to be merely combining prior art elements according to known methods to yield predictable results, see MPEP § 2143(I)(A). Sankaralingam teaches a method for partitioning a circuit, estimating power for selected partitions, and estimating power for the circuit based on the selected partitions. However, Sankaralingam does not appear to specifically teach comparing the output of the power estimation model with power analysis for select partitions. On the other hand, Naffziger, which relates similarly to power estimation in ICs, does teach comparing a power model and a power estimate from sampling to determine that a minimum accuracy has been reached. As both Sankaralingam and Naffziger disclose methods for sampling parts of an IC to estimate power usage, one of ordinary skill in the art could have combined the power estimation of Sankaralingam with the accuracy checking of Naffziger. In combination, each element merely performs the same function as it does separately. Furthermore, Sankaralingam already discloses a verification step 412, where an estimated power consumption is checked against power constraints (e.g., Sankaralingam; figure 4A; column 9, lines 10-13). Thus, one of ordinary skill in the art would have recognized that the results of the combination would have predictably verified the accuracy of the power consumption estimation. Therefore, it would have been obvious to a person of ordinary skill in the art to combine Sankaralingam with Naffziger in order to automatically verify the accuracy of the power estimation using the power correction ratio.
Regarding Claims 12 and 19, the claims recite substantially similar limitations to Claim 5, and the claims are rejected under 35 U.S.C 103 for the same reasons. It would have been obvious to combine Sankaralingam with Naffziger for the same reasons as in Claim 5, above.
Claim(s) 6, 7, 13, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaralingam in view of Cao (U.S. Pub. No. 20030097348 A1), hereinafter Cao.
Regarding Claim 6, Sankaralingam teaches The processor as recited in claim 1. However, Sankaralingam does not appear to specifically teach wherein the power estimation model comprises a neural network trained using power analysis results for the subset of portions of the integrated circuit.
On the other hand, Cao, which relates similarly as a method for modeling behavior of an electrical circuit, does teach wherein the power estimation model comprises a neural network trained using power analysis results for the subset of portions of the integrated circuit (“Shown in FIG. 1 is a method 10 for estimating power consumption of a circuit comprising steps 12, 14, 16, 18, 20, 22, 24, and 26 and an event driven model 28. Shown in FIG. 2 is a neural network (neural net) 30 useful in the method of FIG. 1.”) (e.g., paragraph [0016]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant's claimed invention to combine Sankaralingam with Cao. The claimed invention is considered to be a simple substitution of one known element for another to obtain predictable results, see MPEP § 2143(I)(B). Sankaralingam teaches a method for partitioning a circuit, estimating power for selected partitions, and estimating power for the circuit based on the selected partitions using an average power correction ratio. However, Sankaralingam does not appear to specifically teach wherein the power estimation model comprises a neural network trained on training values and validated using validation values. On the other hand, Cao does teach a method for estimating power consumption of an electrical circuit using a neural network, wherein the neural network is trained on a first set of data and verified on a second set of data. As the power correction ratio of Sankaralingam is used to estimate power consumption, which may be a simple average of the power correction of each of the selected partitions (e.g., Sankaralingam; column 8, lines 11-16), and the neural network of Cao is used to perform a similar function of estimating power (e.g., Cao; figure 1), one of ordinary skill in the art could have substituted the method of Sankaralingam using a power correction ratio with the neural network of Cao, and the result of the substitution would have predictably also predicted power consumption. Therefore, it would have been obvious to a person of ordinary skill in the art to combine Sankaralingam with Cao in order to use a more accurate power estimation model.
Regarding Claim 7, Sankaralingam teaches The processor as recited in claim 2. However, Sankaralingam does not appear to specifically teach wherein the circuitry is further configured to divide the capacitance related values corresponding to the subset of portions into training values and validation values used during creation of the power estimation model.
On the other hand, Cao, which relates similarly as a method for modeling behavior of an electrical circuit, does teach wherein the circuitry is further configured to divide the capacitance related values corresponding to the subset of portions into training values and validation values used during creation of the power estimation model (“The neural net is trained by running a first portion of the calculated inputs and their correlated power values through the neural net 30 as shown in step 20. The first portion is generally 80% of the total. The training of the neural net 30 is verified using a second portion of the calculated inputs as shown in step 22.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant's claimed invention to combine Sankaralingam with Cao for the same reasons as in Claim 6, above.
Regarding Claims 13, 14, and 20, the claims recite substantially similar limitations to Claims 6, 7, and 7, respectively, and the claims are rejected under 35 U.S.C 103 for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al. (U.S. Pub. No. 2021/0158155 A1) teaches a graph neural network for average power estimation of a netlist.
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/K.H.T./ Examiner, Art Unit 2189
/REHANA PERVEEN/ Supervisory Patent Examiner, Art Unit 2189
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