DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Koduri; US 11,887,906 B2; 11/11/2021 in view of Mallik et al.; US 2021/0035881 A1; 08/2019.
Claim 1: Koduri discloses an integrated circuit (IC) package comprising: a first IC die ( Fig. 7A #710 ) comprising one or more first conductive contacts ( Fig. 7A #129 ) and one or more second conductive contacts ( Fig. 7A contacts on top of #710 ) at a first side of the first IC die ( Fig. 7A top of #710 ); a second IC die ( Fig. 7A #720 ) coupled to the first IC die ( Fig. 7A #710 ), the second IC die comprising a second side ( Fig. 7A bottom of #720 ), a third side opposite the second side ( Fig. 7A top of #720 ), a sidewall extending between the second and third sides ( Fig. 7A sides of #720 ), and third conductive contacts ( Fig. 7A contacts between #720 and #710 ) at the second side ( Fig. 7A bottom of #720) in direct contact with respective ones of the first conductive contacts ( as shown in Fig. 7A ).
Koduri does not appear to disclose a body comprising a mold compound, the body contacting the sidewall of the second IC die and the first side of the first IC die; one or more interconnect structures extending through the body, each of the interconnect structures comprising a first end surface and a second end surface opposite the first end surface, the first end surface contacting and coupled to a respective one of the second conductive contacts; and fourth conductive contacts at the third side of the second IC die, wherein the second end surface and a surface of at least one of the fourth conductive contacts are coplanar.
However, Mallik teaches a body comprising a mold compound ( Fig. 2B a mold material #250), the body contacting the sidewall of the second IC die ( [0025] is adjacent to a sidewall of chip substrate #223 ) and the first side of the first IC die ( [0025] covers IC chips #221 ); one or more interconnect structures ( [0024] One or more pillars or other metallization features suitable for contacting RDL interconnects #235A, #235B may protrude from active region #225 ) extending through the body ( [0025] Mold material #250 is also adjacent to solder features #235A ), each of the interconnect structures ( [0021] RDL structure #210 includes one or more levels of metallization #206 embedded within dielectric materials #205 ) comprising a first end surface ( Fig. 2A top of #210 ) and a second end surface ( Fig. 2A bottom of #210 ) opposite the first end surface ( as shown in Fig. 2A) , the first end surface contacting and coupled to a respective one of the second conductive contacts ( Fig. 2B #235A ); and fourth conductive contacts ( Fig. 5 #285 ) at the third side of the second IC die ( see Fig. 5), wherein the second end surface ( Fig. 2A bottom of #210 ) and a surface of at least one of the fourth conductive contacts ( Fig. 5 #285 ) are coplanar ( Fig. 5 #285 is coplanar with contacts for #221 ).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Mallik with Koduri to implement a body comprising a mold compound, the body contacting the sidewall of the second IC die and the first side of the first IC die; one or more interconnect structures extending through the body, each of the interconnect structures comprising a first end surface and a second end surface opposite the first end surface, the first end surface contacting and coupled to a respective one of the second conductive contacts; and fourth conductive contacts at the third side of the second IC die, wherein the second end surface and a surface of at least one of the fourth conductive contacts are coplanar because this ensures reliable and consistent electrical connections for subsequent assembly and soldering processes.
Claim 2: Koduri and Mallik disclose the IC package of claim 1 (as discussed above).
Koduri teaches the one or more interconnect structures are conductive pillars ( Col 4. Lines 40 – 43 The die bonding features can comprise an anisotropic electrically conductive paste, solder bumps, copper pillars, an electrically conductive epoxy, or a metal polymer composite ).
Claim 4: Koduri and Mallik disclose the IC package of claim 1 (as discussed above).
Koduri does not appear to disclose the mold compound comprises an organic material.
However, Mallik teaches the mold compound ( Fig. 2B #250 ) comprises an organic material ( [0025] mold material #250 comprises a cured resin or polymer comprising epoxy and/or silicon).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Mallik with Koduri to implement the mold compound comprises an organic material because organic resins form the essential polymer matrix.
Claim 5: Koduri and Mallik disclose the IC package of claim 1 ( as discussed above).
Koduri does not appear to disclose the second IC die further comprises a through-silicon via connecting one of the fourth conductive contacts with a metal interconnect layer of the second IC die.
However, Mallik teaches the second IC die ( bottom side IC Fig. 2A shown in Fig. 2B ) further comprises a through-silicon via ( [0022] a plurality of IC chips is attached to the RDL interconnect features ) connecting one of the fourth conductive contacts ( Fig. 5 #285 ) with a metal interconnect layer ( Fig. 2B #210 ) of the second IC die ( bottom side IC Fig. 2A shown in Fig. 2B ).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Mallik with Koduri to implement the second IC die further comprises a through-silicon via connecting one of the fourth conductive contacts with a metal interconnect layer of the second IC die because this enables a 3D integrated circuit structure.
Claim 15: Koduri discloses a system comprising: a power supply ( Fig. 14 fan out power WCSP #1400 ); and an integrated circuit (IC) package ( Fig. 14 #125 ) coupled to the power supply ( Fig. 14 #1400 ), comprising: a first IC die ( Fig. 14 #125 ) comprising one or more first conductive contacts ( Fig. 7A #129 ) and one or more second conductive contacts ( Fig. 7A contacts on top of #710 ) at a first side of the first IC die ( Fig. 7A #710 ); a second IC die ( Fig. 7A #720 ) coupled to the first IC die ( Fig. 7A #710 ), the second IC die ( Fig. 7A #720 ) comprising a second side ( Fig. 7A bottom of #720 ), a third side opposite the second side ( Fig. 7A top of #720 ), a sidewall extending between the second and third sides ( Fig. 7A sides of #720 ), and third conductive contacts ( Fig. 7A contacts between #720 and #710 ) at the second side (Fig. 7A bottom of #720) in direct contact with respective ones of the first conductive contacts ( as shown in Fig. 7A);
Koduri does not appear to disclose a body comprising a mold compound, the body contacting the sidewall of the second IC die and the first side of the first IC die; one or more interconnect structures extending through the body, each of the interconnect structures extending from a first end surface to a second end surface opposite the first end surface, the first end surface contacting and coupled to a respective one of the second conductive contacts, wherein each of the interconnect structures is spaced apart from one of the sidewalls; and fourth conductive contacts at the third side of the second IC die.
However, Mallik teaches a body comprising a mold compound ( Fig. 2B a mold material #250), the body contacting the sidewall of the second IC die ( [0025] is adjacent to a sidewall of chip substrate #223 ) and the first side of the first IC die ( [0025] covers IC chips #221 ); one or more interconnect structures ( [0024] One or more pillars or other metallization features suitable for contacting RDL interconnects #235A, #235B may protrude from active region #225 ) extending through the body ( [0025] Mold material #250 is also adjacent to solder features #235A ), each of the interconnect structures ( [0021] RDL structure #210 includes one or more levels of metallization #206 embedded within dielectric materials #205 ) extending from a first end surface ( left side of #223 ) to a second end surface ( right side of #223 ) opposite the first end surface ( as shown in Fig. 2B ), the first end surface ( as shown in Fig. 2B ) contacting and coupled to a respective one of the second conductive contacts ( #235B ), wherein each of the interconnect structures is spaced apart from one of the sidewalls; and fourth conductive contacts ( Fig. 5 #285 ) at the third side ( Fig. 5 bottom of #205 ) of the second IC die ( Fig. 5 #201).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Mallik with Koduri to implement a body comprising a mold compound, the body contacting the sidewall of the second IC die and the first side of the first IC die; one or more interconnect structures extending through the body, each of the interconnect structures coupled to a respective one of the second conductive contacts, wherein the first conductive contacts are in a region of the first side in contact with the second IC die, and the second conductive contacts are outside of the region; and fourth conductive contacts at the third side of the second IC die because the mold compound’s primary function is to protect the delicate internal components and the configuration of the contacts is designed to enable high-speed, direct die-to-die communication inside the region and also facilitate routing signals and power outside of the region.
Claim 16: Koduri and Mallik disclose the system of claim 15 (as discussed above).
Koduri does not appear to disclose the first IC die comprises memory circuitry to store data; and the second IC die comprises logic circuity to execute instructions on the data.
However, Mallik teaches the first IC die comprises memory circuitry to store data ( [0023] IC chip #221 may be a first of any of a wireless radio circuit, microprocessor circuit, electronic memory circuit ); and the second IC die comprises logic circuity to execute instructions on the data ( [0040] processor #604 includes a package having a multi-chip unit ).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Mallik with Koduri to implement the first IC die comprises memory circuitry to store data; and the second IC die comprises logic circuity to execute instructions on the data because this approach provides significant advantages in performance, power efficiency, manufacturing optimization, and form factor.
Claim 17: Koduri and Mallik disclose the system of claim 15 ( as discussed above).
Koduri does not appear to disclose the mold compound comprises an organic material.
However, Mallik teaches the mold compound ( Fig. 2B #250 ) comprises an organic material ( [0025] mold material #250 comprises a cured resin or polymer comprising epoxy and/or silicon).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Mallik with Koduri to implement the mold compound comprises an organic material because it offers a cost-effective, durable, and highly processable encapsulation solution that protects the delicate chip components from the environment.
Claim 18: Koduri and Mallik disclose the system of claim 15 ( as discussed above).
Koduri teaches the one or more interconnect structures are comprised of copper ( Col 4. Lines 40 – 43 The die bonding features can comprise an anisotropic electrically conductive paste, solder bumps, copper pillars, an electrically conductive epoxy, or a metal polymer composite ).
Claims 8 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Koduri; US 11,887,906 B2; 11/11/2021 in view of Kim; US 2022/0399296 A1; 02/2022
Claim 8: Koduri discloses an integrated circuit (IC) package comprising: a first IC die ( Fig. 7A #710 ) comprising one or more first conductive contacts ( Fig. 7A #129 ) and one or more second conductive contacts ( Fig. 7A contacts on top of #710 ) at a first side of the first IC die ( Fig. 7A top of #710 ); a second IC die ( Fig. 7A #720 ) coupled to the first IC die ( Fig. 7A #710 ), the second IC die comprising a second side ( Fig. 7A bottom of #720 ), a third side opposite the second side ( Fig. 7A top of #720 ), sidewalls ( Fig. 7A sides of #720 ) extending between the second ( Fig. 7A bottom of #720 ) and third sides ( Fig. 7A top of #720 ), and third conductive contacts ( Fig. 7A contacts between #720 and #710 ) at the second side ( Fig. 7A bottom of #720) in direct contact with respective ones of the first conductive contacts ( as shown in Fig. 7A ).
Koduri does not appear to disclose one or more interconnect structures extending through a body, each of the interconnect structures extending from a first end surface to a second end surface opposite the first end surface, the first end surface contacting and coupled to a respective one of the second conductive contacts, wherein each of the interconnect structures is spaced apart from one of the sidewalls; and fourth conductive contacts at the third side of the second IC die, wherein the second end surface and a surface of at least one of the fourth conductive contacts are coplanar.
However, Kim teaches one or more interconnect structures extending through a body ( Fig. 5 through silicon via 230 ), each of the interconnect structures extending from a first end surface ( Fig. 5 electrode pad 205 ) to a second end surface ( Fig. 5 PSB connection pad ) opposite the first end surface ( as shown in Fig. 5 ), the first end surface contacting and coupled to a respective one of the second conductive contacts ( [0051] The first to third semiconductor chips 200-1, 200-2, and 200-3 may be electrically connected to each other through the TSV 230 ), wherein each of the interconnect structures ( Fig. 5 #230 ) is spaced apart from one of the sidewalls ( as shown in Fig. 5 ); and fourth conductive contacts at the third side of the second IC die ( as shown in Fig. 5 ), wherein the second end surface and a surface of at least one of the fourth conductive contacts are coplanar ( as shown in Fig. 5 the die are stacked vertically ).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Kim with Koduri to implement one or more interconnect structures extending through a body, each of the interconnect structures extending from a first end surface to a second end surface opposite the first end surface, the first end surface contacting and coupled to a respective one of the second conductive contacts, wherein each of the interconnect structures is spaced apart from one of the sidewalls; and fourth conductive contacts at the third side of the second IC die, wherein the second end surface and a surface of at least one of the fourth conductive contacts are coplanar because this leads to improved 3D stacking and vertical connectivity.
Claim 11: Koduri, Kim, and Mallik disclose the IC package of claim 8 ( as discussed above).
Koduri teaches the one or more interconnect structures are conductive pillars ( Col 4. Lines 40 – 43 The die bonding features can comprise an anisotropic electrically conductive paste, solder bumps, copper pillars, an electrically conductive epoxy, or a metal polymer composite ).
Claim 12: Koduri, Kim, and Mallik disclose the IC package of claim 8 ( as discussed above).
Neither Koduri nor Kim appear to disclose the second IC die further comprises a through-silicon via connecting one of the fourth conductive contacts with a metal interconnect layer of the second IC die.
However, Mallik teaches the second IC die ( bottom side IC Fig. 2A shown in Fig. 2B ) further comprises a through-silicon via ( [0022] a plurality of IC chips is attached to the RDL interconnect features ) connecting one of the fourth conductive contacts ( Fig. 5 #285 ) with a metal interconnect layer ( Fig. 2B #210 ) of the second IC die ( bottom side IC Fig. 2A shown in Fig. 2B ).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Mallik with Koduri and Kim to implement the second IC die further comprises a through-silicon via connecting one of the fourth conductive contacts with a metal interconnect layer of the second IC die because this provides a vertical, high-speed, and power-efficient electrical pathway for signals and power between the different layers of a stacked IC circuit.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Koduri; US 11,887,906 B2; 11/11/2021 in view of Kim; US 2022/0399296 A1; 02/2022 as it relates to claim 8 and further in view of Mallik et al.; US 2021/0035881 A1; 08/2019.
Claim 9: Koduri and Kim disclose the IC package of claim 8 ( as discussed above).
Neither Koduri nor Kim appear to disclose the body comprises a mold compound contacting the sidewall of the second IC die and the first side of the first IC die.
However, Mallik teaches the body comprises a mold compound ( Fig. 2B a mold material #250) contacting the sidewall of the second IC die ( [0025] is adjacent to a sidewall of chip substrate #223 ) and the first side of the first IC die ( [0025] covers IC chips #221 ).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Mallik with Koduri and Kim to implement the body comprises a mold compound contacting the sidewall of the second IC die and the first side of the first IC die because it provides protection from environmental factors and improves mechanical integrity.
Claim 10: Koduri, Kim, and Mallik disclose the IC package of claim 9 ( as discussed above).
Neither Koduri nor Kim appear to disclose the mold compound comprises an organic material.
However, Mallik teaches the mold compound ( Fig. 2B #250 ) comprises an organic material ( [0025] mold material #250 comprises a cured resin or polymer comprising epoxy and/or silicon).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Mallik with Koduri and Kim to implement the mold compound comprises an organic material because of the exceptional balance of performance, low cost, and manufacturing advantages.
Claims 6, 7, 13, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al.; US 2021/0035881 A1; 08/2019 in view Koduri; US 11,887,906 B2; 11/11/2021 as it relates to claim 1 and further in view of Chen et al.; US 2018/0005940 A1; 06/2016.
Claim 6: Koduri and Mallik disclose the IC package of claim 1 ( as discussed above).
Neither Koduri nor Mallik appear to disclose a thickness of the second IC die is greater than 40 microns.
However, Chen teaches a thickness of the second IC die is greater than 40 microns (par. [0040] a possible thickness of the substrate (102’) of the second die (102+102A) (see fig. 3 of up to 100 microns).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Chen with Koduri and Mallik to implement the second IC die with a thickness greater than 40 microns because it enables better heat dissipation.
Claim 7: Koduri and Mallik disclose the IC package of claim 1 ( as discussed above).
Neither Koduri nor Mallik appear to disclose a distance between the first side of the first IC die and the second end surface is greater than 90 microns.
However, Chen teaches a distance between the first side of the first IC die and the second end surface is greater than 90 microns ( [0025] The semiconductor structure 102 and the bonding dielectric 102A together has a total thickness of H’. Through dielectric vias (#105) possesses a height H, measured from one end of the through dielectric vias (#105) connecting with the metallization (#103) to the bonding metallization (#101A). The height H is greater than the thickness H’. par. [0040] a possible thickness of the substrate (102’) of the second die (102+102A) (see fig. 3 of up to 100 microns.)
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Chen with Koduri and Mallik to implement a distance between the first side of the first IC die and the second end surface greater than 90 microns because this enhances reliability and enables fine-pitch designs.
Claim 13: Koduri and Mallik disclose the IC package of claim 8 ( as discussed above).
Neither Koduri nor Mallik appear to disclose a thickness of the second IC die is greater than 40 microns.
However, Chen teaches a thickness of the second IC die is greater than 40 microns (par. [0040] a possible thickness of the substrate (102’) of the second die (102+102A) (see fig. 3 of up to 100 microns).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Chen with Koduri and Mallik to implement a thickness of the second IC die is greater than 40 microns because it enables better heat dissipation.
Claim 14: Koduri and Mallik disclose the IC package of claim 8 ( as discussed above).
Koduri discloses each of the one or more interconnect structures comprises a first end surface ( Fig. 7A surface above #129 ) contacting the second conductive contact ( Fig. 7A contacts between #710 and #720 ) with which the interconnect structure is coupled and a second end surface ( Fig. 7A top of #710 ) opposite the first end surface ( Fig. 7A bottom of #710 ).
Neither Koduri nor Mallik appear to disclose a distance between the first side of the first IC die and the second end surface is greater than 90 microns.
However, Chen teaches a distance between the first side of the first IC die and the second end surface is greater than 90 microns ( [0025] The semiconductor structure 102 and the bonding dielectric 102A together has a total thickness of H’. Through dielectric vias (#105) possesses a height H, measured from one end of the through dielectric vias (#105) connecting with the metallization (#103) to the bonding metallization (#101A). The height H is greater than the thickness H’. par. [0040] a possible thickness of the substrate (102’) of the second die (102+102A) (see fig. 3 of up to 100 microns.)
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Chen with Koduri and Mallik to implement a distance between the first side of the first IC die and the second end surface greater than 90 microns because this enhances reliability and enables fine-pitch designs.
Claim 20: Koduri and Mallik disclose the system of claim 15 ( as discussed above).
Neither Koduri nor Mallik appear to disclose a thickness of the second IC die is greater than 40 microns.
However, Chen teaches a thickness of the second IC die is greater than 40 microns (par. [0040] a possible thickness of the substrate (102’) of the second die (102+102A) (see fig. 3 of up to 100 microns).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Chen et al. with Mallik to create the second IC die with a thickness greater than 40 microns to enable better heat dissipation.
Response to Arguments
Applicant's request for reconsideration of the finality of the rejection of the last Office action is persuasive and, therefore, the finality of that action is withdrawn.
Applicant's arguments, see pages 2-3 of remarks filed 07/08/26 have been fully considered but they are not persuasive. Koduri teaches in Col. 6 lines 47 – 52 FIGS. 7A-B shows yet some other alternate arrangements shown as three die-wrapped packaged devices shown in FIG. 7A as 710, 720, 730 stacked on one another, with die-wrapped packaged device 730 being on the top, die-wrapped packaged device 720 being in the middle, and die-wrapped packaged device 710 being on the bottom. This approach is common in advanced packaging like chip-scale packages (CSP), chip-on-board (COB), and embedded die designs.
Applicant's arguments, see pages 3-4 of remarks filed 07/08/26 have been fully considered but they are not persuasive. Koduri teaches third conductive contacts ( Fig. 7A contacts between #720 and #710 ) at the second side ( Fig. 7A bottom of #720 ) in direct contact with the respective ones of the first conductive contacts ( as shown in Fig. 7A ). Applicant is focusing on #180 but the entire die-wrapped package is the IC die as described above and it is shown in Fig. 7A that the dies are in direct contact.
Applicant’s arguments, see pages 4-5 of remarks, filed 07/08/26, with respect to the rejection of claim 8 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
