DETAILED ACTION
Response to Amendment
Applicant’s amendment, filed 02/11/26, for application number 17/563,788 has been received and entered into record. Claims 2 and 9 have been amended. Therefore, Claims 1-20 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4-6, 8, 9, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Choquette et al., US 7,337,339 B1, in view of Fossati et al., US 2020/0089296 A1..
Regarding Claim 1, Choquette discloses an apparatus [multi-processor chip of Fig. 2] comprising:
a plurality of functional blocks configured to receive a global alarm signal indicating whether power consumption of the apparatus exceeds a global limit of the apparatus [when the global power estimate exceeds the global power thresholds from global power table 32, then power must be reduced. Local power targets are read from global power table 32 and are sent to local power tables 38, 38′, 38″. Local power managers 36, 36′, 36″ are also activated by central power manager 30; step 112 of Fig. 6A checks if estimated moving average (EMA) is over the global threshold, and if yes, proceeds to step B of Fig. 6B to send local power targets to local blocks (i.e. global alarm signal to reduce power), col. 3, ll. 42-47]; and
a power management controller[central power manager 30] comprising circuitry configured to:
convey first power limits to each of the plurality of functional blocks [when processor core 10 generates an event, the event is looked up in local power table 38. Local power table 38 stores power estimates for each kind of event; Local power targets are read from global power table 32 and are sent to local power tables 38,38', 38"; that is, local blocks have local power tables already provided by the global power manager prior to any events occurring, col. 3, ll. 3-5, 44-47]; and
convey second power limits to a given functional block of the plurality of functional blocks, responsive to detecting assertion of the global alarm signal [when the EMA is over the global power threshold at step 112, then global power manager sends local power targets (limits) to the local blocks at step 116, Fig. 6A, 6B].
However, while Choquette discloses reducing power consumption responsive to detecting the assertion of the global alarm signal irrespective of whether or not power consumption of the given functional block exceeds its local power limit of the first power limits [throttling local blocks to new targets based on exceeding global threshold, steps 112, 116, without consideration of the local power limits, Fig. 6A, 6B], Choquette does not explicitly teach wherein the given functional block is configured to reduce its power consumption prior to receiving one of the second power limits.
In the analogous art of power management, Fossati teaches wherein the given functional block is configured to reduce its power consumption prior to receiving one of the second power limits [power allocator may dictate the power consumption to be a certain threshold value lower than the power allocated to the display device before adjusting set power allocations (i.e. lowering the power before the power allocation will be adjusted), par 41, ll. 1-4].
It would have been obvious to one of ordinary skill in the art, having the teachings of Choquette and Fossati before him before the effective filing date of the claimed invention, to incorporate the power limit update as taught by Fossati into the apparatus as disclosed by Choquette, to avoid frequent power adjustments [Fossati, par 41, ll. 5-9].
Regarding Claim 2, Choquette and Fossati disclose the apparatus as recited in Claim 1. Choquette further discloses wherein a plurality of the functional blocks concurrently initiate reduction of power consumption in response to assertion of the global alarm signal [monitoring of local blocks and the associated reduction of power are performed in response to the global power table being exceeded (i.e. the monitoring and associated reductions occur in parallel, or concurrently), Fig. 6B; col. 6, ll. 55-67, col. 7, ll. 1-10].
Regarding Claim 4, Choquette and Fossati disclose the apparatus as recited in Claim 1. Choquette further discloses wherein in response to the global alarm signal indicating power consumption of the apparatus has exceeded the global limit [exceeding global limit at step 112, Fig. 6A], the power management controller is configured to: send a plurality of requests to retrieve power consumption values from one or more of the plurality of functional blocks [after throttling at local power targets, Fig. 6B provides local power throttling which ultimately returns to continued monitoring at a global level].
Regarding Claim 5, Choquette and Fossati disclose the apparatus as recited in Claim 1. Choquette further discloses wherein, while the global alarm signal continues to indicate power consumption of the apparatus has exceeded a global limit of the apparatus, one or more of the plurality of functional blocks are configured to further reduce power consumption to less than a corresponding one of the second power limits, in response to a duration of a given time interval has elapsed while the global alarm signal is asserted [Choquette Fig. 4 shows different recording decay periods 52 and 54 operating at different time intervals (1 ms and 1 second). See Col. 5, ll. 5-24, stating that different thresholds operate at different time intervals relative to their severity].
Regarding Claim 6, Choquette and Fossati disclose the apparatus as recited in Claim 4. Choquette discloses sending updated limits to the plurality of functional blocks [Choquette Fig. 3 Step 136 sends the local power targets that are stored to the respective groups of functional blocks], and Fossati further teaches generate updated limits of the second power limits based on the power consumption values received from the plurality of functional blocks [power allocator may dictate the power consumption to be a certain threshold value lower than the power allocated to the display device before adjusting set power allocations, par 41, ll. 1-4].
Regarding Claim 8, Choquette discloses a method [using the chip of Fig. 2]. The remainder of Claim 8 recites limitations similar those presented in Claim 1, and is rejected accordingly.
Regarding Claim 9 and 11-13, Choquette and Fossati disclose the method as recited in Claim 8. Claims 9 and 11-13 recite limitations similar to those presented in Claims 2 and 4-6, respectively, and are rejected accordingly.
Claims 3, 7, 10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Choquette and Fossati, and further in view of Kalyanam et al., US 2021/0096635 A1.
Regarding Claim 3, Choquette and Fossati disclose the apparatus as recited in Claim 1. However, the combination of references does not explicitly teach wherein at least the given functional block is configured to reduce power consumption to a corresponding one of the first power limits in response to: a monitored power consumption exceeds a corresponding one of the first power limits; and the global alarm signal indicating power consumption of the apparatus does not exceed the a global limit of the apparatus.
In the analogous art of power control, Kalyanam teaches wherein at least the given functional block is configured to reduce power consumption to a corresponding one of the first power limits in response to: a monitored power consumption exceeds a corresponding one of the first power limits; and the global alarm signal indicating power consumption of the apparatus does not exceed the a global limit of the apparatus [the overage signal having a value that ranges based on how much current there is above a threshold. After receiving the overage signal power is reduced across the system. Once power is reduced and the current levels are no longer exceeded, the overage value and signal will become cancelled/eliminated (negated), par 35].
It would have been obvious to one of ordinary skill in the art, having the teachings of Choquette, Fossati, and Kalyanam before him before the effective filing date of the claimed invention, to incorporate the power monitoring as taught by Kalyanam into the apparatus as disclosed by Choquette and Fossati to obtain reliable power measurements of functional block power supplies.
Regarding Claim 7, Choquette and Fossati disclose the apparatus as recited in Claim 6. However, the combination of references does not explicitly teach wherein the power management controller is further configured to generate updated limits of the second power limits based on one or more of a monitored work load and a quality of service (QoS) parameter.
In the analogous art of power control, Kalyanam teaches wherein the power management controller is further configured to generate updated limits of the second power limits based on one or more of a monitored work load and a quality of service (QoS) parameter [excess current being drawn results in quality of service issues; new target performance and power consumptions are used to mitigate and quality of service issues, par 28].
It would have been obvious to one of ordinary skill in the art, having the teachings of Choquette, Fossati, and Kalyanam before him before the effective filing date of the claimed invention, to incorporate the setting of power limits based on monitored quality of service as taught by Kalyanam into the apparatus as disclosed by Choquette and Fossati, to ensure a reliable standard of operation.
Regarding Claims 10 and 14, Choquette and Fossati disclose the method as recited in Claim 8. Claims 10 and 14 recite limitations similar to those presented in Claims 3 and 7, respectively, and are rejected accordingly.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choquette, Fossati, and Kalyanam, and further in view of Varma et al., US 2013/0332753 A1.
Regarding Claim 15, Choquette discloses a computing system [the chip of Fig. 2]. The remainder of Claim 15 recite limitations similar to those presented in Claim 1, and is rejected by the combination of Choquette and Fossati accordingly, save for a first voltage regulator configured to provide a first power supply voltage level on a first power rail; a second voltage regulator configured to provide a second power supply voltage level on a second power rail; and an integrated circuit configured to utilize each of the first power rail and the second power rail.
In the analogous art of power control, Kalyanam teaches a first voltage regulator configured to provide a first power supply voltage level on a first power rail [PMIC 102 connected to voltage supply rail; the PMIC provides various power levels to multiple separate voltage supply rails, Fig. 1A; par 25]; a second power supply voltage level on a second power rail [exemplary aspects including multiple voltage supply rails providing different voltage levels, par 25]; and an integrated circuit configured to utilize each of the first power rail and the second power rail [rails as part of IC of Fig. 1].
It would have been obvious to one of ordinary skill in the art, having the teachings of Choquette, Fossati, and Kalyanam before him before the effective filing date of the claimed invention, to incorporate the monitored power rails as taught by Kalyanam into the system as disclosed by Choquette and Fossati to ensure power delivery to various functional blocks of the system.
However, the combination of Choquette, Fossati, and Kalyanam does not explicitly teach a second voltage regulator configured to provide a second power supply voltage level.
In the analogous art of dynamic power limit sharing, Varma teaches a second voltage regulator configured to provide a second power supply voltage level [digital voltage regulators associated with separate modules (this would include a second voltage regulator providing a second power supply voltage level for separate components), par 27].
It would have been obvious to one of ordinary skill in the art, having the teachings of Choquette, Fossati, Kalyanam, and Varma and before him before the effective filing date of the claimed invention, to incorporate the additional voltage regulators as taught by Varma, into the system as disclosed by Choquette, Fossati, and Kalyanam to improve performance of the system by allowing for combined power budgets and limits [Varma, par 3, 4].
Regarding Claims 16-20, Choquette, Fossati, Kalyanam, and Varma disclose the computer system as recited in Claim 15. Claims 16-20 recite limitations similar to those presented in Claims 2-6, respectively, and are rejected accordingly.
Response to Arguments
Applicant’s arguments as to the newly-amended limitations filed 02/11/26 have been considered but are moot due to the new rejection based on the references previously presented.
Applicant's arguments regarding the remaining limitations have been fully considered but they are not persuasive.
Applicant argues Choquette does not describe or suggest functional blocks initiating power reduction merely upon detection of a global alarm signal, does not disclose power reduction occurring prior to receipt of updated limits, and does not disclose power reduction that is independent of local-limit exceedance.
Examiner notes the rejection as previously presented (and repeated above), provides a mapping as to where Choquette discloses power reduction upon detection of a global alarm, with the power reduction independent of local-limit exceedance (reducing power consumption responsive to detecting the assertion of the global alarm signal irrespective of whether or not power consumption of the given functional block exceeds its local power limit of the first power limits [throttling local blocks to new targets based on exceeding global threshold, steps 112, 116, without consideration of the local power limits, Fig. 6A, 6B]).
The rejection then relied upon Fossati to teach power reduction prior to receipt of updated limits, as illustrated previously and repeated above.
Applicant acknowledges the combination of references, but argues Choquette and Fossati do not teach or suggest the timing and trigger relationship recited in Claim 1, arguing “the cited art does not disclose or suggest a sequence in which functional blocks autonomously initiate power reduction upon assertion of a global alarm signal, before updated limits are received and without first determining whether local limits have been exceeded.” However, in making the argument, Applicant appears to be attacking the references individually, as the rejection has indicated each portion of the limitations as addressed by the respective reference.
Thus, it is unclear why Applicant nonetheless argues the limitation is not taught by the combination of references. Applicant may wish to further amend the claims to better reflect any features provided in the Specification but not fully expressed in the claim limitations regarding sequential or timing features of the invention to better distinguish the claims from the rejection of record.
No additional arguments were made as to the remaining limitations, and as such, the rejection is maintained.
Conclusion
Applicant's amendments as to Claims 2 and 9 necessitated the new grounds of rejection presented in this Office action. The rejection is maintained as to the remaining claims. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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/Paul Yen/Primary Examiner, Art Unit 2175