DETAILED ACTION
Response to Amendment
Applicant’s amendment, filed 05/29/26, for application number 17/563,788 has been received and entered into record. Claims 1-15, 17, 19, and 20 have been amended. Therefore, Claims 1-20 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 6, 8, 9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Dai et al, US 2020/0089308 A1, in view of Gangopadhyay et al., US 2020/0334425 A1.
Regarding Claim 1, Dai discloses an apparatus [system on chip (SoC) 1710, Fig. 17] comprising:
a plurality of functional blocks, each comprising circuitry configured to process tasks using respective assigned power limits; a power management controller comprising circuitry configured to assign the respective assigned power limits to the plurality of functional blocks [IP circuit 0; IP Circuit 1; IP Circuit 2 with logic circuits and local controllers; PCU 1730 can assign local current budgets for IP circuits at step 1930, Fig. 19; par 124, 138]; and
an alarm signal path configured to route a global alarm signal to both the power management controller and the plurality of functional blocks, wherein the global alarm signal, when asserted, indicates that current or power consumption associated with the apparatus has exceeded a global current or power limit [when total current consumption exceeds budget at step 1970, then global violation detection signal is sent to IP circuits at step 1980 (PCU would be aware of global violation as well as it is sending the violation signal to the IP circuits)];
wherein, responsive to assertion of the global alarm signal:
given functional block is configured to, before receiving an updated power limit from the power management controller and irrespective of whether power consumption of the given functional block exceeds a power limit currently assigned to the given functional block, limit peak power consumption of the given functional block [in the absence of a global violation signal no local throttling may occur, i.e. local throttling based on global violations at step 1980]; and
the power management controller is configured to assign updated power limits to one or more of the plurality of functional blocks [at step 1950, PCU may receive current requests from IP circuits; in response to the requests, PCU may determine whether to grant the requests or grand authorization for a lower level of operation (i.e. assign power limits), Fig. 19; par 140, 141].
However, Dai does not explicitly teach limit peak power consumption of the given functional block to no greater than a given level that is less than the power limit currently assigned to the given functional block.
Gangopadhyay teaches limiting peak power consumption of the given functional block to no greater than a given level that is less than the power limit currently assigned to the given functional block [power scaling by having power consumption reduce to fraction of maximum power consumption, par 82].
It would have been obvious to one of ordinary skill in the art, having the teachings of Dai and Gangopadhyay before him before the effective filing date of the claimed invention, to incorporate the power scaling as taught by Gangopadhyay into the apparatus as disclosed by Dai, to perform efficient operation by using only the necessary amount of system components [Gangopadhyay, par 4].
Regarding Claim 2, Dai and Gangopadhyay disclose the apparatus as recited in Claim 1. Dai further discloses wherein the global alarm signal is a single global alarm signal indicative of whether one or more of a plurality of groups of the functional blocks has exceeded a respective current or power limit [when total current consumption exceeds budget at step 1970, then global violation detection signal is sent to IP circuits at step 1980 (PCU would be aware of global violation as well as it is sending the violation signal to the IP circuits), Fig. 19].
Regarding Claim 6, Dai and Gangopadhyay disclose the apparatus as recited in Claim 1. Dai further discloses reducing the power limit while the global alarm signal remains asserted [in the absence of a global violation signal no local throttling may occur, i.e. local throttling based on global violations at step 1980, Fig. 19], and Gangopadhyay further teaches wherein the given level is based on a positive, non-zero fraction less than one of the power limit currently assigned to the given functional block [power scaling by having power consumption reduce to fraction of maximum power consumption, i.e. 44% of maximum power consumption, par 82].
Regarding Claim 8, Dai discloses a method [using the apparatus of Fig. 7]. Claim 8 recites limitations similar to those of Claim 1, and is rejected accordingly.
Regarding Claims 9 and 13, Dai and Gangopadhyay disclose the apparatus as recited in Claim 8. Claims 9 and 13 recite limitations similar to those of Claims 2 and 6, and are rejected accordingly.
Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Dai and Gangopadhyay, and further in view of Chu et al., US 2018/0288344 A1.
Regarding Claim 3, Dai and Gangopadhyay disclose the apparatus as recited in Claim 2. However, while Dai discloses the functional blocks [IP circuits 0, 1, 2, Fig. 17], the combination of references does not explicitly teach wherein a first group of the plurality of groups of functional blocks shares a first power rail, and wherein a second group of the plurality of groups of functional blocks shares a second power rail different from the first power rail.
Chu teaches wherein a first group of the plurality of groups of functional blocks shares a first power rail, and wherein a second group of the plurality of groups of functional blocks shares a second power rail different from the first power rail [different groups of components on the SoC can be on different power rails; SoC power rail A 403 and SoC power rail B 404, with different components of the SoC 402 on their respective power rails, Fig. 4].
It would have been obvious to one of ordinary skill in the art, having the teachings of Dai, Gangopadhyay, and Chu before him before the effective filing date of the claimed invention, to incorporate the separate power rails as taught by Chu into the apparatus as disclosed by Dai and Gangopadhyay, to allow for different components to operate at different voltages and avoid wasted resources [Chu, par 25].
Regarding Claim 10, Dai and Gangopadhyay disclose the method as recited in Claim 8. Claim 10 repeats the same limitations as recited in Claim 3, and is rejected accordingly.
Claims 4, 5, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Dai and Gangopadhyay, and further in view of Wiencke et al., US 2018/0136706 A1.
Regarding Claim 4, Dai and Gangopadhyay disclose the apparatus as recited in Claim 1. However, the combination of references does not explicitly teach requesting power-consumption information from one or more of the plurality of functional blocks before assigning the updated power limits.
Wiencke teaches requesting power-consumption information from one or more of the plurality of functional blocks before assigning the updated power limits [decision circuitry may… adjust the operational frequency of specific components, to limit peak power consumption or to limit average power consumption based on an estimated measure of energy consumption by the component, par 91].
It would have been obvious to one of ordinary skill in the art, having the teachings of Dai, Gangopadhyay, and Wiencke before him before the effective filing date of the claimed invention, to incorporate requesting component information to limit power consumption as taught by Wiencke into the apparatus as disclosed by Dai and Gangopadhyay, to allow for dynamic power consumption management [Wiencke, par 91].
Regarding Claim 5, Dai, Gangopadhyay, and Wiencke disclose the apparatus as recited in Claim 4. Wiencke further teaches wherein the power management controller is configured to assign the updated power limits based on the requested power-consumption information and a quality of service parameter [decision circuitry may enable/disable specific components or peripherals, or adjust the operational frequency of specific components, to limit peak power consumption or to limit average power consumption based on an estimated measure of energy consumption by the component (enabling/disable components or peripherals being a QoS parameter), par 91].
Regarding Claims 11 and 12, Dai and Gangopadhyay disclose the method as recited in Claim 8. Claims 11 and 12 repeat the limitations recited in Claims 4 and 5, and are rejected accordingly.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Dai and Gangopadhyay, and further in view of Choquette et al., US 7,337,339 B1.
Regarding Claim 7, Dai and Gangopadhyay disclose the apparatus as recited in Claim 1. However, the combination of references does not explicitly teach wherein the given functional block is configured to use one of the updated power limits after the global alarm signal becomes negated.
Choquette teaches wherein the given functional block is configured to use one of the updated power limits after the global alarm signal becomes negated [step 136 sends local power targets that are stored to the respective groups of functional blocks (which is performed after “over threshold” alarm signal is sent at step 135 (signals being negated upon task of indicating being complete), Fig. 3].
It would have been obvious to one of ordinary skill in the art, having the teachings of Dai, Gangopadhyay, and Choquette before him before the effective filing date of the claimed invention, to incorporate updating the local power limits as taught by Choquette into the apparatus as disclosed by Dai and Gangopadhyay, to allow for power management of multiple components which can operate independently of one another [Choquette, col. 1, ll. 62-67].
Regarding Claim 14, Dai and Gangopadhyay disclose the method as recited in Claim 8. Claim 14 repeats the same limitations as recited in Claim 7, and is rejected accordingly.
Claims 15-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Dai and Gangopadhyay, and further in view of Varma et al., US 2013/0332753 A1.
Regarding Claim 15, Dai discloses a computing system [system on chip (SoC) 1710, Fig. 17]. The remainder of Claim 15 recites limitations similar to those of Claim 1, and is rejected by the combination of Dai and Gangopadhyay, and is rejected accordingly, save for a first voltage regulator configured to provide a first power supply voltage level on a first power rail; a second voltage regulator configured to provide a second power supply voltage level on a second power rail; and an integrated circuit configured to utilize each of the first power rail and the second power rail.
Varma teaches a first voltage regulator configured to provide a first power supply voltage level on a first power rail; a second voltage regulator configured to provide a second power supply voltage level on a second power rail; and an integrated circuit configured to utilize each of the first power rail and the second power rail [the platform may access readings taken from the associated digital voltage regulators for the module (i.e. multiple regulators with their respective modules); the voltage regulators being accessed by the platform, which includes a computing device, par 27].
It would have been obvious to one of ordinary skill in the art, having the teachings of Dai, Gangopadhyay, and Varma before him before the effective filing date of the claimed invention, to incorporate the additional voltage regulators as taught by Varma into the apparatus as disclosed by Dai and Gangopadhyay, improve performance of the system by allowing for combined power budgets and limits [Varma, par 3, 4].
Regarding Claim 16, Dai, Gangopadhyay, and Varma disclose the computing system as recited in Claim 15. Varma further teaches wherein a first group of functional blocks of the plurality of functional blocks share a first power rail, and a second group of functional blocks of the plurality of functional blocks share a second power rail [the platform may access readings taken from the associated digital voltage regulators for the module (i.e. multiple regulators with their respective modules); the voltage regulators being accessed by the platform, which includes a computing device, par 27], and wherein power consumption of the integrated circuit exceeding the global limit is based on one or more of: a power limit of the first power rail has been exceeded; and a power limit of the second power rail has been exceeded [the processor-based firmware has access to the power measurements of the modules in the platform. This allows the average power consumption of each module to be determined and checked against the set threshold (i.e. determining if the respective rail limits have been exceeded), par 27].
Regarding Claims 17 and 20, Dai, Gangopadhyay, and Varma disclose the computing system as recited in Claim 15. Claims 17 and 20 repeat the same limitations as recited in Claims 2 and 6, respectively, and are rejected accordingly.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Dai and Gangopadhyay, and Varma, and further in view of Wiencke.
Regarding Claims 18 and 19, Dai and Gangopadhyay, and Varma, disclose the computing system as recited in Claim 15. Claims 18 and 19 repeat the same limitations as recited in Claims 4 and 5, and are rejected accordingly.
Response to Arguments
Applicant’s arguments filed 05/29/26 have been considered but are moot due to the new rejection based on the references cited above, as well as the newly cited portions of the references previously presented.
Conclusion
Applicant is reminded that in amending a response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Paul Yen/Primary Examiner, Art Unit 2175
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