Prosecution Insights
Last updated: April 19, 2026
Application No. 17/564,725

AUTOMATED REDISTRIBUTION LAYER POWER CONNECTIONS

Final Rejection §101§103
Filed
Dec 29, 2021
Examiner
LIN, ARIC
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Ati Technologies Ulc
OA Round
4 (Final)
60%
Grant Probability
Moderate
5-6
OA Rounds
3y 3m
To Grant
72%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allow Rate
312 granted / 521 resolved
-8.1% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
51 currently pending
Career history
572
Total Applications
across all art units

Statute-Specific Performance

§101
18.4%
-21.6% vs TC avg
§103
43.9%
+3.9% vs TC avg
§102
12.8%
-27.2% vs TC avg
§112
21.5%
-18.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 521 resolved cases

Office Action

§101 §103
DETAILED ACTION This office action addresses Applicant’s response filed on 3 November 2025. Claims 1-20 are pending. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract mental processes without significantly more. The claim(s) recite(s) accessing a netlist and attributes including boundary regions for placement of signal types in metal layers of an interposer between integrated circuits and a package substrate, and generating, responsive to analysis of design-rule data, first and second placement data ‘indicative of’ placement of the signal types in metal layers based on the netlist and attributes, and generating updated mask layout data with the first and second placement data, which could be performed by a designer entirely in the mind or with pen and paper. The claimed invention is directed to an abstract design process that places/routes signals in a circuit design according to regions that constrain routing direction and density. A circuit designer thinking about or receiving a design specification with signal direction and density characteristics in specified regions (as illustrated in Fig. 8), and then thinking about, writing, drawing, etc. any information ‘indicative of’ where to place signals according to the specification, satisfies the claim. Although the claims have been amended to recite that the signals are placed in metal layers of an interposer between one or more integrated circuits and a package substrate, these limitations merely describe the product that is being designed by the process, which does not change the abstract nature of the claimed steps. The claimed invention itself remains an abstract design process that could be performed by a human designer and produces merely data/information about the interposer, rather than a fabrication process that actually manufactures or produces the interposer. This judicial exception is not integrated into a practical application because the only additional elements recited are a processor and data stored on a storage device, which are merely generic computer elements used as tools for implementing the otherwise abstract mental process. Generic computer implementation of an abstract idea does not qualify as integrating the abstract idea into a patentable practical application. Similarly, the claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because generic computer implementation of an abstract idea does not qualify as ‘significantly more’ than the abstract idea itself. Claim 2 recites two boundary regions; claim 3 recites that the data is indicative of placement of the signal type in the overlap region and first/second regions adjacent to the overlap region, when it is determined that the first/second regions overlap; claim 4 recites that one boundary region has higher priority; claim 7 recites that the metal layers are redistribution layers. Claims 2-4 and 7 thus recite merely characteristics of the data received or generated by the process, and do not change the abstract nature of the process itself. Claim 5 recites generating a report that indicates whether placement includes a minimum junction area, which is another abstract mental step similar to the data generation of parent claim 1. Claim 6 recites that generating placement is in an order specified by the attributes, which does not change the abstract nature of the placement generation itself. Claims 8-14 recite the methods performed by the processor of claims 1-7 and are rejected under the same reasoning. Claims 15-20 similarly recite a computer system that performs the same method performed by the processor of claims 1-5 and 7, with an additional step of receiving the netlist and basing the data generation also on the netlist in addition to the attributes, which are also abstract mental steps of receiving additional information and using the additional information in the data generation of claim 1. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 8-10, and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2020/0020644) in view of Hetzel (US 2005/0273748), Ou (US 2023/0014110), and Teig (US 2002/0147958). Regarding claim 1, Lee discloses a processor comprising circuitry configured to (Fig. 12; ¶¶74-75): access mask layout data stored on a storage device, wherein the mask layout data comprises a netlist and a plurality of attributes (¶66) for placement of signals in metal layers of an interposer between one or more integrated circuits and a package substrate (Fig. 1; ¶16), generate first placement data indicative of a placement of a plurality of signal types in a plurality of levels of the metal layers of the interposer, based at least in part on the netlist and the plurality of attributes, and generate updated mask layout data with the first placement data (¶¶66, 71, 72). Lee does not appear to explicitly disclose accessing a plurality of attributes stored on the storage device that include an identification of boundary regions for placement of signals in metal layers, wherein at least two boundary regions specify confined placement of a given signal type in a given level of a plurality of levels of metal layers of the interposer using a same orientation and two different metal densities. Hetzel discloses these limitations (Fig. 17; ¶¶56, 71, 82). Although Hetzel clearly discloses regions having a same orientation and two different metal densities by contrasting between embodiments where each region has its own density and embodiments where a density is set for each orientation, if Hetzel is found to be unclear regarding regions having a same orientation and two different metal densities, Ou also explicitly discloses the same (Fig. 4). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Lee, Hetzel, and Ou, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of increasing routing flexibility by allowing designers to route signals in different directions and using different track pitches as desired. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Lee discloses routing metal layers of an interposer. Hetzel discloses that routing metal layers should be done according to regions that define different allowable routing orientations and densities; Ou similarly discloses that routing should be done according to regions that define different allowable densities even when the orientations are the same. The teachings of Hetzel and Ou are directly applicable to Lee in the same way, so that Lee would similarly route interposers using regions that define allowable routing orientations and densities, in order to increase routing flexibility by allowing designers to route signals using different orientations, densities, and combinations thereof. Lee does not appear to explicitly disclose responsive to automated analysis of design-rule data associated with the mask layout data, responsive to a determination that an overlap region exists between the two boundary regions, generate second placement data indicative of a placement of the given signal type using a first metal density of the two different metal densities in the overlap region, so that the updated mask layout data is generated with the second placement data. Hetzel discloses these limitations (Fig. 59C-D; ¶¶3, 82); Teig also discloses the same, where the two boundary regions have the same orientation (Fig. 72). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Lee, Hetzel, Ou, and Teig, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of increasing routing flexibility using defined routing regions by allowing routing across region boundaries. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Lee discloses routing metal layers of an interposer. Hetzel discloses that routing metal layers should be done according to regions that define different allowable routing orientations and densities; Ou similarly discloses that routing should be done according to regions that define different allowable densities even when the orientations are the same; Teig further teaches that routing regions having the same orientations can overlap. Hetzel further teaches that when regions overlap, routing density of one region can also be used in the overlap region. The teachings of Hetzel, Ou, and Teig are directly applicable to Lee in the same way, so that Lee would similarly route interposers using regions that define allowable routing orientations and densities, while further increasing routing flexibility by also allowing routing across overlapping region boundaries. Regarding claim 2, Lee does not appear to explicitly disclose that the at least two boundary regions comprise a first boundary region using a first orientation and the first metal density; and a second boundary region using the first orientation and a second metal density different from the first metal density. As discussed above with regard to claim 1, Hetzel (Fig. 17; ¶¶82) and Ou (Fig. 4) disclose these limitations. Motivation to combine remains consistent with claim 1. Regarding claim 3, Lee does not appear to explicitly disclose that responsive to the overlap region exists between the first boundary region and the second boundary region, the circuitry is further configured to generate data indicative of a placement of the given signal type using the first metal density in a region adjacent to the overlap region in the first boundary region and in a region adjacent to the overlap region in the second boundary region. Hetzel discloses these limitations (Fig. 59A and C; routing density from, e.g., upper LPDR, used in both LPDRs adjacent to boundary overlap). Claims 8-10 are directed to the methods performed by the processor of claims 1-3, recite substantially similar limitations, and are rejected under the same reasoning. Claims 15-17 are directed to computing systems comprising a processing circuit, a memory circuit coupled to the processing circuit configured to store a netlist, wherein the circuitry of the processing circuit is configured to perform the methods of claims 1-3, recite substantially similar limitations, and are rejected under the same reasoning. As discussed above with regard to claim 1, Lee discloses computing systems comprising a processing circuit, a memory circuit coupled to the processing circuit configured to store a netlist, wherein the circuitry of the processing circuit is configured to perform the claimed methods (Fig. 12; ¶¶66, 74, 75). Claim(s) 4, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hetzel, Ou, Teig, and Bales (US 2016/0267204). Regarding claim 4, Lee does not appear to explicitly disclose that the circuitry is further configured to determine the first boundary region has higher priority than the second boundary region. Bales discloses these limitations (Abstract, ¶7). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Lee, Hetzel, Ou, Teig, and Bales, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of allowing designers to prioritize some design constraints over others when routing an interposer. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Lee discloses routing an interposer. As discussed above with regard to claim 1, Hetzel, Ou, and Teig teach regions with defined routing directions and densities. Bales teaches that the regions should have relative priorities, so that the constraints defined for higher priority regions take precedence over those defined for lower priority regions. The teachings of Bales are directly applicable to Lee, Hetzel, Ou, and Teig, so that Lee would similarly route interposers using routing regions having different relative priorities, to provider greater routing flexibility while allowing designers to prioritize selected routing constraints over others. Claim(s) 5, 12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hetzel, Ou, Teig, and Culp (US 2004/0210863). Regarding claim 5, Lee does not appear to explicitly disclose that the circuitry is further configured to generate a report that indicates whether the placement of the plurality of signal types in the plurality of levels of metal layers includes a minimum junction area specified by the plurality of attributes. Culp discloses these limitations (¶¶5, 37, 38). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Lee, Hetzel, Ou, Teig, and Culp, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of ensuring that there is sufficient overlap to meet design requirements for a properly functioning circuit. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Lee discloses routing signals of an interposer. Culp teaches that when routed signals should be checked for minimum junction area in order to meet design requirements. The teachings of Culp are directly applicable to Lee in the same way, so that Lee would similarly check that routed signals have minimum junction area to meet design requirements for a properly functioning circuit. Claim(s) 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hetzel, Ou, Teig, and Yaguchi (US 2005/0278679). Regarding claims 6 and 13, Lee does not appear to explicitly disclose that the circuitry is further configured to generate the placement of the plurality of signal types of the plurality of levels of metal layers in an order of sequences specified by the plurality of attributes, wherein each sequence identifies one of the plurality of levels of metal layers. Yaguchi discloses these limitations (Abstract, ¶99). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Lee, Hetzel, Ou, Teig, and Yaguchi, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of correctly routing signals through required routing layers according to design specifications. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Lee discloses routing signals through regions in various layers. Yaguchi teaches that the routing should progress through layers in a specified sequence. The teachings of Yaguchi are directly applicable to Lee in the same way, so that Lee would similarly route signals through layers in a given sequence in accordance with design intent. Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hetzel, Ou, Teig, and Chiang (US 2019/0370433). Regarding claims 7 and 14, Lee discloses that the plurality of levels of metal layers are redistribution layers between an integrated circuit and a printed circuit board (Fig. 1; ¶¶16, 27). If Lee is found to be unclear regarding these limitations, Chiang discloses the same (Fig. 1a; ¶2). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Lee, Hetzel, Ou, Teig, and Chiang, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing ICs to connect to each other and external circuitry through PCBs/packaging. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Lee discloses an interposer having redistribution layers (RDLs) connected to a PCB or package substrate and on which ICs are mounted. Persons having ordinary skill in the art would recognize interposers comprise a plurality of RDLs between the ICs and PCB/package to allow connection between the ICs and PCB/package. The teachings of Chiang are directly applicable to Lee in the same way, so that Lee would similarly be used for routing of RDLs to provide connectivity between ICs and PCBs/package substrates. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hetzel, Ou, Teig, Culp, and Chiang. Regarding claim 20, Lee discloses that the plurality of levels of metal layers are redistribution layers between an integrated circuit and a printed circuit board (Fig. 1; ¶¶16, 27). If Lee is found to be unclear regarding these limitations, Chiang discloses the same (Fig. 1a; ¶2). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Lee, Hetzel, Ou, Teig, Culp, and Chiang, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing ICs to connect to each other and external circuitry through PCBs/packaging. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Lee discloses an interposer having redistribution layers (RDLs) connected to a PCB or package substrate and on which ICs are mounted. Persons having ordinary skill in the art would recognize interposers comprise a plurality of RDLs between the ICs and PCB/package to allow connection between the ICs and PCB/package. The teachings of Chiang are directly applicable to Lee in the same way, so that Lee would similarly be used for routing of RDLs to provide connectivity between ICs and PCBs/package substrates. Response to Arguments Applicant's arguments filed 3 November 2025 have been fully considered but they are not persuasive. Applicant asserts that the design specification has too much information for a circuit designer to think about and that a circuit designer cannot think about both the entire netlist and the entirety of the attributes and the design rule checks, select a metal level of the interposer, choose correct data of the netlist and attributes for the selected metal level, and then decide how to place different signal types in the level. Remarks 8. The examiner disagrees. Circuit designers can and have routed designs manually; see e.g., US 4,701,860 to Mader, col. 2, lines 7-8; US 2003/0041309 to Chopra, ¶30; US 2006/0242614 to Wadland, ¶3. Applicant further asserts that a designer is unable to perform the added limitation of “automated analysis of design-rule data associated with the mask layout data”. Remarks 8. The examiner disagrees. Including the word ‘automated’ to the step merely indicates generic computer implementation of the step. The analysis of design rule data could absolutely be performed by a designer, since design rules include e.g. defined routing tracks and preferred routing directions. The claim also does not specify what sort of ‘analysis’ is being performed, so there is no basis to assert that a designer could not perform it. Applicant asserts that the mask layout is used for fabrication. Remarks 9. The examiner disagrees. The claim does not require fabrication of the interposer. Even assuming, arguendo, that Applicant’s intended purpose for the mask layout is to fabricate the interposer, the claimed invention itself stops short of fabricating the interposer, and remains entirely within the realm of design and information generation. A designer performing the claimed design steps and producing no actual physical interposer literally satisfies the claim. Applicant asserts that the prior art fails to disclose “responsive to a determination that an overlap region exists between two boundary regions, generate second placement data indicative of a placement of the given signal type using a first metal density of the two different metal densities in the overlap region” because Hetzel’s overlapping region utilizes two different orientations, and Teig’s overlapping region has the same pitch. Remarks 11. The examiner disagrees. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As explained in the office action, “Hetzel discloses that routing metal layers should be done according to regions that define different allowable routing orientations and densities; Ou similarly discloses that routing should be done according to regions that define different allowable densities even when the orientations are the same; Teig further teaches that routing regions having the same orientations can overlap. Hetzel further teaches that when regions overlap, routing density of one region can also be used in the overlap region.” In short, Hetzel teaches local preferred direction routing (LPDR) regions having distinct densities, and Teig teaches overlapping routing regions having the same orientation; the deficiency Applicant asserts against Hetzel is taught by Teig, and the deficiency Applicant asserts against Teig is taught by Hetzel. Thus, the claims are obvious over the combination of prior art teachings in the manner explained above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIC LIN whose telephone number is (571)270-3090. The examiner can normally be reached M-F 07:30-17:00 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. 5 February 2026 /ARIC LIN/ Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Dec 29, 2021
Application Filed
Mar 18, 2024
Non-Final Rejection — §101, §103
Aug 22, 2024
Response Filed
Nov 30, 2024
Final Rejection — §101, §103
Apr 02, 2025
Request for Continued Examination
Apr 03, 2025
Response after Non-Final Action
Jul 01, 2025
Non-Final Rejection — §101, §103
Nov 03, 2025
Response Filed
Feb 05, 2026
Final Rejection — §101, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
60%
Grant Probability
72%
With Interview (+12.6%)
3y 3m
Median Time to Grant
High
PTA Risk
Based on 521 resolved cases by this examiner. Grant probability derived from career allow rate.

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