DETAILED ACTION
This action is for Request for Continued Examination regarding application number 17/564,802 filed 05/21/2026. Claims 1-26 have been examined and are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicants’ submission filed on 05/21/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the
statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a
new ground of rejection if the prior art relied upon, and the rationale supporting the rejection,
would be the same under either status.
Information Disclosure Statements
Applicant's Information Disclosure Statements, filed on 05/21/2026 and 07/22/2026 have been received and entered into the record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Regarding claims 1-3, 5-10, 13-16, 18-23 and 26:
Claim(s) 1-3, 5-10, 13-16, 18-23 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Neill et al(US20210182728A1, “Two-qubit gates implemented with a tunable coupler” henceforth known as Neill) in view of Garion et al(“Experimental implementation of non-Clifford interleaved randomized benchmarking with a controlled-S gate” henceforth in view of Garion)
Regarding claims 1, Neill teaches a method for achieving an error divisible gate in a quantum computing system having a gate coupled between a pair of qubits((Neill, [0047], “The predetermined threshold for the accuracy of the target unitary transformation may be determined based on a target fidelity of the two-qubit gate.”).
Neill teaches selecting an intrinsic gate error rate threshold(Neill, [0046], “The selected unitary transformation control signal results in a target unitary transformation of the first data qubit and second data qubit having an accuracy above a predetermined threshold when the unitary transformation control signal is applied to the tunable coupler over the predetermined period of time”) for the gate coupled between a pair of qubits in a quantum computing system(Neill, [0047], “The predetermined threshold for the accuracy of the target unitary transformation may be determined based on a target fidelity of the two-qubit gate.”)
Neill teaches determining a first gate time to execute a full entangling gate rotation on the gate(Neill, [0005] “…the method further comprises, selecting the unitary transformation control signal from a plurality of different candidate control signals, wherein the selected unitary transformation control signal results in a target unitary transformation of the first data qubit and second data qubit having an accuracy above a predetermined threshold when the unitary transformation control signal is applied to the tunable coupler over the predetermined period of time” where the transformation control signal selected resulting in a target unitary transformation of a first and second qubit over predetermined period of time corresponds to determining a first gate time to execute a full entangling gate rotation on the gate as the transformation control signal causes the rotation/transformation of qubits) with a first error rate less than the intrinsic gate error rate threshold(Neill, [0006], “…selecting the unitary transformation control signal from the plurality of different candidate control signals comprises: for each different candidate control signal, applying the candidate control signal to the tunable coupler, wherein two or more of the different candidate control signals comprise different maximum amplitude values, determining, for each different candidate control signal applied to the tunable coupler, a corresponding accuracy of the unitary transformation of the first data qubit and the second data qubit, and identifying the candidate control signal that results in the unitary transformation having the accuracy above the predetermined threshold” where determining each candidates accuracy of the unitary transformation that is created by applying a candidate control signal corresponds to determining a first error rate and determining an accuracy of candidates above the predetermined threshold corresponds to determining a first error rate less than error rate less than the intrinsic gate error rate threshold )
Neill teaches selecting the second gate time as a final gate time when the second error rate is smaller than the first error rate(Neill, [0048], “…to minimize the effect of decoherence a shorter total pulse length that does not degrade an intrinsic fidelity of the gate may be chosen” and Neill, [0053], “Applying two or more of the different candidate control signals to the tunable coupler may include applying the two or more different candidate control signals to the tunable coupler over different periods of time.…these cases the candidate periods of time may be chosen to be longer than 1/200 MHz, e.g., 5 ns, 6 ns, 7 ns, 8 ns or slower.” where choosing a shorter total pulse length out of the candidates that does not degrade the intrinsic fidelity of the gate corresponds to selecting the second gate time as a final gate time when the second error rate is smaller than the first error rate as each candidate is tested and evaluated(See also, Neill, [0055], “In a second step of the process, a corresponding accuracy of the unitary transformation of the first data qubit and the second data qubit is determined for each different candidate control signal applied to the tunable coupler (step 304). The accuracy may be determined by measuring the state of the first data qubit and second data qubit after each application of one of the different candidate control signals to the tunable coupler.”))
Neill teaches operating the gate, wherein a total error rate of the quantum computing system is reduced(Neill, [0063], “Further, the simulation results show that a fermionic SWAP gate realized by applying a unitary transformation control signal to a tunable coupler as described with reference to FIGS. 2 and 3 has high fidelity and the error per fermionic SWAP gate is about 0.4% or about 0.2%. An error of 0.2% is approximately 3 times smaller than the smallest two-qubit gate error achieved using other known techniques”)
Neill does not explicitly disclose, however Garion discloses based on the first gate time to execute the full entangling rotation on the gate, applying, to the gate, a second gate rotation having a second gate time less than the first gate time in order to determine a second error rate.
Garion discloses based on the first gate time(Garion, Page 3, Col. 1, “We performed calibration to a CR rotation angle
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for different values of τsq.” where τsq corresponds to a pulse-duration parameter) to execute the full entangling rotation on the gate(Garion, Page 3, Col. 1, Paragraph 3, “We use the CR pulse sequence as a generator of two-qubit entanglement”), applying, to the gate, a second gate rotation having a second gate time less than the first gate time(Garion, Page 5, Fig. 2, where Figure 2 shows the average gate error as a function of τsq with the corresponding gate time total with less time showing a smaller error associated with a smaller rotation) in order to determine a second error rate(Garion, Page 2, Col. 1, Paragraph 1, “In this work we calibrate CS and CS−1 gates of varying durations on an IBM Quantum system and benchmark the gate error rates…For specific gate durations we are able to obtain a high-fidelity CS gate approaching the coherence limit, which due to the shorter CR interaction time results in a lower error rate” where choosing gate durations that are shorter to receive a lower error rate corresponds to based on the first gate time to execute the full entangling rotation on the gate, applying, to the gate, a second gate rotation having a second gate time less than the first gate time in order to determine a second error rate(See also, Garion, Page 5, Col. 2, Paragraph 4, “We obtained a minimal gate error of 5.9(7) × 10−3 with appropriately shaped echoes and a total gate time of 263.1 ns…By performing RB and QPT for a variety of gate lengths we were also able to study the performance of the CS gate in different regimes and observed a break down in performance if gate lengths were reduced below the best value obtained for 263.1 ns.” and Garion, Page 5, Fig. 2, where Figure 2 shows the average gate error as a function of τsq with the corresponding gate time total))
References Neill and Garion are analogous art because they are from the same field of endeavor of implementing/controlling a two-qubit gate so that it is fast and/or has low error/high fidelity.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Neill and Garion before him or her, to modify the qubit error measurement process of Neill to include the time iteration testing of Garion to determine the best performance of the gate. The suggestion/motivation for doing so would have been Garion, Page 1, Col. 2, Paragraph 2, “…with a shorter gate duration or lower power, potentially leading to a higher fidelity two-qubit gate when calibrated close to the coherence limit” and Garion, Page 5, Col. 2, Paragraph 4, “for a variety of gate lengths we were also able to study the performance of the CS gate in different regimes and observed a break down in performance if gate lengths were reduced below the best value obtained for 263.1 ns”)
Regarding claim 2, Neill-Garion teaches the method of claim 1(and thus the rejection
of claim 1 is incorporated).
Garion further teaches based on the first gate time(Garion, Page 3, Col. 1, “We performed calibration to a CR rotation angle
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for different values of τsq.” where τsq corresponds to a pulse-duration parameter) to execute a full entangling gate rotation(Garion, Page 3, Col. 1, Paragraph 3, “We use the CR pulse sequence as a generator of two-qubit entanglement”), applying, to the gate, a third gate rotation having a third gate time less than the second gate time(Garion, Page 5, Fig. 2, where Figure 2 shows the average gate error as a function of τsq with the corresponding gate time total with less time showing a smaller error associated with a smaller rotation) in order to determine a third error rate(Garion, Page 2, Col. 1, Paragraph 1, “In this work we calibrate CS and CS−1 gates of varying durations on an IBM Quantum system and benchmark the gate error rates…For specific gate durations we are able to obtain a high-fidelity CS gate approaching the coherence limit, which due to the shorter CR interaction time results in a lower error rate” where choosing gate durations that are shorter to receive a lower error rate corresponds based on the first gate to execute a full entangling gate rotation, applying, to the gate, a third gate rotation having a third gate time less than the second gate time in order to determine a third error rate (See also, Garion, Page 5, Col. 2, Paragraph 4, “We obtained a minimal gate error of 5.9(7) × 10−3 with appropriately shaped echoes and a total gate time of 263.1 ns…By performing RB and QPT for a variety of gate lengths we were also able to study the performance of the CS gate in different regimes and observed a break down in performance if gate lengths were reduced below the best value obtained for 263.1 ns.”))
Garion discloses selecting the third gate rotation when the third error rate is smaller than the first error rate (Garion, Page 5, Fig. 2, where Figure 2 shows the average gate error as a function of τsq with the corresponding gate time total with less time showing a smaller error associated with a smaller rotation and the error at 250 τsq is smaller than the error at 350 τsq )
Regarding claim 3, Neill-Garion discloses the method of claim 1(and thus the rejection
of claim 1 is incorporated).
Neill teaches determining the second error rate after application of the second gate rotation having a second gate time (Neill, [0006], “…for each different candidate control signal applied to the tunable coupler, a corresponding accuracy of the unitary transformation of the first data qubit and the second data qubit, and identifying the candidate control signal that results in the unitary transformation having the accuracy above the predetermined threshold” where determining each candidates accuracy of the unitary transformation that is created by applying a candidate control signal for a period of time corresponds to determining the second error rate after application of the second gate rotation having a second gate time)
Regarding claim 5, Neill-Garion teaches the method of claim 1(and thus the rejection
of claim 1 is incorporated).
Garion teaches, further comprising applying, to the gate, a waveform having a frequency(Garion “The CR pulse is realized by ir radiating one (control) qubit with a microwave pulse at the transition frequency of another (target) qubit”) determined based on the second gate rotation(Garion, Page 3, Col. 1, “We performed calibration to a CR rotation angle
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for different values of τsq.” where τsq corresponds to a pulse-duration parameter) to perform quantum error correction for the quantum computing system(Garion, Page 5, Fig. 2, where Figure 2 shows the average gate error as a function of τsq with the corresponding gate time total with less time showing a smaller error associated with a smaller rotation)
Regarding claim 6, Neill-Garion teaches the method of claim 5(and thus the rejection
of claim 1 is incorporated).
Neill teaches wherein the pair of qubits comprises a primary bit coupled to an auxiliary qubit (Neill, “…the first value corresponds to a value at which there is no coupling between the first data qubit and the second data qubit” where the first qubit corresponds to a primary bit and a second qubit corresponds to a secondary qubit)
Regarding claim 7, Neill-Garion teaches the method of claim 1(and thus the rejection
of claim 1 is incorporated).
Neill teaches further comprising tuning the gate via a tunable coupling element (Neill, [0003], “The present disclosure describes technologies for implementing two-qubit quantum logic gates using a tunable coupler.”)
Regarding claim 8, Neill-Garion teaches the method of claim 1(and thus the rejection
of claim 1 is incorporated).
Neill teaches wherein the tunable coupling element includes a capacitor, an inductor, or a combination thereof (Neill, [0041], “For example, the tunable coupling 108 may include a three-terminal device constructed from superconductor materials using a fixed negative mutual inductance and a single, current-biased Josephson junction that acts as a tunable positive inductance”)
Regarding claim 9, Neill-Garion teaches the method of claim 1(and thus the rejection
of claim 1 is incorporated).
Neill teaches further comprising tuning the pair of qubits, wherein the gate is configured to provide fixed coupling (Neill, [0041], “For example, the tunable coupling 108 may include a three-terminal device constructed from superconductor materials using a fixed negative mutual inductance and a single, current-biased Josephson junction that acts as a tunable positive inductance” where the fixed negative mutual inductance corresponds to the coupling having a fixed property)
Regarding claim 10, Neill-Garion teaches the method of claim 1(and thus the rejection
of claim 1 is incorporated).
Neill teaches wherein the pair of qubits are included in a multi-qubit architecture having a plurality of one-bit and/or two-bit gates, including the gate(Neill, [0025] , “Two-qubit gates that form a universal set of quantum gates in combination with single qubit gates can be realized using the techniques described in this specification” where the single-qubit and two-qubit gates correspond to a multi-qubit architecture having a plurality of one-bit and/or two-bit gates, including the gate)
Regarding claim 13, Neill-Garion teaches the method of claim 10(and thus the rejection
of claim 1 is incorporated).
Garion teaches further comprising tuning the pair of qubits in a multi-bit architecture such that relatively smaller angle gates of the plurality of one-bit or two-bit gates, have a proportionally smaller error than relatively larger-angle gates of the plurality of one-bit or two-bit gates(Garion, Page 5, Fig. 2, where Figure 2 shows the average gate error as a function of τsq with the corresponding gate time total with less time showing a smaller error associated with a smaller rotation)
Regarding claims 14, Neill teaches non-transitory computer-readable medium storing program instructions that are executable on a computer processor unit(Neill, [0080], “Control of the various systems described in this specification, or portions of them, can be implemented in a computer program product that includes instructions that are stored on one or more non-transitory machine-readable storage media, and that are executable on one or more processing devices”)
Neill teaches select an intrinsic gate error rate threshold(Neill, [0046], “The selected unitary transformation control signal results in a target unitary transformation of the first data qubit and second data qubit having an accuracy above a predetermined threshold when the unitary transformation control signal is applied to the tunable coupler over the predetermined period of time”) for the gate coupled between a pair of qubits in a quantum computing system(Neill, [0047], “The predetermined threshold for the accuracy of the target unitary transformation may be determined based on a target fidelity of the two-qubit gate.”)
Neill teaches determine a first gate time to execute a full entangling gate rotation on the gate(Neill, [0005] “…the method further comprises, selecting the unitary transformation control signal from a plurality of different candidate control signals, wherein the selected unitary transformation control signal results in a target unitary transformation of the first data qubit and second data qubit having an accuracy above a predetermined threshold when the unitary transformation control signal is applied to the tunable coupler over the predetermined period of time” where the transformation control signal selected resulting in a target unitary transformation of a first and second qubit over predetermined period of time corresponds to determining a first gate time to execute a full entangling gate rotation on the gate as the transformation control signal causes the rotation/transformation of qubits) with a first error rate less than the intrinsic gate error rate threshold(Neill, [0006], “…selecting the unitary transformation control signal from the plurality of different candidate control signals comprises: for each different candidate control signal, applying the candidate control signal to the tunable coupler, wherein two or more of the different candidate control signals comprise different maximum amplitude values, determining, for each different candidate control signal applied to the tunable coupler, a corresponding accuracy of the unitary transformation of the first data qubit and the second data qubit, and identifying the candidate control signal that results in the unitary transformation having the accuracy above the predetermined threshold” where determining each candidates accuracy of the unitary transformation that is created by applying a candidate control signal corresponds to determining a first error rate and determining an accuracy of candidates above the predetermined threshold corresponds to determining a first error rate less than error rate less than the intrinsic gate error rate threshold )
Neill teaches select the second gate time as a final gate time when the second error rate is smaller than the first error rate(Neill, [0048], “…to minimize the effect of decoherence a shorter total pulse length that does not degrade an intrinsic fidelity of the gate may be chosen” and Neill, [0053], “Applying two or more of the different candidate control signals to the tunable coupler may include applying the two or more different candidate control signals to the tunable coupler over different periods of time.…these cases the candidate periods of time may be chosen to be longer than 1/200 MHz, e.g., 5 ns, 6 ns, 7 ns, 8 ns or slower.” where choosing a shorter total pulse length out of the candidates that does not degrade the intrinsic fidelity of the gate corresponds to selecting the second gate time as a final gate time when the second error rate is smaller than the first error rate as each candidate is tested and evaluated(See also, Neill, [0055], “In a second step of the process, a corresponding accuracy of the unitary transformation of the first data qubit and the second data qubit is determined for each different candidate control signal applied to the tunable coupler (step 304). The accuracy may be determined by measuring the state of the first data qubit and second data qubit after each application of one of the different candidate control signals to the tunable coupler.”))
Neill teaches operating the gate, wherein a total error rate of the quantum computing system is reduced(Neill, [0063], “Further, the simulation results show that a fermionic SWAP gate realized by applying a unitary transformation control signal to a tunable coupler as described with reference to FIGS. 2 and 3 has high fidelity and the error per fermionic SWAP gate is about 0.4% or about 0.2%. An error of 0.2% is approximately 3 times smaller than the smallest two-qubit gate error achieved using other known techniques”)
Neill does not explicitly disclose, however Garion discloses based on the first gate time to execute the full entangling rotation on the gate, applying, to the gate, a second gate rotation having a second gate time less than the first gate time in order to determine a second error rate.
Garion discloses based on the first gate time(Garion, Page 3, Col. 1, “We performed calibration to a CR rotation angle
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for different values of τsq.” where τsq corresponds to a pulse-duration parameter) to execute the full entangling rotation on the gate(Garion, Page 3, Col. 1, Paragraph 3, “We use the CR pulse sequence as a generator of two-qubit entanglement”), applying, to the gate, a second gate rotation having a second gate time less than the first gate time(Garion, Page 5, Fig. 2, where Figure 2 shows the average gate error as a function of τsq with the corresponding gate time total with less time showing a smaller error associated with a smaller rotation) in order to determine a second error rate (Garion, Page 2, Col. 1, Paragraph 1, “In this work we calibrate CS and CS−1 gates of varying durations on an IBM Quantum system and benchmark the gate error rates…For specific gate durations we are able to obtain a high-fidelity CS gate approaching the coherence limit, which due to the shorter CR interaction time results in a lower error rate” where choosing gate durations that are shorter to receive a lower error rate corresponds to based on the first gate time to execute the full entangling rotation on the gate, applying, to the gate, a second gate rotation having a second gate time less than the first gate time in order to determine a second error rate(See also, Garion, Page 5, Col. 2, Paragraph 4, “We obtained a minimal gate error of 5.9(7) × 10−3 with appropriately shaped echoes and a total gate time of 263.1 ns…By performing RB and QPT for a variety of gate lengths we were also able to study the performance of the CS gate in different regimes and observed a break down in performance if gate lengths were reduced below the best value obtained for 263.1 ns.” and Garion, Page 5, Fig. 2, where Figure 2 shows the average gate error as a function of τsq with the corresponding gate time total))
Regarding claim 15, The rejection of claim 14 incorporated in claims 15, and further, claim 15 is rejected under the same rationale as set forth in the rejection of claims 2 respectively.
Regarding claim 16, The rejection of claim 14 incorporated in claims 16, and further, claim 16 is rejected under the same rationale as set forth in the rejection of claims 5 respectively.
Regarding claim 18, The rejection of claim 14 incorporated in claims 18, and further, claim 18 is rejected under the same rationale as set forth in the rejection of claims 5 respectively.
Regarding claim 19, The rejection of claim 18 incorporated in claim 19, and further,
claim 19 is rejected under the same rationale as set forth in the rejection of claim 6.
Regarding claims 20-23, The rejection of claim 14 incorporated in claims 20-23, and further, claims 20-23 are rejected under the same rationale as set forth in the rejection of claims 7-10 respectively.
Regarding claim 26, The rejection of claim 14 incorporated in claim 26, and further,
claim 26 is rejected under the same rationale as set forth in the rejection of claim 13.
Regarding claims 4 and 7:
Claim(s) 4 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Neil et al(US20210182728A1, “Two-qubit gates implemented with a tunable coupler” henceforth known as Neill) in view of Garion et al(“Experimental implementation of non-Clifford interleaved randomized benchmarking with a controlled-S gate” henceforth in view of Garion) and further in view of Campbell(Random Compiler for Fast Hamiltonian Simulation henceforth known as Campbell).
Regarding claim 4, Neill-Garion teaches the method of claim 1(and thus the rejection
of claim 1 is incorporated).
Neill-Garion does not teach; however Campbell discloses iteratively applying(Campbell, Page 2, Col. 2, FIG. 1. Pseudocode, section 5 shows iterative application based on N a sampling process from a probability distribution to select which unitary(rotation) to apply), to the gate, incrementally smaller gate rotations having incrementally smaller gate times(Campbell, Page 2, Col. 2, Paragraph 3, “The strength τj of each unitary is fixed to a constant τj = τ := tλ/N” where the unitary is defined as both the action and the time it takes divided by N gate steps and lowers the time and rotation for each gate for every N added which is considered incrementally) until an achieved error rate(Campbell, Page 3, Col. 2, Paragraph 2, “We see the total error decreases as we increase N”) exceeds the first error rate (Campbell, Page 2, Col. 1, Paragraph 3, “The gate count in this sequence will be N = Lr, so we would like to know the smallest r that suffices to achieve a desired precision ε” where desired precision ε is considered an error rate)
Regarding claim 17, The rejection of claim 14 incorporated in claims 17, and further, claim 17 is rejected under the same rationale as set forth in the rejection of claim 4 respectively.
References Neill-Garion and Campbell are analogous art because they are from the same field of endeavor of quantum computing hardware and simulation methods with quantum information processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Neill-Garion and Campbell before him or her, to modify the qubit rotation method of Neill-Garion to include the gate step division of qDRIFT of Campbell’s method reports to speed and cause reduce errors in quantum simulations. The suggestion/motivation for doing so would have been “we find that our approach can speed up quantum simulations of electronic structure Hamiltonians by several orders of magnitude” (Campbell, Page 1, Col 2, Paragraph 2)
Regarding claims 11-12 and 24-25:
Claim(s) 11-12 and 24-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Neil et al(US20210182728A1, “Two-qubit gates implemented with a tunable coupler” henceforth known as Neill) in view of Garion et al(“Experimental implementation of non-Clifford interleaved randomized benchmarking with a controlled-S gate” henceforth in view of Garion) and further in view of Venturelli et al.( Compiling quantum circuits to realistic hardware architectures using temporal planners), henceforth known as Venturelli.
Regarding claim 11, Neill-Garion teaches the method of claim 10(and thus the rejection
of claim 10 is incorporated).
Neill teaches further comprising operating, via the quantum computing system, the plurality of one-bit and/or two-bit gates based on a quantum algorithm(Neill, [0025] , “Two-qubit gates that form a universal set of quantum gates in combination with single qubit gates can be realized using the techniques described in this specification” where the single-qubit and two-qubit gates correspond to operating, via the quantum computing system, the plurality of one-bit and/or two-bit gates based on a quantum algorithm).
Neill does not teach; however Venturelli discloses and according to a schedule(Venturelli, Page 13, Paragraph 1,“ we apply temporal planning techniques to the problem of compiling quantum circuits to realistic gate-model quantum hardware”)
References Neill and Venturelli are analogous art because they are from the same field of endeavor of quantum computing hardware and quantum optimization techniques.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Neill and Venturelli before him or her, to modify the qubit rotation method of Neill to include the scheduler of Venturelli as the scheduler provides a method of reducing runtime. The suggestion/motivation for doing so would have been “The temporal planners aim to provide a machine-dependent plan that minimizes makespan, while respecting all machine-dependent constraints”” (Venturelli, Page 3, Paragraph 5)
Regarding claim 12, Neill -Venturelli teaches the method of claim 11(and thus the rejection of claim 11 is incorporated).
Venturelli additionally discloses further comprising providing the schedule via a compiler of the quantum computing system (Venturelli, Page 15, Paragraph 3, “This temporal planning approach to quantum circuit compilation should be of great interest to the community developing low-level quantum compilers for generic architectures … and to designers of machine-instructions languages for quantum computing”), wherein the schedule is provided for operation the plurality of one-bit and/or two-bit gates(Venturelli, Page 9, Paragraph 2, “Temporal planning actions are created to model:(i) 2-qubit SWAP gates,(ii) 2-qubit P S-gates, and (iii) 1-qubit MIX gates” where the actions the schedule can operate include using gates that include rotational gate. Specifically P-S gates(2 qubits) and MIX gates(1 qubit) is considered having a scheduler that operates multiple small angle one-bit and/or two-bit gates) to minimize a total runtime of the quantum algorithm(Venturelli, Page 3, Paragraph 5,“ The most common objective function in temporal planning is to minimize the plan makespan, i.e. the shortest total plan execution time. This objective matches well with the objective of our targeted quantum circuit compilation problem.” where makespan is considered, at least in part of, the total runtime of a quantum algorithm and minimizing the makespan is considered minimizing the total runtime of a quantum algorithm)
References Neill and Venturelli are analogous art because they are from the same field of endeavor of quantum computing hardware and quantum optimization techniques.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Neill and Venturelli before him or her, to modify the qubit rotation method of Neill to include the scheduler of Venturelli as the scheduler provides a method of reducing runtime. The suggestion/motivation for doing so would have been “The temporal planners aim to provide a machine-dependent plan that minimizes makespan, while respecting all machine-dependent constraints” (Venturelli, Page 3, Paragraph 5)
Regarding claim 24, The rejection of claim 15 incorporated in claim 24, and further,
claim 24 is rejected under the same rationale as set forth in the rejection of claim 11.
Regarding claim 25, The rejection of claim 15 incorporated in claim 25, and further,
claim 25 is rejected under the same rationale as set forth in the rejection of claim 12.
Relevant Art
While not used in the current rejection, Examiner found the following prior art:
McKay et al. “Efficient Z gates for quantum computing” as the references describes a similar use of thresholds and rotation of qubit.
Response to Arguments
Applicant's arguments filed 05/21/2026 have been fully considered but they are not persuasive. A breakdown of arguments can be found below:
102/103:
Applicant appears to argue on pages 6-10 that gate fidelity used in Nichol is not the same as an intrinsic gate error rate and that aiming to cancel inherent noise for qubits is not a threshold.
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument as prior art Nichol is no longer used in the rejection after further search found closer prior art for the current claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES JEFFREY JONES JR whose telephone number is (703)756-1414. The examiner can normally be reached Monday - Friday 8:00 - 5:00 EST.
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/C.J.J./Examiner, Art Unit 2122
/KAKALI CHAKI/Supervisory Patent Examiner, Art Unit 2122
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