DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/08/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to amendments and remarks filed on 04/24/2026, which have been entered. In the current amendments, claims 1, 8, and 15 are amended. Claims 1-20 are pending and have been examined.
In response to amendments and remarks filed on 04/24/2026, the 35 U.S.C. 101 non-statutory subject matter rejections, and the 35 U.S.C. 101 abstract idea rejections made in the previous office action have been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 8-12, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Petre et al. (US 10,404,299 B1) in view of Smith et al. (US 2019/0120932 A1) and further in view of Petre, Matic, and Virbila (US 10,211,856 B1); hereinafter Matic et al.
Regarding Claim 1,
Petre et al. teaches a cognitive signal processor comprising: a reservoir computer … a delay embedding component; a weight adaptation component; and an output layer computer (Fig. 6; Col. 6, lines 38-42: "This disclosure provides a system for signal processing (or otherwise referred to as a “cognitive” signal processor (CSP)) that takes an input signal containing a mixture of pulse waveforms over a very large (e.g., >30 GHz) bandwidth and denoises the input signal" teaches a cognitive signal processor (CSP). Fig. 6; Col. 6, lines 43-59: "The CSP includes three primary components. The first component is a reservoir computer (RC), which is the cognitive-inspired aspect of the CSP. The dynamic reservoir computer maps an input signal to a high-dimensional dynamical system known as the reservoir. The reservoir connectivity weights are optimized for the task of signal denoising. The second component is a delay embedding that creates a finite temporal record of the values of the reservoir states. The third component is a weight adaptation module that adapts the output of the reservoir via gradient descent to produce a prediction of the input signal a small time-step in the future. Since the noise in the input signal is inherently random and unpredictable, the predicted input signal will be free of noise (i.e., denoised signal). The error between the predicted input signal and actual input is used by the weight adaptation module to further tune the output weights of the reservoir in an iterative process" teaches that the CSP comprises a dynamic reservoir (reservoir computer), a delay embedding component, and a weight adaptation module (component). Fig. 6; Col. 14, lines 20-21: "The model shows the dynamic reservoir 400 with fixed connections (A) and adaptable output layers attached to it" teaches that the CSP comprises adaptable output layers (output layer computer)),
wherein, an output of the reservoir computer is communicatively coupled to an input of the reservoir computer and to the delay embedding component, the reservoir computer being configured to produce a plurality of reservoir state values (Fig. 4; Fig. 6; Col. 12, lines 39-52: "As shown in FIG. 4, the dynamic reservoir 400 according to the various embodiments of the present invention applies a delay embedding 402 to the reservoir states to provide a time history of reservoir dynamics. As shown, the 402 delay-embedding is applied to each of the reservoir states instead of to the input signal 404. This provides three key benefits. First, time delays and adaptation are only required at the output of the reservoir, rather than at the input. Second, having a temporal record of the states provides more useful information for signal analysis than a temporal record of the raw signal input. Third when combined with the designed reservoir states, delay-embedded states enable each state to be denoised separately, which can be used to generate a denoised spectrogram of the input signal" teaches that the reservoir computer output is coupled to the reservoir computer input and to the delay component. Fig. 4; Fig. 6; Col. 2, lines 41-46: "This disclosure provides a system for signal processing (or otherwise referred to as a “cognitive” signal processor (CSP)) that takes an input signal containing a mixture of pulse waveforms over a very large (e.g., >30 GHz) bandwidth and denoises the input signal" teaches that the dynamic reservoir (reservoir computer) produces reservoir states);
an input of the delay embedding component communicatively coupled to an output of the reservoir computer and an output of the delay embedding component communicatively coupled to an input of the weight adaptation component and to an input of the output layer computer, the delay embedding component configured to collect the plurality of reservoir state values (Fig. 4; Fig. 6; Col. 12, lines 39-52: "As shown in FIG. 4, the dynamic reservoir 400 according to the various embodiments of the present invention applies a delay embedding 402 to the reservoir states to provide a time history of reservoir dynamics. As shown, the 402 delay-embedding is applied to each of the reservoir states instead of to the input signal 404. This provides three key benefits. First, time delays and adaptation are only required at the output of the reservoir, rather than at the input. Second, having a temporal record of the states provides more useful information for signal analysis than a temporal record of the raw signal input. Third when combined with the designed reservoir states, delay-embedded states enable each state to be denoised separately, which can be used to generate a denoised spectrogram of the input signal" teaches that the delay embedding component input is coupled to the reservoir computer output, and that the delay embedding component collects the reservoir states. Fig. 6; Col. 14, lines 26-30: "That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the delay embedding of states component (delay embedding component) output is communicatively coupled to the input of the gradient learning algorithm 602 (weight adaptation component) and to the input of the output layers 604 (output computer));
an output of the weight adaptation component communicatively coupled to an input of the weight adaptation component and to an input of the output layer computer, the weight adaptation component configured to compute a plurality of reservoir state value weights to produce a plurality of output values (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the output of the gradient descent algorithm 602 (weight adaptation component) is communicatively coupled to the input of the gradient descent algorithm 602 (weight adaptation component) and to the input of the output layers 604 (output computer), and that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) to produce outputs), and
an input of the output layer computer communicatively coupled to an output of the delay embedding component, an input of the output layer computer communicatively coupled to an output of the weight adaptation component, and an output of the output layer computer communicatively coupled to an input to the weight adaptation component, the output layer computer being configured to output the plurality of output values (Fig. 6; Col. 14, lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the input of the output layers 604 (output computer) is communicatively coupled to the output of the delay embedding of states component (delay embedding component) and the output of the gradient learning algorithm 602 (weight adaptation component), the output of the output layers 604 (output computer) is communicatively coupled to an input of the gradient learning algorithm 602 (weight adaptation component), and that the output layers 604 (output computer) outputs a plurality of outputs).
Petre et al. does not appear to explicitly teach wherein the reservoir computer comprises a reservoir connectivity matrix having a block-diagonal form, wherein each block of the reservoir connectivity matrix is of size 2 x 2 and corresponds to a single pole infinite impulse response (IIR) filter; wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored.
However, Smith et al. teaches wherein the reservoir computer comprises a reservoir connectivity matrix having a block-diagonal form, wherein each block of the reservoir connectivity matrix is of size 2 x 2 and corresponds to a single pole infinite impulse response (IIR) filter (Fig. 4; [0063]: "the reservoir state transition matrix A is constructed such that it is in a 2×2 block diagonal form. Each 2×2 block in the state matrix A corresponds to a single pole Infinite Impulse Response (IIR) filter" teaches a matrix A (reservoir connectivity matrix) of the reservoir computer having a 2×2 block diagonal form, with each block corresponding to an IIR filter. [0059]: "Where A is the reservoir connectivity matrix that determines the filter pole locations" teaches that the matrix A is the reservoir connectivity matrix).
Petre et al. and Smith et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the reservoir computer comprises a reservoir connectivity matrix having a block-diagonal form, wherein each block of the reservoir connectivity matrix is of size 2 x 2 and corresponds to a single pole infinite impulse response (IIR) filter as taught by Smith et al. to the disclosed invention of Petre et al.
One of ordinary skill in the art would have been motivated to make this modification for the reservoir to be "optimized for signal de-noising and efficient implementation in hardware" (Smith et al. [0014]).
Petre et al. in view of Smith et al. does not appear to explicitly teach wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored.
However, Matic et al. teaches wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the reservoir computer 600 is an adaptable nonlinear state space filter, wherein the states and outputs are iteratively updated (e.g. calculated) at sample times driven by a clock (e.g. over multiple clock cycles) for weight adaptation for adapting/updating output layer weights (reservoir state weight values) for the signal processing system. Fig. 1; Fig. 6; Col. 5, lines 10-30: "the HSC 108 can: tolerate realistic hardware constraints, such as feedback loop delay and delays in the feedforward paths; enable massively parallel implementations of high quality IIR filters; … the HSC 108 includes a parallel neuromorphic processor architecture that is configured to perform the neuromorphic processing. In this example, the parallel neuromorphic processor architecture is a reservoir computer that may be an echo state network or liquid-state machine. The reservoir computer includes a reservoir and a plurality of trainable readouts. In general, the reservoir computer is an adaptable state space filter having a plurality of reservoir connectivity matrix weights, plurality of input layer weights, and a plurality of output layer weights which will be described in greater detail later" teaches that the reservoir computer is an adaptable state space filter for implementing IIR filters. Fig. 1; Fig. 6; Col. 6, lines 40-49: "The HSC 108 utilizes an ordinary differential equation to delayed transformation to map the IIR filtering process onto a massively parallel neuromorphic processor architecture. As a result, this IIR filtering design can tolerate realistic hardware constraints, such as, for example, feedback loop delay and delays in the feedforward paths. Additionally, this IIR filtering design also allows the utilization of an arbitrary number of pipeline stages in each multiplier and summing junction in the implemented hardware IC" teaches that calculations for the IIR filtering performed by the reservoir computer can be performed over multiple pipeline stages (e.g. the weight update/adaptation for the output layer weights driven by a clock are performed using pipelining)).
Petre et al., Smith et al., and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored as taught by Matic et al. to the disclosed invention of Petre et al. in view of Smith et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 2,
Petre et al. in view of Smith et al. and further in view of Matic et al. teaches the cognitive signal processor of claim 1.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights that are updated over the multiple clock cycles by converting ordinary differential equations (ODE) of an output layer weight update equation to delay differential equations (DDE) (Fig. 4; Fig. 6; (86-101) Col. 14, line 23 - Col. 15, line 58: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise … To perform short-time prediction of the input signal, the system of the present disclosure uses the online gradient descent algorithm 602. The idea is to enforce exact prediction of the current time point that is used in the delay embedding. The predicted input value at time (t+τ) is calculated from the current value the of the output weights (ck(t), d(t)) and the current and past values of the states (x) and the input (u) … The ODEs for the dynamic reservoir and the weight adaptation system can be implemented directly in analog hardware. To implement the above ODEs in software or efficient digital hardware (e.g., field-programmable gate arrays (FPGAs) or custom digital application-specific integrated circuits (ASICs)), the update equations must be discretized … To implement the process of the present disclosure in software or digital hardware, the ODEs are converted to delay difference equations (DDEs)" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) that are adapted/updated by converting ODEs of the output weight update equation to delay difference equations (DDEs)).
Regarding Claim 3,
Petre et al. in view of Smith et al. and further in view of Matic et al. teaches the cognitive signal processor of claim 2.
In addition, Matic et al. further teaches wherein a representation for a next set of weights is computed over the multiple clock cycles (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the output weights (reservoir state weight values) are calculated at sample times driven by a clock (e.g. over multiple clock cycles) for adapting/updating output layer weights (computing next set of weights)).
Petre et al., Smith et al., and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein a representation for a next set of weights is computed over the multiple clock cycles as taught by Matic et al. to the disclosed invention of Petre et al. in view of Smith et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 4,
Petre et al. in view of Smith et al. and further in view of Matic et al. teaches the cognitive signal processor of claim 1.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights and a final output is computed using multiplication of the output layer weights with a history of state results (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) to produce outputs. Fig. 6; Fig. 8; Col. 17, lines 36-47: "The reservoir state vector x(t) is then split into individual elements 800 x1(t), . . . , xN(t), and for each reservoir state element 800 xi(t), a time history of its dynamics is created by applying a length-K delay embedding. The delay embedded reservoir state elements 801 xi(t), xi(t−τi), . . . , xi(t−Kτi) are multiplied by tunable output weights 802 Ci1, . . . , Ci(K+1), summed together and delayed by time delay 803 τSK to obtain denoised reservoir state element 804
x
~
i(t). The denoised reservoir state elements are them summed together, and delayed by time delay 805 τSN to obtain the denoised output signal 806 y(t)" teaches that a final output is computed by multiplying a time history of reservoir state results from the delay embedding with the output weights).
Regarding Claim 5,
Petre et al. in view of Smith et al. and further in view of Matic et al. teaches the cognitive signal processor of claim 1.
In addition, Matic et al. further teaches wherein an output delay is defined as a maximum of feedforward and feedback delays (Fig. 1; Fig. 4; Col. 5, lines 12-14: "As disclosed, the HSC 108 can: tolerate realistic hardware constraints, such as feedback loop delay and delays in the feedforward paths" teaches that the system tolerates both feedforward and feedback delays. Fig. 4; Fig. 7B; Col. 9, line 59 - Col. 10, line 19: " As such, in FIG. 7B, a system diagram is shown of an example of an implementation of the discretized DDE output equation for y(t) in accordance with the present disclosure … Again, the feedback delay value τ 808 is equal to the sampling period Δt 806 multiplied by the number of delay samples ne, where the feedback delay value τ 808 is the time window to be processed by the system. … In this example, it is assumed that the input sample rate (i.e., the inverse of the sampling period Δt 706 or 806) is equal to the clock speed of the digital processor. The output signal y(t) 800 is then determined from the updated state values xi and the most current input sample ui. Arbitrary feedforward delay values can be incorporated into the output update equation since there is no feedback connection in this part of the circuit. As such, the design can tolerate arbitrary feedforward and feedback delays" teaches that the delay for the output is based on is based on the greater (maximum) of the feedforward and feedback delays).
Petre et al., Smith et al., and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein an output delay is defined as a maximum of feedforward and feedback delays as taught by Matic et al. to the disclosed invention of Petre et al. in view of Smith et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 8,
Petre et al. teaches a method of denoising a signal by a cognitive signal processor (Col. 3, lines 21-30: "the present invention also includes a computer program product and a computer implemented method. The computer program product includes computer-readable instructions stored on a non-transitory computer-readable medium that are executable by a computer having one or more processors, such that upon execution of the instructions, the one or more processors perform the operations listed herein. Alternatively, the computer implemented method includes an act of causing a computer to execute such instructions and perform the resulting operations" teaches a method for performing operations of the embodiment. Fig. 6; Col. 6, lines 38-42: "This disclosure provides a system for signal processing (or otherwise referred to as a “cognitive” signal processor (CSP)) that takes an input signal containing a mixture of pulse waveforms over a very large (e.g., >30 GHz) bandwidth and denoises the input signal" teaches a cognitive signal processor (CSP) for denoising a signal), the method comprising:
Producing, using a reservoir connectivity matrix, a plurality of reservoir state values based on the signal (Fig. 4; Fig. 6; Col. 2, lines 41-46: "This disclosure is directed to a cognitive signal processor (CSP) for signal denoising. In operation, the CSP receives a noisy signal as a time-series of data points from a mixture of both noise and one or more desired waveform signals. The noisy signal is linearly mapped to reservoir states of a dynamical reservoir" teaches that the dynamic reservoir (reservoir computer) produces reservoir states based on the signal. Col. 3, lines 14-15: "Further, the dynamical reservoir includes a connectivity matrix having a block diagonal structure" teaches the dynamic reservoir (reservoir computer) including a connectivity matrix (reservoir connectivity matrix));
collecting the plurality of reservoir state values into a historical record (Fig. 4; Fig. 6; Col. 12, lines 39-52: "As shown in FIG. 4, the dynamic reservoir 400 according to the various embodiments of the present invention applies a delay embedding 402 to the reservoir states to provide a time history of reservoir dynamics. As shown, the 402 delay-embedding is applied to each of the reservoir states instead of to the input signal 404. This provides three key benefits. First, time delays and adaptation are only required at the output of the reservoir, rather than at the input. Second, having a temporal record of the states provides more useful information for signal analysis than a temporal record of the raw signal input. Third when combined with the designed reservoir states, delay-embedded states enable each state to be denoised separately, which can be used to generate a denoised spectrogram of the input signal" teaches that the delay embedding component collects the reservoir states from the reservoir computer into a historical record);
computing a plurality of reservoir state value weights based at least in part on the historical record to produce a plurality of output values (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) based in part on the historical record from the delay embedding to produce outputs), and
outputting the plurality of output values (Fig. 6; Col. 14, lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the output layers 604 (output computer) outputs a plurality of outputs).
Petre et al. does not appear to explicitly teach the reservoir connectivity matrix having a block-diagonal form, wherein each block of the reservoir connectivity matrix is of size 2 x 2 and corresponds to a single pole infinite impulse response (IR) filter; wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor.
However, Smith et al. teaches the reservoir connectivity matrix having a block-diagonal form, wherein each block of the reservoir connectivity matrix is of size 2 x 2 and corresponds to a single pole infinite impulse response (IR) filter (Fig. 4; [0063]: "the reservoir state transition matrix A is constructed such that it is in a 2×2 block diagonal form. Each 2×2 block in the state matrix A corresponds to a single pole Infinite Impulse Response (IIR) filter" teaches a matrix A (reservoir connectivity matrix) of the reservoir computer having a 2×2 block diagonal form, with each block corresponding to an IIR filter. [0059]: "Where A is the reservoir connectivity matrix that determines the filter pole locations" teaches that the matrix A is the reservoir connectivity matrix).
Petre et al. and Smith et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the reservoir connectivity matrix having a block-diagonal form, wherein each block of the reservoir connectivity matrix is of size 2 x 2 and corresponds to a single pole infinite impulse response (IR) filter as taught by Smith et al. to the disclosed invention of Petre et al.
One of ordinary skill in the art would have been motivated to make this modification for the reservoir to be "optimized for signal de-noising and efficient implementation in hardware" (Smith et al. [0014]).
Petre et al. in view of Smith et al. does not appear to explicitly teach wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor.
However, Matic et al. teaches wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the reservoir computer 600 is an adaptable nonlinear state space filter, wherein the states and outputs are iteratively updated (e.g. calculated) at sample times driven by a clock (e.g. over multiple clock cycles) for weight adaptation for adapting/updating output layer weights (reservoir state weight values) for the signal processing system).
Petre et al., Smith et al., and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor as taught by Matic et al. to the disclosed invention of Petre et al. in view of Smith et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 9,
Petre et al. in view of Smith et al. and further in view of Matic et al. teaches the method of claim 8.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights that are updated over the multiple clock cycles by converting ordinary differential equations (ODE) of an output layer weight update equation to delay differential equations (DDE) (Fig. 4; Fig. 6; (86-101) Col. 14, line 23 - Col. 15, line 58: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise … To perform short-time prediction of the input signal, the system of the present disclosure uses the online gradient descent algorithm 602. The idea is to enforce exact prediction of the current time point that is used in the delay embedding. The predicted input value at time (t+τ) is calculated from the current value the of the output weights (ck(t), d(t)) and the current and past values of the states (x) and the input (u) … The ODEs for the dynamic reservoir and the weight adaptation system can be implemented directly in analog hardware. To implement the above ODEs in software or efficient digital hardware (e.g., field-programmable gate arrays (FPGAs) or custom digital application-specific integrated circuits (ASICs)), the update equations must be discretized … To implement the process of the present disclosure in software or digital hardware, the ODEs are converted to delay difference equations (DDEs)" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) that are adapted/updated by converting ODEs of the output weight update equation to delay difference equations (DDEs)).
Regarding Claim 10,
Petre et al. in view of Smith et al. and further in view of Matic et al. teaches the method of claim 9.
In addition, Matic et al. further teaches further comprising computing a representation for a next set of weights over the multiple clock cycles (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the output weights (reservoir state weight values) are calculated at sample times driven by a clock (e.g. over multiple clock cycles) for adapting/updating output layer weights (computing next set of weights)).
Petre et al., Smith et al., and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate further comprising computing a representation for a next set of weights over the multiple clock cycles as taught by Matic et al. to the disclosed invention of Petre et al. in view of Smith et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 11,
Petre et al. in view of Smith et al. and further in view of Matic et al. teaches the method of claim 8.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights and further comprising computing a final output using multiplication of the output layer weights with a history of state results (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) to produce outputs. Fig. 6; Fig. 8; Col. 17, lines 36-47: "The reservoir state vector x(t) is then split into individual elements 800 x1(t), . . . , xN(t), and for each reservoir state element 800 xi(t), a time history of its dynamics is created by applying a length-K delay embedding. The delay embedded reservoir state elements 801 xi(t), xi(t−τi), . . . , xi(t−Kτi) are multiplied by tunable output weights 802 Ci1, . . . , Ci(K+1), summed together and delayed by time delay 803 τSK to obtain denoised reservoir state element 804
x
~
i(t). The denoised reservoir state elements are them summed together, and delayed by time delay 805 τSN to obtain the denoised output signal 806 y(t)" teaches that a final output is computed by multiplying a time history of reservoir state results from the delay embedding with the output weights).
Regarding Claim 12,
Petre et al. in view of Smith et al. in view of Matic et al. teaches the method of claim 8.
In addition, Matic et al. further teaches wherein an output delay is defined as a maximum of feedforward and feedback delays (Fig. 1; Fig. 4; Col. 5, lines 12-14: "As disclosed, the HSC 108 can: tolerate realistic hardware constraints, such as feedback loop delay and delays in the feedforward paths" teaches that the system tolerates both feedforward and feedback delays. Fig. 4; Fig. 7B; Col. 9, line 59 - Col. 10, line 19: " As such, in FIG. 7B, a system diagram is shown of an example of an implementation of the discretized DDE output equation for y(t) in accordance with the present disclosure … Again, the feedback delay value τ 808 is equal to the sampling period Δt 806 multiplied by the number of delay samples ne, where the feedback delay value τ 808 is the time window to be processed by the system. … In this example, it is assumed that the input sample rate (i.e., the inverse of the sampling period Δt 706 or 806) is equal to the clock speed of the digital processor. The output signal y(t) 800 is then determined from the updated state values xi and the most current input sample ui. Arbitrary feedforward delay values can be incorporated into the output update equation since there is no feedback connection in this part of the circuit. As such, the design can tolerate arbitrary feedforward and feedback delays" teaches that the delay for the output is based on is based on the greater (maximum) of the feedforward and feedback delays).
Petre et al., Smith et al., and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein an output delay is defined as a maximum of feedforward and feedback delays as taught by Matic et al. to the disclosed invention of Petre et al. in view of Smith et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 15,
Petre et al. teaches a computer program product, comprising a computer usable medium having a computer readable program code embodied therein, the computer readable program code adapted to be executed by a cognitive signal processor to implement a method of denoising a signal (Col. 3, lines 21-30: "the present invention also includes a computer program product and a computer implemented method. The computer program product includes computer-readable instructions stored on a non-transitory computer-readable medium that are executable by a computer having one or more processors, such that upon execution of the instructions, the one or more processors perform the operations listed herein. Alternatively, the computer implemented method includes an act of causing a computer to execute such instructions and perform the resulting operations" teaches a computer program product comprising a non-transitory computer-readable medium having computer-readable instructions stored for executing operations (method) of the embodiment. Fig. 6; Col. 6, lines 38-42: "This disclosure provides a system for signal processing (or otherwise referred to as a “cognitive” signal processor (CSP)) that takes an input signal containing a mixture of pulse waveforms over a very large (e.g., >30 GHz) bandwidth and denoises the input signal" teaches a cognitive signal processor (CSP) for denoising a signal), the method comprising:
Producing, using a reservoir connectivity matrix, a plurality of reservoir state values based on the signal (Fig. 4; Fig. 6; Col. 2, lines 41-46: "This disclosure is directed to a cognitive signal processor (CSP) for signal denoising. In operation, the CSP receives a noisy signal as a time-series of data points from a mixture of both noise and one or more desired waveform signals. The noisy signal is linearly mapped to reservoir states of a dynamical reservoir" teaches that the dynamic reservoir (reservoir computer) produces reservoir states based on the signal. Col. 3, lines 14-15: "Further, the dynamical reservoir includes a connectivity matrix having a block diagonal structure" teaches the dynamic reservoir (reservoir computer) including a connectivity matrix (reservoir connectivity matrix));
collecting the plurality of reservoir state values into a historical record (Fig. 4; Fig. 6; Col. 12, lines 39-52: "As shown in FIG. 4, the dynamic reservoir 400 according to the various embodiments of the present invention applies a delay embedding 402 to the reservoir states to provide a time history of reservoir dynamics. As shown, the 402 delay-embedding is applied to each of the reservoir states instead of to the input signal 404. This provides three key benefits. First, time delays and adaptation are only required at the output of the reservoir, rather than at the input. Second, having a temporal record of the states provides more useful information for signal analysis than a temporal record of the raw signal input. Third when combined with the designed reservoir states, delay-embedded states enable each state to be denoised separately, which can be used to generate a denoised spectrogram of the input signal" teaches that the delay embedding component collects the reservoir states from the reservoir computer into a historical record);
computing a plurality of reservoir state value weights based at least in part on the historical record to produce a plurality of output values (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) based in part on the historical record from the delay embedding to produce outputs), and
outputting the plurality of output values (Fig. 6; Col. 14, lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the output layers 604 (output computer) outputs a plurality of outputs).
Petre et al. does not appear to explicitly teach the reservoir connectivity matrix having a block-diagonal form, wherein each block of the reservoir connectivity matrix is of size 2 x 2 and corresponds to a single pole infinite impulse response (IR) filter; wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for a cognitive signal processor system.
However, Smith et al. teaches the reservoir connectivity matrix having a block-diagonal form, wherein each block of the reservoir connectivity matrix is of size 2 x 2 and corresponds to a single pole infinite impulse response (IR) filter (Fig. 4; [0063]: "the reservoir state transition matrix A is constructed such that it is in a 2×2 block diagonal form. Each 2×2 block in the state matrix A corresponds to a single pole Infinite Impulse Response (IIR) filter" teaches a matrix A (reservoir connectivity matrix) of the reservoir computer having a 2×2 block diagonal form, with each block corresponding to an IIR filter. [0059]: "Where A is the reservoir connectivity matrix that determines the filter pole locations" teaches that the matrix A is the reservoir connectivity matrix).
Petre et al. and Smith et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the reservoir connectivity matrix having a block-diagonal form, wherein each block of the reservoir connectivity matrix is of size 2 x 2 and corresponds to a single pole infinite impulse response (IR) filter as taught by Smith et al. to the disclosed invention of Petre et al.
One of ordinary skill in the art would have been motivated to make this modification for the reservoir to be "optimized for signal de-noising and efficient implementation in hardware" (Smith et al. [0014]).
Petre et al. in view of Smith et al. does not appear to explicitly teach wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for a cognitive signal processor system.
However, Matic et al. teaches wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for a cognitive signal processor system (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the reservoir computer 600 is an adaptable nonlinear state space filter, wherein the states and outputs are iteratively updated (e.g. calculated) at sample times driven by a clock (e.g. over multiple clock cycles) for weight adaptation for adapting/updating output layer weights (reservoir state weight values) for the signal processing system).
Petre et al., Smith et al., and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for a cognitive signal processor system as taught by Matic et al. to the disclosed invention of Petre et al. in view of Smith et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 16,
Petre et al. in view of Smith et al. and further in view of Matic et al. teaches the computer program product of claim 15.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights that are updated over the multiple clock cycles by converting ordinary differential equations (ODE) of an output layer weight update equation to delay differential equations (DDE) (Fig. 4; Fig. 6; Col. 14, line 23 - Col. 15, line 58: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise … To perform short-time prediction of the input signal, the system of the present disclosure uses the online gradient descent algorithm 602. The idea is to enforce exact prediction of the current time point that is used in the delay embedding. The predicted input value at time (t+τ) is calculated from the current value the of the output weights (ck(t), d(t)) and the current and past values of the states (x) and the input (u) … The ODEs for the dynamic reservoir and the weight adaptation system can be implemented directly in analog hardware. To implement the above ODEs in software or efficient digital hardware (e.g., field-programmable gate arrays (FPGAs) or custom digital application-specific integrated circuits (ASICs)), the update equations must be discretized … To implement the process of the present disclosure in software or digital hardware, the ODEs are converted to delay difference equations (DDEs)" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) that are adapted/updated by converting ODEs of the output weight update equation to delay difference equations (DDEs)).
Regarding Claim 17,
Petre et al. in view of Smith et al. and further in view of Matic et al. teaches the computer program product of claim 16.
In addition, Matic et al. further teaches wherein the method further comprises computing a representation for a next set of weights over the multiple clock cycles (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the output weights (reservoir state weight values) are calculated at sample times driven by a clock (e.g. over multiple clock cycles) for adapting/updating output layer weights (computing next set of weights)).
Petre et al., Smith et al., and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the method further comprises computing a representation for a next set of weights over the multiple clock cycles as taught by Matic et al. to the disclosed invention of Petre et al. in view of Smith et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 18,
Petre et al. in view of Smith et al. and further in view of Matic et al. teaches the computer program product of claim 15.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights and the method further comprises computing a final output using multiplication of the output layer weights with a history of state results (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) to produce outputs. Fig. 6; Fig. 8; Col. 17, lines 36-47: "The reservoir state vector x(t) is then split into individual elements 800 x1(t), . . . , xN(t), and for each reservoir state element 800 xi(t), a time history of its dynamics is created by applying a length-K delay embedding. The delay embedded reservoir state elements 801 xi(t), xi(t−τi), . . . , xi(t−Kτi) are multiplied by tunable output weights 802 Ci1, . . . , Ci(K+1), summed together and delayed by time delay 803 τSK to obtain denoised reservoir state element 804
x
~
i(t). The denoised reservoir state elements are them summed together, and delayed by time delay 805 τSN to obtain the denoised output signal 806 y(t)" teaches that a final output is computed by multiplying a time history of reservoir state results from the delay embedding with the output weights).
Allowable Subject Matter
Claims 6-7, 13-14, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments, filed 04/24/2026, with respect to the non-statutory subject matter rejections under 35 U.S.C. 101 have been fully considered and are persuasive. Therefore, the 35 U.S.C. 101 non-statutory subject matter rejections have been withdrawn.
Applicant’s arguments, filed 04/24/2026, with respect to the abstract idea rejections under 35 U.S.C. 101 have been fully considered and are persuasive. Therefore, the 35 U.S.C. 101 abstract idea rejections have been withdrawn.
Applicant’s arguments, filed 04/24/2026, with respect to the 35 U.S.C. 103 prior art rejections have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN J HALES whose telephone number is (571)272-0878. The examiner can normally be reached M-F 9:00am - 5:00pm.
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/BRIAN J HALES/Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125
Prosecution Insights