DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to amendments and remarks filed on 12/04/2025. In the current amendments, claims 1-8, 14-15, and 20 are amended. Claims 1-20 are pending and have been examined.
In response to amendments and remarks filed on 12/04/2025, 35 U.S.C. 112(f) claim interpretation, the 35 U.S.C. 112(a) rejections, and the 35 U.S.C. 112(b) rejections made in the previous office action are withdrawn.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 15-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claims could be considered signal per se.
Independent claim 15 recites “A computer program product, comprising a computer usable medium having a computer readable program code embodied therein.” The broadest reasonable interpretation of a claim that recites "computer usable medium," in view of the present specification, covers forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer usable medium, particularly when the specification is silent. See MPEP 2111.01. When the broadest reasonable interpretation of a claim covers a signal per se, the claim must be rejected under 35 U.S.C. § 101 as covering non-statutory subject matter. See In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007) (transitory embodiments are not directed to statutory subject matter) and Interim Examination Instructions for Evaluating Subject Matter Eligibility Under 35 U.S.C. § 101, Aug. 24, 2009; p. 2. 1351 Off. Gaz. Pat. Off. 212 (2010). Under broadest reasonable interpretation, "computer usable medium" recited in claim 15 encompasses a transitory, propagating signal, which is not a process, machine, manufacture, or composition of matter. Nuijten, 500 F.3d at 1357. The claim "covers material not found in any of the four statutory categories [and thus] falls outside the plainly expressed scope of § 101." Id. at 1354. A recommended amendment is to recite “non-transitory computer usable medium” (emphasis added). Dependent claims 16-20 are rejected based on same rationale as claim 15.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding Claim 1,
Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 1 is directed to a processor, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“produce a plurality of reservoir state values”
“compute a plurality of reservoir state value weights to produce a plurality of output values, wherein the plurality of reservoir state value weights are computed over multiple clock cycles, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) and mathematical concepts (mathematical relationships, mathematical formulas or equations, mathematical calculations) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass producing a plurality of reservoir state values (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can produce reservoir state values); and computing reservoir state value weights to produce output values, the reservoir state weight values being computed over multiple clock cycles using pipelining with intermediate values stored (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can compute reservoir state value weights to produce output values in pipelined fashion over multiple clock cycles with stored intermediate values).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“a reservoir computer”
“a delay embedding component”
“a weight adaptation component”
“an output layer computer”
“an output of the reservoir computer is communicatively coupled to an input of the reservoir computer and to the delay embedding component”
“the reservoir computer”
“an input of the delay embedding component communicatively coupled to an output of the reservoir computer and an output of the delay embedding component communicatively coupled to an input of the weight adaptation component and to an input of the output layer computer”
“an output of the weight adaptation component communicatively coupled to an input of the weight adaptation component and to an input of the output layer computer”
“the weight adaptation component”
“a clock for the denoising cognitive signal processor system”
“an input of the output layer computer communicatively coupled to an output of the delay embedding component, an input of the output layer computer communicatively coupled to an output of the weight adaptation component, and an output of the output layer computer communicatively coupled to an input to the weight adaptation component”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). The limitations:
“the delay embedding component configured to collect the plurality of reservoir state values”
“the output layer computer being configured to output the plurality of output values”
As drafted, are additional elements that correspond to insignificant extra-solution activity. In particular, the additional elements are merely directed towards mere data gathering. See MPEP 2106.05(g). Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe computers, components, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collect …” and “output …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 2,
Claim 2 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 2 is directed to a processor, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the plurality of reservoir state value weights define output layer weights that are updated over the multiple clock cycles by converting ordinary differential equations (ODE) of an output layer weight update equation to delay differential equations (DDE)”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass converting ODEs of an output layer weight update equation to DDEs (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can converts ODEs to DDEs for an output layer weight update equation).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 1 of computers, components, and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collect …” and “output …” limitations of claim 1 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe computers, components, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collect …” and “output …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 3,
Claim 3 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 3 is directed to a processor, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein a representation for a next set of weights is computed over the multiple clock cycles”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass computing a representation for a next set of weights over multiple clock cycles (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can compute a representation for a next set of weights).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 2 of computers, components, and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collect …” and “output …” limitations of claim 2 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe computers, components, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collect …” and “output …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 4,
Claim 4 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 4 is directed to a processor, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the plurality of reservoir state value weights define output layer weights and a final output is computed using multiplication of the output layer weights with a history of state results”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass computing a final output by multiplying output layer weights defined by the reservoir state value weights with a history of state results (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can multiply output layer weights with a history of state results to compute a final output).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 1 of computers, components, and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collect …” and “output …” limitations of claim 1 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe computers, components, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collect …” and “output …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 5,
Claim 5 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 5 is directed to a processor, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein an output delay is defined as a maximum of feedforward and feedback delays”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass defining an output delay as the maximum of feedforward and feedback delays (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can define a maximum of feedforward and feedback delays as an output delay).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 1 of computers, components, and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collect …” and “output …” limitations of claim 1 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe computers, components, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collect …” and “output …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 6,
Claim 6 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 6 is directed to a processor, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the plurality of reservoir state value weights define output layer weights and the output layer weights are minimized using an objective function including a parameter that balances an importance of a signal prediction error versus a magnitude of the output layer weights”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass minimizing output layers weights defined by the reservoir state value weights by using an objective function including a parameter that balances an importance of signal prediction errors versus a magnitude of the output layer weights (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can use an objective function containing a parameter that balances importance of prediction errors with magnitude of the output layer weights in order to minimize the output layer weights).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 1 of computers, components, and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collect …” and “output …” limitations of claim 1 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe computers, components, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collect …” and “output …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 7,
Claim 7 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 7 is directed to a processor, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the output layer weights are obtained using delays that are based on hardware constraints and using a prediction length that is a user-defined delay value”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass obtaining output layer weights using delays based on hardware constraints and a user-defined prediction length delay value (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can use hardware constraint based delays and a prediction length that is a user-defined delay value to obtain the output layer weights).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 6 of computers, components, and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collect …” and “output …” limitations of claim 6 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe computers, components, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collect …” and “output …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 8,
Claim 8 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 8 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“producing a plurality of reservoir state values based on the signal”
“computing a plurality of reservoir state value weights based at least in part on the historical record to produce a plurality of output values, wherein the plurality of reservoir state value weights are computed over multiple clock cycles”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) and mathematical concepts (mathematical relationships, mathematical formulas or equations, mathematical calculations) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass producing a plurality of reservoir state values (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can produce reservoir state values); and computing reservoir state value weights to produce output values, the reservoir state weight values being computed over multiple clock cycles (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can compute reservoir state value weights to produce output values).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“a cognitive signal processor”
“a clock for the cognitive signal processor system”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). The limitations:
“collecting the plurality of reservoir state values into a historical record”
“outputting the plurality of output values”
As drafted, are additional elements that correspond to insignificant extra-solution activity. In particular, the additional elements are merely directed towards mere data gathering. See MPEP 2106.05(g). Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a cognitive signal processor and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 9,
Claim 9 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 9 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the plurality of reservoir state value weights define output layer weights that are updated over the multiple clock cycles by converting ordinary differential equations (ODE) of an output layer weight update equation to delay differential equations (DDE)”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass converting ODEs of an output layer weight update equation to DDEs (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can converts ODEs to DDEs for an output layer weight update equation).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 8 of a cognitive signal processor and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collecting …” and “outputting …” limitations of claim 8 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a cognitive signal processor and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 10,
Claim 10 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 10 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“further comprising computing a representation for a next set of weights over the multiple clock cycles”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass computing a representation for a next set of weights over multiple clock cycles (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can compute a representation for a next set of weights).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 9 of a cognitive signal processor and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collecting …” and “outputting …” limitations of claim 9 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a cognitive signal processor and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 11,
Claim 11 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 11 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the plurality of reservoir state value weights define output layer weights and further comprising computing a final output using multiplication of the output layer weights with a history of state results”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass computing a final output by multiplying output layer weights defined by the reservoir state value weights with a history of state results (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can multiply output layer weights with a history of state results to compute a final output).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 8 of a cognitive signal processor and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collecting …” and “outputting …” limitations of claim 8 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a cognitive signal processor and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 12,
Claim 12 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 12 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein an output delay is defined as a maximum of feedforward and feedback delays”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass defining an output delay as the maximum of feedforward and feedback delays (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can define a maximum of feedforward and feedback delays as an output delay).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 8 of a cognitive signal processor and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collecting …” and “outputting …” limitations of claim 8 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a cognitive signal processor and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 13,
Claim 13 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 13 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the plurality of reservoir state value weights define output layer weights and further comprising minimizing the output layer weights using an objective function including a parameter that balances an importance of a signal prediction error versus a magnitude of the output layer weights”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass minimizing output layers weights defined by the reservoir state value weights by using an objective function including a parameter that balances an importance of signal prediction errors versus a magnitude of the output layer weights (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can use an objective function containing a parameter that balances importance of prediction errors with magnitude of the output layer weights in order to minimize the output layer weights).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 8 of a cognitive signal processor and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collecting …” and “outputting …” limitations of claim 8 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a cognitive signal processor and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 14,
Claim 14 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 14 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the output layer weights are obtained using delays that are based on hardware constraints and using a prediction length that is a user-defined delay value”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass obtaining output layer weights using delays based on hardware constraints and a user-defined prediction length delay value (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can use hardware constraint based delays and a prediction length that is a user-defined delay value to obtain the output layer weights).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 13 of a cognitive signal processor and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collecting …” and “outputting …” limitations of claim 13 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a cognitive signal processor and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 15,
Claim 15 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 15 is directed to a computer program product, comprising a computer usable medium, which is directed to an article of manufacture, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“producing a plurality of reservoir state values based on the signal”
“computing a plurality of reservoir state value weights based at least in part on the historical record to produce a plurality of output values, wherein the plurality of reservoir state value weights are computed over multiple clock cycles”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) and mathematical concepts (mathematical relationships, mathematical formulas or equations, mathematical calculations) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass producing a plurality of reservoir state values (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can produce reservoir state values); and computing reservoir state value weights to produce output values, the reservoir state weight values being computed over multiple clock cycles (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can compute reservoir state value weights to produce output values).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“a computer usable medium having a computer readable program code embodied therein”
“a cognitive signal processor”
“a clock for a cognitive signal processor system”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). The limitations:
“collecting the plurality of reservoir state values into a historical record”
“outputting the plurality of output values”
As drafted, are additional elements that correspond to insignificant extra-solution activity. In particular, the additional elements are merely directed towards mere data gathering. See MPEP 2106.05(g). Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a computer usable medium, cognitive signal processor, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 16,
Claim 16 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 16 is directed to a computer program product, comprising a computer usable medium, which is directed to an article of manufacture, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the plurality of reservoir state value weights define output layer weights that are updated over the multiple clock cycles by converting ordinary differential equations (ODE) of an output layer weight update equation to delay differential equations (DDE)”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass converting ODEs of an output layer weight update equation to DDEs (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can converts ODEs to DDEs for an output layer weight update equation).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 15 of a computer usable medium, cognitive signal processor, and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collecting …” and “outputting …” limitations of claim 15 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a computer usable medium, cognitive signal processor, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 17,
Claim 17 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 17 is directed to a computer program product, comprising a computer usable medium, which is directed to an article of manufacture, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the method further comprises computing a representation for a next set of weights over the multiple clock cycles”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass computing a representation for a next set of weights over multiple clock cycles (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can compute a representation for a next set of weights).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 16 of a computer usable medium, cognitive signal processor, and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collecting …” and “outputting …” limitations of claim 16 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a computer usable medium, cognitive signal processor, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 18,
Claim 18 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 18 is directed to a computer program product, comprising a computer usable medium, which is directed to an article of manufacture, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the plurality of reservoir state value weights define output layer weights and the method further comprises computing a final output using multiplication of the output layer weights with a history of state results”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass computing a final output by multiplying output layer weights defined by the reservoir state value weights with a history of state results (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can multiply output layer weights with a history of state results to compute a final output).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 15 of a computer usable medium, cognitive signal processor, and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collecting …” and “outputting …” limitations of claim 15 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a computer usable medium, cognitive signal processor, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 19,
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 19 is directed to a computer program product, comprising a computer usable medium, which is directed to an article of manufacture, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the plurality of reservoir state value weights define output layer weights and the method further comprises minimizing the output layer weights using an objective function including a parameter that balances an importance of a signal prediction error versus a magnitude of the output layer weights”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass minimizing output layers weights defined by the reservoir state value weights by using an objective function including a parameter that balances an importance of signal prediction errors versus a magnitude of the output layer weights (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can use an objective function containing a parameter that balances importance of prediction errors with magnitude of the output layer weights in order to minimize the output layer weights).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 15 of a computer usable medium, cognitive signal processor, and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collecting …” and “outputting …” limitations of claim 15 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a computer usable medium, cognitive signal processor, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 20,
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 20 is directed to a computer program product, comprising a computer usable medium, which is directed to an article of manufacture, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the output layer weights are obtained using delays that are based on hardware constraints and using a prediction length that is a user-defined delay value”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass obtaining output layer weights using delays based on hardware constraints and a user-defined prediction length delay value (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can use hardware constraint based delays and a prediction length that is a user-defined delay value to obtain the output layer weights).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The recitation of additional elements in claim 19 of a computer usable medium, cognitive signal processor, and a clock are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. Furthermore, the “collecting …” and “outputting …” limitations of claim 19 are additional elements that correspond to insignificant extra-solution activity as mere data gathering. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a computer usable medium, cognitive signal processor, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collecting …” and “outputting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 8-12, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Petre et al. (US 10,404,299 B1) in view of Petre, Matic, and Virbila (US 10,211,856 B1); hereinafter Matic et al.
Regarding Claim 1,
Petre et al. teaches a cognitive signal processor comprising: a reservoir computer; a delay embedding component; a weight adaptation component; and an output layer computer (Fig. 6; Col. 6, lines 38-42: "This disclosure provides a system for signal processing (or otherwise referred to as a “cognitive” signal processor (CSP)) that takes an input signal containing a mixture of pulse waveforms over a very large (e.g., >30 GHz) bandwidth and denoises the input signal" teaches a cognitive signal processor (CSP). Fig. 6; Col. 6, lines 43-59: "The CSP includes three primary components. The first component is a reservoir computer (RC), which is the cognitive-inspired aspect of the CSP. The dynamic reservoir computer maps an input signal to a high-dimensional dynamical system known as the reservoir. The reservoir connectivity weights are optimized for the task of signal denoising. The second component is a delay embedding that creates a finite temporal record of the values of the reservoir states. The third component is a weight adaptation module that adapts the output of the reservoir via gradient descent to produce a prediction of the input signal a small time-step in the future. Since the noise in the input signal is inherently random and unpredictable, the predicted input signal will be free of noise (i.e., denoised signal). The error between the predicted input signal and actual input is used by the weight adaptation module to further tune the output weights of the reservoir in an iterative process" teaches that the CSP comprises a dynamic reservoir (reservoir computer), a delay embedding component, and a weight adaptation module (component). Fig. 6; Col. 14, lines 20-21: "The model shows the dynamic reservoir 400 with fixed connections (A) and adaptable output layers attached to it" teaches that the CSP comprises adaptable output layers (output layer computer)),
wherein, an output of the reservoir computer is communicatively coupled to an input of the reservoir computer and to the delay embedding component, the reservoir computer being configured to produce a plurality of reservoir state values (Fig. 4; Fig. 6; Col. 12, lines 39-52: "As shown in FIG. 4, the dynamic reservoir 400 according to the various embodiments of the present invention applies a delay embedding 402 to the reservoir states to provide a time history of reservoir dynamics. As shown, the 402 delay-embedding is applied to each of the reservoir states instead of to the input signal 404. This provides three key benefits. First, time delays and adaptation are only required at the output of the reservoir, rather than at the input. Second, having a temporal record of the states provides more useful information for signal analysis than a temporal record of the raw signal input. Third when combined with the designed reservoir states, delay-embedded states enable each state to be denoised separately, which can be used to generate a denoised spectrogram of the input signal" teaches that the reservoir computer output is coupled to the reservoir computer input and to the delay component. Fig. 4; Fig. 6; Col. 2, lines 41-46: "This disclosure provides a system for signal processing (or otherwise referred to as a “cognitive” signal processor (CSP)) that takes an input signal containing a mixture of pulse waveforms over a very large (e.g., >30 GHz) bandwidth and denoises the input signal" teaches that the dynamic reservoir (reservoir computer) produces reservoir states);
an input of the delay embedding component communicatively coupled to an output of the reservoir computer and an output of the delay embedding component communicatively coupled to an input of the weight adaptation component and to an input of the output layer computer, the delay embedding component configured to collect the plurality of reservoir state values (Fig. 4; Fig. 6; Col. 12, lines 39-52: "As shown in FIG. 4, the dynamic reservoir 400 according to the various embodiments of the present invention applies a delay embedding 402 to the reservoir states to provide a time history of reservoir dynamics. As shown, the 402 delay-embedding is applied to each of the reservoir states instead of to the input signal 404. This provides three key benefits. First, time delays and adaptation are only required at the output of the reservoir, rather than at the input. Second, having a temporal record of the states provides more useful information for signal analysis than a temporal record of the raw signal input. Third when combined with the designed reservoir states, delay-embedded states enable each state to be denoised separately, which can be used to generate a denoised spectrogram of the input signal" teaches that the delay embedding component input is coupled to the reservoir computer output, and that the delay embedding component collects the reservoir states. Fig. 6; Col. 14, lines 26-30: "That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the delay embedding of states component (delay embedding component) output is communicatively coupled to the input of the gradient learning algorithm 602 (weight adaptation component) and to the input of the output layers 604 (output computer));
an output of the weight adaptation component communicatively coupled to an input of the weight adaptation component and to an input of the output layer computer, the weight adaptation component configured to compute a plurality of reservoir state value weights to produce a plurality of output values (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the output of the gradient descent algorithm 602 (weight adaptation component) is communicatively coupled to the input of the gradient descent algorithm 602 (weight adaptation component) and to the input of the output layers 604 (output computer), and that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) to produce outputs), and
an input of the output layer computer communicatively coupled to an output of the delay embedding component, an input of the output layer computer communicatively coupled to an output of the weight adaptation component, and an output of the output layer computer communicatively coupled to an input to the weight adaptation component, the output layer computer being configured to output the plurality of output values (Fig. 6; Col. 14, lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the input of the output layers 604 (output computer) is communicatively coupled to the output of the delay embedding of states component (delay embedding component) and the output of the gradient learning algorithm 602 (weight adaptation component), the output of the output layers 604 (output computer) is communicatively coupled to an input of the gradient learning algorithm 602 (weight adaptation component), and that the output layers 604 (output computer) outputs a plurality of outputs).
Petre et al. does not appear to explicitly teach wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored.
However, Matic et al. teaches wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the reservoir computer 600 is an adaptable nonlinear state space filter, wherein the states and outputs are iteratively updated (e.g. calculated) at sample times driven by a clock (e.g. over multiple clock cycles) for weight adaptation for adapting/updating output layer weights (reservoir state weight values) for the signal processing system. Fig. 1; Fig. 6; Col. 5, lines 10-30: "the HSC 108 can: tolerate realistic hardware constraints, such as feedback loop delay and delays in the feedforward paths; enable massively parallel implementations of high quality IIR filters; … the HSC 108 includes a parallel neuromorphic processor architecture that is configured to perform the neuromorphic processing. In this example, the parallel neuromorphic processor architecture is a reservoir computer that may be an echo state network or liquid-state machine. The reservoir computer includes a reservoir and a plurality of trainable readouts. In general, the reservoir computer is an adaptable state space filter having a plurality of reservoir connectivity matrix weights, plurality of input layer weights, and a plurality of output layer weights which will be described in greater detail later" teaches that the reservoir computer is an adaptable state space filter for implementing IIR filters. Fig. 1; Fig. 6; Col. 6, lines 40-49: "The HSC 108 utilizes an ordinary differential equation to delayed transformation to map the IIR filtering process onto a massively parallel neuromorphic processor architecture. As a result, this IIR filtering design can tolerate realistic hardware constraints, such as, for example, feedback loop delay and delays in the feedforward paths. Additionally, this IIR filtering design also allows the utilization of an arbitrary number of pipeline stages in each multiplier and summing junction in the implemented hardware IC" teaches that calculations for the IIR filtering performed by the reservoir computer can be performed over multiple pipeline stages (e.g. the weight update/adaptation for the output layer weights driven by a clock are performed using pipelining)).
Petre et al. and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored as taught by Matic et al. to the disclosed invention of Petre et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 2,
Petre et al. in view of Matic et al. teaches the cognitive signal processor of claim 1.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights that are updated over the multiple clock cycles by converting ordinary differential equations (ODE) of an output layer weight update equation to delay differential equations (DDE) (Fig. 4; Fig. 6; (86-101) Col. 14, line 23 - Col. 15, line 58: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise … To perform short-time prediction of the input signal, the system of the present disclosure uses the online gradient descent algorithm 602. The idea is to enforce exact prediction of the current time point that is used in the delay embedding. The predicted input value at time (t+τ) is calculated from the current value the of the output weights (ck(t), d(t)) and the current and past values of the states (x) and the input (u) … The ODEs for the dynamic reservoir and the weight adaptation system can be implemented directly in analog hardware. To implement the above ODEs in software or efficient digital hardware (e.g., field-programmable gate arrays (FPGAs) or custom digital application-specific integrated circuits (ASICs)), the update equations must be discretized … To implement the process of the present disclosure in software or digital hardware, the ODEs are converted to delay difference equations (DDEs)" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) that are adapted/updated by converting ODEs of the output weight update equation to delay difference equations (DDEs)).
Regarding Claim 3,
Petre et al. in view of Matic et al. teaches the cognitive signal processor of claim 2.
In addition, Matic et al. further teaches wherein a representation for a next set of weights is computed over the multiple clock cycles (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the output weights (reservoir state weight values) are calculated at sample times driven by a clock (e.g. over multiple clock cycles) for adapting/updating output layer weights (computing next set of weights)).
Petre et al. and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein a representation for a next set of weights is computed over the multiple clock cycles as taught by Matic et al. to the disclosed invention of Petre et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 4,
Petre et al. in view of Matic et al. teaches the cognitive signal processor of claim 1.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights and a final output is computed using multiplication of the output layer weights with a history of state results (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) to produce outputs. Fig. 6; Fig. 8; Col. 17, lines 36-47: "The reservoir state vector x(t) is then split into individual elements 800 x1(t), . . . , xN(t), and for each reservoir state element 800 xi(t), a time history of its dynamics is created by applying a length-K delay embedding. The delay embedded reservoir state elements 801 xi(t), xi(t−τi), . . . , xi(t−Kτi) are multiplied by tunable output weights 802 Ci1, . . . , Ci(K+1), summed together and delayed by time delay 803 τSK to obtain denoised reservoir state element 804
x
~
i(t). The denoised reservoir state elements are them summed together, and delayed by time delay 805 τSN to obtain the denoised output signal 806 y(t)" teaches that a final output is computed by multiplying a time history of reservoir state results from the delay embedding with the output weights).
Regarding Claim 5,
Petre et al. in view of Matic et al. teaches the cognitive signal processor of claim 1.
In addition, Matic et al. further teaches wherein an output delay is defined as a maximum of feedforward and feedback delays (Fig. 1; Fig. 4; Col. 5, lines 12-14: "As disclosed, the HSC 108 can: tolerate realistic hardware constraints, such as feedback loop delay and delays in the feedforward paths" teaches that the system tolerates both feedforward and feedback delays. Fig. 4; Fig. 7B; Col. 9, line 59 - Col. 10, line 19: " As such, in FIG. 7B, a system diagram is shown of an example of an implementation of the discretized DDE output equation for y(t) in accordance with the present disclosure … Again, the feedback delay value τ 808 is equal to the sampling period Δt 806 multiplied by the number of delay samples ne, where the feedback delay value τ 808 is the time window to be processed by the system. … In this example, it is assumed that the input sample rate (i.e., the inverse of the sampling period Δt 706 or 806) is equal to the clock speed of the digital processor. The output signal y(t) 800 is then determined from the updated state values xi and the most current input sample ui. Arbitrary feedforward delay values can be incorporated into the output update equation since there is no feedback connection in this part of the circuit. As such, the design can tolerate arbitrary feedforward and feedback delays" teaches that the delay for the output is based on is based on the greater (maximum) of the feedforward and feedback delays).
Petre et al. and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein an output delay is defined as a maximum of feedforward and feedback delays as taught by Matic et al. to the disclosed invention of Petre et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 8,
Petre et al. teaches a method of denoising a signal by a cognitive signal processor (Col. 3, lines 21-30: "the present invention also includes a computer program product and a computer implemented method. The computer program product includes computer-readable instructions stored on a non-transitory computer-readable medium that are executable by a computer having one or more processors, such that upon execution of the instructions, the one or more processors perform the operations listed herein. Alternatively, the computer implemented method includes an act of causing a computer to execute such instructions and perform the resulting operations" teaches a method for performing operations of the embodiment. Fig. 6; Col. 6, lines 38-42: "This disclosure provides a system for signal processing (or otherwise referred to as a “cognitive” signal processor (CSP)) that takes an input signal containing a mixture of pulse waveforms over a very large (e.g., >30 GHz) bandwidth and denoises the input signal" teaches a cognitive signal processor (CSP) for denoising a signal), the method comprising:
producing a plurality of reservoir state values based on the signal (Fig. 4; Fig. 6; Col. 2, lines 41-46: "This disclosure is directed to a cognitive signal processor (CSP) for signal denoising. In operation, the CSP receives a noisy signal as a time-series of data points from a mixture of both noise and one or more desired waveform signals. The noisy signal is linearly mapped to reservoir states of a dynamical reservoir" teaches that the dynamic reservoir (reservoir computer) produces reservoir states based on the signal);
collecting the plurality of reservoir state values into a historical record (Fig. 4; Fig. 6; Col. 12, lines 39-52: "As shown in FIG. 4, the dynamic reservoir 400 according to the various embodiments of the present invention applies a delay embedding 402 to the reservoir states to provide a time history of reservoir dynamics. As shown, the 402 delay-embedding is applied to each of the reservoir states instead of to the input signal 404. This provides three key benefits. First, time delays and adaptation are only required at the output of the reservoir, rather than at the input. Second, having a temporal record of the states provides more useful information for signal analysis than a temporal record of the raw signal input. Third when combined with the designed reservoir states, delay-embedded states enable each state to be denoised separately, which can be used to generate a denoised spectrogram of the input signal" teaches that the delay embedding component collects the reservoir states from the reservoir computer into a historical record);
computing a plurality of reservoir state value weights based at least in part on the historical record to produce a plurality of output values (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) based in part on the historical record from the delay embedding to produce outputs), and
outputting the plurality of output values (Fig. 6; Col. 14, lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the output layers 604 (output computer) outputs a plurality of outputs).
Petre et al. does not appear to explicitly teach wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor.
However, Matic et al. teaches wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the reservoir computer 600 is an adaptable nonlinear state space filter, wherein the states and outputs are iteratively updated (e.g. calculated) at sample times driven by a clock (e.g. over multiple clock cycles) for weight adaptation for adapting/updating output layer weights (reservoir state weight values) for the signal processing system).
Petre et al. and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the cognitive signal processor as taught by Matic et al. to the disclosed invention of Petre et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 9,
Petre et al. in view of Matic et al. teaches the method of claim 8.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights that are updated over the multiple clock cycles by converting ordinary differential equations (ODE) of an output layer weight update equation to delay differential equations (DDE) (Fig. 4; Fig. 6; (86-101) Col. 14, line 23 - Col. 15, line 58: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise … To perform short-time prediction of the input signal, the system of the present disclosure uses the online gradient descent algorithm 602. The idea is to enforce exact prediction of the current time point that is used in the delay embedding. The predicted input value at time (t+τ) is calculated from the current value the of the output weights (ck(t), d(t)) and the current and past values of the states (x) and the input (u) … The ODEs for the dynamic reservoir and the weight adaptation system can be implemented directly in analog hardware. To implement the above ODEs in software or efficient digital hardware (e.g., field-programmable gate arrays (FPGAs) or custom digital application-specific integrated circuits (ASICs)), the update equations must be discretized … To implement the process of the present disclosure in software or digital hardware, the ODEs are converted to delay difference equations (DDEs)" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) that are adapted/updated by converting ODEs of the output weight update equation to delay difference equations (DDEs)).
Regarding Claim 10,
Petre et al. in view of Matic et al. teaches the method of claim 9.
In addition, Matic et al. further teaches further comprising computing a representation for a next set of weights over the multiple clock cycles (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the output weights (reservoir state weight values) are calculated at sample times driven by a clock (e.g. over multiple clock cycles) for adapting/updating output layer weights (computing next set of weights)).
Petre et al. and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate further comprising computing a representation for a next set of weights over the multiple clock cycles as taught by Matic et al. to the disclosed invention of Petre et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 11,
Petre et al. in view of Matic et al. teaches the method of claim 8.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights and further comprising computing a final output using multiplication of the output layer weights with a history of state results (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) to produce outputs. Fig. 6; Fig. 8; Col. 17, lines 36-47: "The reservoir state vector x(t) is then split into individual elements 800 x1(t), . . . , xN(t), and for each reservoir state element 800 xi(t), a time history of its dynamics is created by applying a length-K delay embedding. The delay embedded reservoir state elements 801 xi(t), xi(t−τi), . . . , xi(t−Kτi) are multiplied by tunable output weights 802 Ci1, . . . , Ci(K+1), summed together and delayed by time delay 803 τSK to obtain denoised reservoir state element 804
x
~
i(t). The denoised reservoir state elements are them summed together, and delayed by time delay 805 τSN to obtain the denoised output signal 806 y(t)" teaches that a final output is computed by multiplying a time history of reservoir state results from the delay embedding with the output weights).
Regarding Claim 12,
Petre et al. in view of Matic et al. teaches the method of claim 8.
In addition, Matic et al. further teaches wherein an output delay is defined as a maximum of feedforward and feedback delays (Fig. 1; Fig. 4; Col. 5, lines 12-14: "As disclosed, the HSC 108 can: tolerate realistic hardware constraints, such as feedback loop delay and delays in the feedforward paths" teaches that the system tolerates both feedforward and feedback delays. Fig. 4; Fig. 7B; Col. 9, line 59 - Col. 10, line 19: " As such, in FIG. 7B, a system diagram is shown of an example of an implementation of the discretized DDE output equation for y(t) in accordance with the present disclosure … Again, the feedback delay value τ 808 is equal to the sampling period Δt 806 multiplied by the number of delay samples ne, where the feedback delay value τ 808 is the time window to be processed by the system. … In this example, it is assumed that the input sample rate (i.e., the inverse of the sampling period Δt 706 or 806) is equal to the clock speed of the digital processor. The output signal y(t) 800 is then determined from the updated state values xi and the most current input sample ui. Arbitrary feedforward delay values can be incorporated into the output update equation since there is no feedback connection in this part of the circuit. As such, the design can tolerate arbitrary feedforward and feedback delays" teaches that the delay for the output is based on is based on the greater (maximum) of the feedforward and feedback delays).
Petre et al. and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein an output delay is defined as a maximum of feedforward and feedback delays as taught by Matic et al. to the disclosed invention of Petre et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 15,
Petre et al. teaches a computer program product, comprising a computer usable medium having a computer readable program code embodied therein, the computer readable program code adapted to be executed by a cognitive signal processor to implement a method of denoising a signal (Col. 3, lines 21-30: "the present invention also includes a computer program product and a computer implemented method. The computer program product includes computer-readable instructions stored on a non-transitory computer-readable medium that are executable by a computer having one or more processors, such that upon execution of the instructions, the one or more processors perform the operations listed herein. Alternatively, the computer implemented method includes an act of causing a computer to execute such instructions and perform the resulting operations" teaches a computer program product comprising a non-transitory computer-readable medium having computer-readable instructions stored for executing operations (method) of the embodiment. Fig. 6; Col. 6, lines 38-42: "This disclosure provides a system for signal processing (or otherwise referred to as a “cognitive” signal processor (CSP)) that takes an input signal containing a mixture of pulse waveforms over a very large (e.g., >30 GHz) bandwidth and denoises the input signal" teaches a cognitive signal processor (CSP) for denoising a signal), the method comprising:
producing a plurality of reservoir state values based on the signal (Fig. 4; Fig. 6; Col. 2, lines 41-46: "This disclosure is directed to a cognitive signal processor (CSP) for signal denoising. In operation, the CSP receives a noisy signal as a time-series of data points from a mixture of both noise and one or more desired waveform signals. The noisy signal is linearly mapped to reservoir states of a dynamical reservoir" teaches that the dynamic reservoir (reservoir computer) produces reservoir states based on the signal);
collecting the plurality of reservoir state values into a historical record (Fig. 4; Fig. 6; Col. 12, lines 39-52: "As shown in FIG. 4, the dynamic reservoir 400 according to the various embodiments of the present invention applies a delay embedding 402 to the reservoir states to provide a time history of reservoir dynamics. As shown, the 402 delay-embedding is applied to each of the reservoir states instead of to the input signal 404. This provides three key benefits. First, time delays and adaptation are only required at the output of the reservoir, rather than at the input. Second, having a temporal record of the states provides more useful information for signal analysis than a temporal record of the raw signal input. Third when combined with the designed reservoir states, delay-embedded states enable each state to be denoised separately, which can be used to generate a denoised spectrogram of the input signal" teaches that the delay embedding component collects the reservoir states from the reservoir computer into a historical record);
computing a plurality of reservoir state value weights based at least in part on the historical record to produce a plurality of output values (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) based in part on the historical record from the delay embedding to produce outputs), and
outputting the plurality of output values (Fig. 6; Col. 14, lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the output layers 604 (output computer) outputs a plurality of outputs).
Petre et al. does not appear to explicitly teach wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for a cognitive signal processor system.
However, Matic et al. teaches wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for a cognitive signal processor system (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the reservoir computer 600 is an adaptable nonlinear state space filter, wherein the states and outputs are iteratively updated (e.g. calculated) at sample times driven by a clock (e.g. over multiple clock cycles) for weight adaptation for adapting/updating output layer weights (reservoir state weight values) for the signal processing system).
Petre et al. and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for a cognitive signal processor system as taught by Matic et al. to the disclosed invention of Petre et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 16,
Petre et al. in view of Matic et al. teaches the computer program product of claim 15.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights that are updated over the multiple clock cycles by converting ordinary differential equations (ODE) of an output layer weight update equation to delay differential equations (DDE) (Fig. 4; Fig. 6; Col. 14, line 23 - Col. 15, line 58: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise … To perform short-time prediction of the input signal, the system of the present disclosure uses the online gradient descent algorithm 602. The idea is to enforce exact prediction of the current time point that is used in the delay embedding. The predicted input value at time (t+τ) is calculated from the current value the of the output weights (ck(t), d(t)) and the current and past values of the states (x) and the input (u) … The ODEs for the dynamic reservoir and the weight adaptation system can be implemented directly in analog hardware. To implement the above ODEs in software or efficient digital hardware (e.g., field-programmable gate arrays (FPGAs) or custom digital application-specific integrated circuits (ASICs)), the update equations must be discretized … To implement the process of the present disclosure in software or digital hardware, the ODEs are converted to delay difference equations (DDEs)" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) that are adapted/updated by converting ODEs of the output weight update equation to delay difference equations (DDEs)).
Regarding Claim 17,
Petre et al. in view of Matic et al. teaches the computer program product of claim 16.
In addition, Matic et al. further teaches wherein the method further comprises computing a representation for a next set of weights over the multiple clock cycles (Fig. 4; Fig. 6; Col. 8, lines 10-39: "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" teaches that the output weights (reservoir state weight values) are calculated at sample times driven by a clock (e.g. over multiple clock cycles) for adapting/updating output layer weights (computing next set of weights)).
Petre et al. and Matic et al. are analogous to the claimed invention because they are directed to signal processing using reservoir computing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the method further comprises computing a representation for a next set of weights over the multiple clock cycles as taught by Matic et al. to the disclosed invention of Petre et al.
One of ordinary skill in the art would have been motivated to make this modification to "enable high speed operation via advanced design techniques such as pipelining and asynchronous digital design" (Matic et al. Col. 10, lines 17-19).
Regarding Claim 18,
Petre et al. in view of Matic et al. teaches the computer program product of claim 15.
In addition, Petre et al. further teaches wherein the plurality of reservoir state value weights define output layer weights and the method further comprises computing a final output using multiplication of the output layer weights with a history of state results (Fig. 6; Col. 14; lines 23-34: "The weights of the output layers 604 are adapted via the gradient learning algorithm 602 described below. The gradient descent learning algorithm 602 is based on short-time prediction of the input signal. That is, the weights of the output layers 604 are adapted to make the best prediction of the input signal a short step τ in the future using a weighted combination of the delay-embedded states (which encodes the time history of reservoir state dynamics) and optionally, the delay embedding of the input signal (which encodes the time history of the input signal). Since noise is random and unpredictable, the predicted signal y(t)=≐ũo(t+τ) will be free of noise" teaches that the gradient descent algorithm 602 (weight adaptation component) computes output layer weights (reservoir state value weights) to produce outputs. Fig. 6; Fig. 8; Col. 17, lines 36-47: "The reservoir state vector x(t) is then split into individual elements 800 x1(t), . . . , xN(t), and for each reservoir state element 800 xi(t), a time history of its dynamics is created by applying a length-K delay embedding. The delay embedded reservoir state elements 801 xi(t), xi(t−τi), . . . , xi(t−Kτi) are multiplied by tunable output weights 802 Ci1, . . . , Ci(K+1), summed together and delayed by time delay 803 τSK to obtain denoised reservoir state element 804
x
~
i(t). The denoised reservoir state elements are them summed together, and delayed by time delay 805 τSN to obtain the denoised output signal 806 y(t)" teaches that a final output is computed by multiplying a time history of reservoir state results from the delay embedding with the output weights).
Response to Arguments
Applicant’s arguments, filed 12/04/2025, with respect to the claim interpretation under 35 U.S.C. 112(f) have been fully considered and are persuasive. Therefore, the 35 U.S.C. 112(f) claim interpretations have been withdrawn.
Applicant’s arguments, filed 12/04/2025, with respect to the claim rejections under 35 U.S.C. 112(a) have been fully considered and are persuasive. Therefore, the 35 U.S.C. 112(a) rejections have been withdrawn.
Applicant’s arguments, filed 12/04/2025, with respect to the claim rejections under 35 U.S.C. 112(b) have been fully considered and are persuasive. Therefore, the 35 U.S.C. 112(b) rejections have been withdrawn.
Applicant's arguments, filed 12/04/2025, with respect to the 35 U.S.C. 101 abstract idea rejections to the claims have been fully considered but they are not persuasive. Applicant asserts “Claims 1-20 stand rejected under 35 U.S.C. § 101 as allegedly being directed to non- statutory subject matter.
Without acquiescing in the Examiner's rejection, independent claims 1, 8, and 15, as amended, and the claims that depend thereon, are patent-eligible under 35 U.S.C. § 101.
The Office Action alleges that "the claimed invention is directed to an abstract idea without significantly more." Office Action, page 12. Applicant respectfully disagrees.
Firstly, claim 1 is not directed to directed to an abstract idea at least because it is integrated in a specific, unconventional technological implementation. Claim 1 recites a "cognitive signal processor" implemented as a physical machine, comprising a reservoir computer, a delay embedding component, a weight adaptation component, and an output layer computer, with specific interconnections and functional relationships. Unlike mere "instructions to apply" an abstract idea, the claim is directed to a non-conventional hardware architecture that enables denoising of wide bandwidth signals under real-world constraints.
Secondly, the specification describes, and claim 1 recites, a technical solution to a
technical problem. The specification explains that conventional signal processors are limited by the need to compute all values within a single clock cycle, which restricts either the system size or the processing bandwidth (see paragraphs 0024, 0029, and 0065). The technical solution overcomes these limitations by "allowing and accounting for multiple clock cycles when computing various values throughout the system," and by breaking "each major computation... into a cascade of elementary functional computations over multiple clock cycles" (see paragraphs 0066 ad 0072).
Furthermore, the system may be "implemented on either a field-programmable gate array (FPGA) or digital complementary metal-oxide-semiconductor (CMOS) hardware" (see paragraph 0024), and leverages pipelined computation, delay accounting, and custom memory architecture (see paragraphs 0059, 0066, and 0064). The delay embedding component may include "a volatile memory device, e.g., Random Access Memory (RAM), that holds states, and concatenates them into {z}n," with FIFO functionality (see paragraph 0059). The weight adaptation component utilizes "gradient descent based on [the error signal] to scale the reservoir state matrix {z}n," and "provides as output a matrix of weights C to the output layer computer..., and as feedback back to itself after being subjected to a delay of NTout" (see paragraph 0060).
Additionally, the system is customized to "track and account for delays produced by the various components and processing... [and] imposes a delay to the input vector prior to input to the comparator" (see paragraphs 0062-0063) and is optimized for hardware resource constraints (see paragraphs 0081-0082).
Thirdly, the claims recite improvements over conventional techniques. As stated in paragraph 0026, the disclosed techniques "allows for multiple clock cycle delays in computing various sets of values throughout the system using pipelining, resulting in a system running at a faster clock rate than conventional hardware CSPs." By converting ordinary differential equations (ODEs) to delay differential equations (DDEs), the system "allows for the output layer weights to be updated over multiple clock cycles" and achieves "increased achievable processing performance." See paragraphs 0026-0027. The features These features produce a "technical effect... increasing denoising performance while maintaining processing bandwidth (e.g., operating at higher clock rates)" ([0025]), which is a practical application in hardware not achievable by mental effort or pen/paper calculation.
Finally, the claimed cognitive signal processor is not generic, specifically tailored for real-time, wide-bandwidth signal denoising using non-conventional memory management, component delays, and hardware-optimized pipelining. The claim does not preempt the abstract idea of denoising, but is limited to a particular architecture-one that is not routine, as demonstrated by the technical details above.
Although potentially of different scope than claim 1, independent claims 8 and 15, as amended, recite similar features. Therefore, independent claims 1, 8, and 15 and the claims that depend thereon, are also patent-eligible under 35 U.S.C. § 101.
Accordingly, for at least the above reasons, Applicant respectfully requests that the Examiner reconsider and withdraw the rejection of claims 1-20 under 35 U.S.C. § 101.” (Remarks Pages 8-10).
Examiner’s Response:
The examiner respectfully disagrees. Applicant has made general assertions that claim 1 recites claim elements that are not directed to an abstract idea and that even if the claim elements are directed to an abstract idea, the judicial exceptions are integrated into a practical application because the claims recite elements that cannot reasonably be characterized as covering mental processes or reflect an improvement to a technology or technical field. Regarding the “produce a plurality of reservoir state values” limitation of claim 1, this limitation, under it broadest reasonable interpretation, is considered an abstract idea encompassing producing a plurality of reservoir state values (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can produce reservoir state values). In addition, regarding the “compute a plurality of reservoir state value weights to produce a plurality of output values, wherein the plurality of reservoir state value weights are computed over multiple clock cycles, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored” limitation of claim 1, this limitation, under it broadest reasonable interpretation, is considered an abstract idea encompassing computing reservoir state value weights to produce output values, the reservoir state weight values being computed over multiple clock cycles using pipelining with intermediate values stored (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can compute reservoir state value weights to produce output values in pipelined fashion over multiple clock cycles with stored intermediate values). Furthermore, since the “produce a plurality of reservoir state values …” and “compute a plurality of reservoir state value weights …” limitations are directed to a judicial exception, they cannot provide any alleged solution or improvement. See MPEP 2106.05(a): “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. See the discussion of Diamond v. Diehr, 450 U.S. 175, 187 and 191-92, 209 USPQ 1, 10 (1981)) in subsection II, below.”
Thus, it is the additional elements that are analyzed to determine whether the judicial exception is integrated into a practical application, not the judicial exception itself. The additional elements in claim 1 of “a reservoir computer”, “a delay embedding component”, “a weight adaptation component”, “an output layer computer”, “an output of the reservoir computer is communicatively coupled to an input of the reservoir computer and to the delay embedding component”, “the reservoir computer”, “an input of the delay embedding component communicatively coupled to an output of the reservoir computer and an output of the delay embedding component communicatively coupled to an input of the weight adaptation component and to an input of the output layer computer”, “an output of the weight adaptation component communicatively coupled to an input of the weight adaptation component and to an input of the output layer computer, “the weight adaptation component”, “a clock for the denoising cognitive signal processor system”, “an input of the output layer computer communicatively coupled to an output of the delay embedding component, an input of the output layer computer communicatively coupled to an output of the weight adaptation component, and an output of the output layer computer communicatively coupled to an input to the weight adaptation component” as drafted, under their broadest reasonable interpretations, are high level recitations of applying a generic computer and neural network to implement the abstract ideas such that it amounts to no more than merely using a computer as a tool to perform generic computer functions. In addition, regarding applicant’s arguments that “the system may be "implemented on either a field-programmable gate array (FPGA) or digital complementary metal-oxide-semiconductor (CMOS) hardware" (see paragraph 0024)”, implementing the cognitive signal processor system on a FPGA or CMOS hardware corresponds to mere instructions to apply language using a generic computer component. As such, the recitation that the abstract ideas are to be performed with such circuitry is a mere instruction to apply the judicial exception using a generic computer component. See MPEP 2106.05(f): “Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. … Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible.” Moreover, the recitation of “collect the plurality of reservoir state values” and “output the plurality of output values”, as drafted, amount to insignificant extra-solution activity. In particular, the additional elements corresponds to mere data gathering. See MPEP 2106.05(g). Accordingly, the additional elements do not integrate the abstract ideas into a practical application.
Furthermore, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe computers, components, and a clock for applying the abstract ideas) or insignificant extra-solution activity (i.e. collecting/recording and outputting/transmitting data). Furthermore, the “collect …” and “output …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network … iii. Electronic recordkeeping). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
In other words, the limitations of “produce a plurality of reservoir state values …” and “compute a plurality of reservoir state value weights …” are abstract ideas that are directed to a judicial exception, so they cannot provide any alleged solution or improvement. Additionally, the limitations of “collect the plurality of reservoir state values” and “output the plurality of output values” are additional elements corresponding to insignificant extra-solution activity that is well-understood, routine, and conventional. Furthermore, the other additional elements recited in claim 1 are directed to mere instructions to apply an abstract idea. Therefore, claim 1 does not recite additional element(s) that can provide any alleged solution, improvement, or inventive concept. As such, the judicial exception is not integrated into a practical application, nor do the claims contain significantly more than the judicial exception.
Applicant relies on the arguments above regarding independent claims 8 and 15 and dependent claims 2-7, 9-14, and 16-20 therefore the response above is applicable to those claims.
Applicant's arguments, filed 12/04/2025, with respect to the 35 U.S.C. 103 prior art rejections to the claims have been fully considered but they are not persuasive. Applicant asserts “Claims 1-5, 8-12, and 15-18 stand rejected under 35 U.S.C.§ 103 as allegedly being unpatentable over PETRE (U.S. Patent No. 10,404,299) and MATIC (U.S. Patent No. 10,211,856). Applicant respectfully traverses the rejection.
Without acquiescing in the Examiner's rejection, the cited sections of the applied references, whether taken alone or in any reasonable combination, do not disclose at least "wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the denoising cognitive signal processor system, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored," as recited in claim 1, as amended (emphasis added). The Office Action concedes that PETRE does not disclose "wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the denoising cognitive signal processor system," and relies on Figs. 4 and 6, and column 8, lines 10-39, of MATIC as allegedly disclosing this feature. See Office Action, pages 51-52. Even assuming that the Examiner's interpretation of MATIC is reasonable, which Applicant does not concede, Applicant respectfully submits that the cited portions of MATIC do not disclose the features recited in amended claim 1.
For example, column 8, lines 10-39, of MATIC recite (emphasis added): …
As such, MATIC at column 8, lines 10-39, discloses a reservoir computer where state functions are "represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock." The Office Action has not shown that MATIC discloses, and the cited portions of MATIC do not disclose "wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the denoising cognitive signal processor system, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored," as recited in claim 1, as amended (emphasis added).
Although potentially of different scope than claim 1, independent claims 8 and 15, as amended, recite similar features. Therefore, independent claims 1, 8, and 15 and the claims that depend thereon, are patentable over the cited sections of the applied references, whether taken alone or in any reasonable combination.
Accordingly, Applicant respectfully requests that the Examiner reconsider and withdraw the rejection of claims 1-5, 8-12, and 15-18 under 35 U.S.C. § 103 based on PETRE and MATIC” (Remarks Pages 14-16).
Examiner’s Response:
The examiner respectfully disagrees. Regarding claim 1, the examiner respectfully disagrees with applicant’s assertion that “the cited sections of the applied references, whether taken alone or in any reasonable combination, do not disclose at least "wherein the plurality of reservoir state value weights are computed over multiple clock cycles of a clock for the denoising cognitive signal processor system, and the weight computation being distributed across the multiple clock cycles using pipelining with intermediate values stored," as recited in claim 1, as amended (emphasis added)” In particular, examiner points to Col. 8, lines 10-39 of Matic et al. (US 10,211,856 B1), which specifically discloses, with respect to Fig. 4 and Fig. 6, "Turning to FIG. 6, a block diagram of an example of an implementation of a reservoir computer 600 as an adaptable nonlinear state space filter is shown in accordance with the present disclosure. In this example, the reservoir computer 600 (similar to the example in FIG. 5) includes the reservoir 402, the plurality of inputs 404, and the plurality of trainable readouts 406 similar to the example shown in FIG. 5. However, in this example, the reservoir computer 600 receives input layer weights 602 at the plurality of inputs 404, reservoir connectivity matrix weights 604 at the reservoir 402, and output layer weights 606 at the plurality of trainable readouts 406. In this example, if the reservoir computer 600 is an ESN, the state functions of the reservoir 402 are represented by uniform time sampled analog waveforms and the states and output, or outputs, are updated at sample times that are typically driven by a clock (not shown). In general, ESN based signal processing and computing requires various iterative maps that govern the state update, weights adaptation, and output generation. As such, in this disclosure computing nodes are utilized with first order dynamics described by first order ODEs. The resultant system of ODEs (i.e., the reservoir dynamic) is converted into an iterative map via converting the ODEs into DDEs using matrix exponentials … For a reservoir 402 with a plurality of state notes 504 that are linear computing nodes, the resultant system of DDEs enables the implementation of arbitrary feedback delays for the hardware implementations. The DDEs also enable effective parallelization of the state update equations and learning processes for adapting the output layer weights 606" (i.e. the reservoir computer 600 is an adaptable nonlinear state space filter, wherein the states and outputs are iteratively updated (e.g. calculated) at sample times driven by a clock (e.g. over multiple clock cycles) for weight adaptation for adapting/updating output layer weights (reservoir state weight values) for the signal processing system). The output layer weights (reservoir state weight values) are updated/adapted based on the updated states that are updated at sample times that are typically driven by a clock (e.g. updated based on a clock cycle). Additionally, the examiner further points to Col. 5, lines 10-30 and Col. 6, lines 40-49 of Matic et al. (US 10,211,856 B1), which specifically disclose, with respect to Fig. 1 and Fig. 6, "the HSC 108 can: tolerate realistic hardware constraints, such as feedback loop delay and delays in the feedforward paths; enable massively parallel implementations of high quality IIR filters; … the HSC 108 includes a parallel neuromorphic processor architecture that is configured to perform the neuromorphic processing. In this example, the parallel neuromorphic processor architecture is a reservoir computer that may be an echo state network or liquid-state machine. The reservoir computer includes a reservoir and a plurality of trainable readouts. In general, the reservoir computer is an adaptable state space filter having a plurality of reservoir connectivity matrix weights, plurality of input layer weights, and a plurality of output layer weights which will be described in greater detail later" (i.e. the reservoir computer is an adaptable state space filter for implementing IIR filters) and "The HSC 108 utilizes an ordinary differential equation to delayed transformation to map the IIR filtering process onto a massively parallel neuromorphic processor architecture. As a result, this IIR filtering design can tolerate realistic hardware constraints, such as, for example, feedback loop delay and delays in the feedforward paths. Additionally, this IIR filtering design also allows the utilization of an arbitrary number of pipeline stages in each multiplier and summing junction in the implemented hardware IC" (i.e. calculations for the IIR filtering performed by the reservoir computer can be performed over multiple pipeline stages). The reservoir computer of the neuromorphic processor performs IIR filtering accounting for hardware constraint delays by utilizing pipelining for performing the computations of the reservoir computer in the hardware IC, meaning that the output layer weights (reservoir state weight values) are updated/adapted based on the updated states that are updated at sample times that are typically driven by a clock using pipelining.
Applicant relies on the arguments above regarding independent claims 8 and 15 and dependent claims 2-7, 9-14, and 16-20 therefore the response above is applicable to those claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN J HALES whose telephone number is (571)272-0878. The examiner can normally be reached M-F 9:00am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamran Afshar can be reached at (571) 272-7796. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRIAN J HALES/Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125