DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/09/26 has been entered.
Claim Amendment
The amendment filed 03/09/26 has been entered.
(1) Claims amended: independent claims: 1 (method), and 11 (system).
(2) Claims canceled: 9, 15 and 17.
Claim Status
Claims 1-8, 10-14, 16 and 18-20 are pending. They comprise of 2 groups:
(1) Method1: 1-8 and 10, and
(2) Apparatus: 11-14, 16, and 18-20.
1. (Currently amended) A method for operating a processing device, the method comprising:
[1] configuring at least one switch to connect one or more selected intellectual property (IP) blocks to the processing device;
[2] receiving, by the at least one switch, an activation signal based on the one or more selected IP blocks, the activation signal configured to identify that the one or more selected IP blocks is to be disabled, wherein the activation signal is a reset enable signal and the activation signal causes the at least one switch to gate the reset to allow logic associated with the one or more selected IP blocks to be clocked while holding the disabled one or more of the selected IP blocks in reset;
[3] irreversibly disabling, by the at least one switch, a connection of the one or more selected IP blocks and the processing device based on the received activation signal; wherein irreversibly disabling is configured by activating an electrical element that once activated is permanently disconnected preventing subsequent electrical connection; and
[4] verifying the disabling of the connection of the one or more selected IP blocks and the processing device is irreversible.
Note: for referential purpose, numerals [1]-[4] are added to the beginning of each element.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-7 (method1) and respective 11, 13 and 18-20 (system1) are rejected under 35 U.S.C. 103(a) as obvious over
Name Publication
(1) DONDINI ET AL., US 2018/0.341.791, and
(2) WO 2019/129.704, and
(3) YU ET AL. US 2019/0.187.899.
As for independent method claim 1, DONDINI ET AL. discloses a method for operating a processing device,
{see [0087 In one or more embodiments apparatus (e.g. a microcontroller-based appliance) may include a processor circuit..], the apparatus or the appliance is the processing device.}
the method comprising: {see claim in italics}
[1] configuring at least one switch to connect one or more selected intellectual property (IP) blocks to the processing device;
{see Fig. 1, switch A, switch B, or switch C, Intellectual property (IP) “IPa”, “IPb”, “IPc,” connected to the processing device is I/O (PAD) of GPIO, and respective 0003]}
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[2] receiving, by the at least one switch, an activation signal based on the one or more selected IP blocks, the activation signal configured to identify that the one or more selected IP blocks is to be disabled;
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{[0024] teaches describes receiving the activation (enable) signal and [0028] which teaches receiving an activation signal for block IPa to enable it while disable other selected IPb and IPc}
As shown in [0005] above, activation signal pertain to a certain IP block based on digital logics associated with the IP’s, which is controlled by the micro-controller, is transmitted to the dedicated analog switch. In view of the teaching of “allowing transmission of analogs signals pertaining to a certain IP to an output pad handled by the GPIO,” the step of “receiving the activation signal” is inherently included or would have been obvious to include the receiving the “digital enable signals” from the analog IP’s to allow the transmission. Furthermore, in view of the teaching in [0024] “analog IP also has a digital output signa with is coupled to the GPIO analog switch,” the step of receiving an activation signal from the IP block is inherently included or would have been obvious to do so to allow the transmission.
[3] disabling, by the at least one switch, a connection of the one or more selected IP blocks and the processing device based on the received activation signal; and
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{see [0028] which teaches receiving an activation signal for block IPa to enable it while disable other selected IPb and IPc.}
[4] verifying the disabling of the connection of the one or more selected IP blocks and the processing device.
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As shown above, a “gating” control may be performed to obtain security information on a certain analog IP and a related GPIO indicates that the connection/communication between these two element should be either allowed or denied (forbidden). If it’s denied (forbidden), then the disabling of the connection of the one or more selected IP blocks and the processing device inherently being verified.
DONDINI ET AL. teaches the claimed invention except for explicitly discloses (1) the step of “receiving, by the at least one switch, the activation signal..” and the verification of the connection, and (2) carrying out step [2] of disabling in a “irreversibly” mode, and (3) the type of activation signal, a reset enable signal with other features.
As shown in [0005] above, activation signal pertain to a certain IP block based on digital logics associated with the IP’s, which is controlled by the micro-controller, is transmitted to the dedicated analog switch. In view of the teaching of “allowing transmission of analogs signals pertaining to a certain IP to an output pad handled by the GPIO,” it would have been obvious to include the receiving the “digital enable signals” from the analog IP’s to achieve the “allowed transmission.” Furthermore, in view of the teaching in [0024] “analog IP also has a digital output signa with is coupled to the GPIO analog switch,” the step of receiving an activation signal would have been obvious to achieve the “allowed transmission.”
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As for the verification, DONDINI ET AL. on [0048] teaches security control may be performed to obtain security information on a certain analog IP and a related GPIO indicates that the connection/communication between these two element should be either allowed or denied (forbidden). Therefore, if the information indicating that the connection /communication is denied, it would have been obvious that the disabling of the connection has been verified. Alternatively, it would have been obvious to use this security control of denied connection/communication as a verifying step of the disabled connection.
DONDINI ET AL. teaches the claimed invention except for explicitly discloses (1) the step of “receiving, by the at least one switch, the activation signal..” and the verification of the connection, and (2) carrying out step [2] of disabling in a “irreversibly” mode, and (3) the type of activation signal, a reset enable signal with other features.
As for the independent claim 11 which is an apparatus to carry out the method of claim 1, DONDINI ET AL. discloses:
[I] A system comprising:
[1] a processing device;
{see [0087 In one or more embodiments apparatus (e.g. a microcontroller-based appliance) may include a processor circuit..], the apparatus or the appliance is the processing device.}
[2] one or more selected intellectual property (IP) blocks configured to operate with the processing device; and
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The processing device is the home appliance such as TV screens, refrigerators, etc., employing micro-controllers and IP blocks are IPa, IPb, IPc, etc. See also Fig. 1 above.
[3] at least one switch configured to connect at least one of the one or more selected IP to the processing device, wherein the at least one switch is further configured to receive an activation signal, the activation signal configured to identify that the one or more selected IP is to be disabled, and disable a connection of the at least one of the one or more selected IP and the processing device based on the received activation signal.
{see Fig. 1, switch A, switch B, or switch C, Intellectual property (IP) “IPa”, “IPb”, “IPc,” connected to the processing device is I/O (PAD) of GPIO, and respective 0003]}
As shown in [0005] above, activation signal pertain to a certain IP block based on digital logics associated with the IP’s, which is controlled by the micro-controller, is transmitted to the dedicated analog switch. In view of the teaching of “allowing transmission of analogs signals pertaining to a certain IP to an output pad handled by the GPIO,” the step of “receiving the activation signal” is inherently included to complete “the allowed transmission.” Furthermore, in view of the teaching in [0024] “analog IP also has a digital output signa with is coupled to the GPIO analog switch,” the step of receiving an activation signal from the IP block is inherently included to complete “the allowed transmission.”
Therefore, as for independent claims 1 (method) and 11 (system) as shown in the rejection above, DONDINI ET AL. teaches the claimed invention except for (2) carrying out step “disabling” in a “irreversibly” mode and (3) the type of activation signal, a reset enable signal with other features.
WO 2019/129704 is cited to teach an integrated circuit (IC) that has specific non-reversible configuration so that the secure area (IC) forces the switch(es) in a permanent and non-reversible lock of the direction, see page 6, lines 8-23, below. The OTP switches includes a fuse which can be blown to prevent further operation of the switches or to disable the corresponding interconnect of each switch. In other word, it teaches the amended feature of irreversibly disabling is configured by activating an electrical element that once activated is permanently disconnected preventing electrical connection; and
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Therefore, it would have been obvious to a person having ordinary skill in the art (PHOSITA) before the effective filing date of the claimed invention to modify a method /system for operating a processing device of DONDINI ET AL. by having non-reversible switch, i.e. a fuse which can be blown to prevent further operation of the switches, for disabling a connection of the IC and IP blocks of DONDINI ET AL. to force the switch(es) in a permanent and non-reversible lock of the direction and irreversibly disabling is configured by activating an electrical element that once activated is permanently disconnected preventing electrical connection as taught by WO 2019/129704, see page 6, lines 8-15 above. Rational G/TSM, combine. Alternatively, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of the combination were predictable.
The teachings of DONDINI ET AL./ WO 2019/129704 teaches the claimed invention except for (3) the amended feature, the type of activation signal, a reset enable signal with other features.
YU ET AL. is cited to teach in an electronic device, the use of a reset signal RESET, generated by a reset circuit 130, creates a “enable” signal for operating the various components of the electric device 100, see [0081-0082] and Fig. 6.
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Therefore, it would have been obvious to a person having ordinary skill in the art (PHOSITA) before the effective filing date of the claimed invention to modify a method for operating a processing device of DONDINI ET AL./ WO 2019/129704 by having a reset enable signal to gate the reset on a component of a device to be in “enable signal (or active signal) that is activated in a period as taught by YU ET AL. on [0082]. Furthermore, in view of the teachings in DONDINI ET AL./WO 2019/129704 and YU ET AL. in [0081-0082] and Fig. 7, it would have been obvious that the “a reset enable signal” causes at least one switch to gate the reset to allow one IP block (IPa) in DONDINI ET AL. to be blocked while holding “disabled one” (IPb) or (IPc) to be in reset or vice versa.
As for dep. claim 4 (part of 1 above) which deals with other function of the switch configuration, identifying an IP blocks to be enabled to selected customers, this is taught in DONDINI ET AL. [0024 … enable signal of the homologous GPIO analog switch in order to enable (or disable) IP-to-pad communication…] which teaches the IP blocks to be enabled and [005 … in order to meet different applications requirements, various products for the general-purpose market..”] which would indicate the IP is configured to be enabled to different and/or selected customers which normally have different applications and requirements.
As for dep. claim 5 (part of 1 above) and respective dependent claim 13 (part of 11 above) which deal with other function of the switch configuration, identifying an IP blocks to be disabled to selected customers, this is taught in DONDINI ET AL. [0024 … signal of the homologous GPIO analog switch in order to [enable or] disable IP-to-pad communication…] which teaches the IP blocks to be disabled. See also Fig. 3, “AIN-Enb” to switch “B.” Also, [005 … in order to meet different applications requirements, various products for the general-purpose market..”] which would indicate the IP is configured to be enabled to different and/or selected customers which normally have different applications and requirements.
As for dep. claim 6 (part of 1 above) which deals with the design of the activation signal to be based on the selected IP blocks, this is taught in DONDINI ET AL. [0024 … signal of the homologous GPIO analog switch in order to enable or disable IP-to-pad communication…] which teaches the IPa blocks to be enabled while IPB to be disabled, See Fig. 3.
As for dep. claim 7 (part of 1 above) which deals with other function of the switch configuration, identifying an IP blocks to be disabled to selected customers, this is taught in DONDINI ET AL. [0024 … signal of the homologous GPIO analog switch in order to [enable or] disable IP-to-pad communication…] which teaches the IP blocks to be enabled. See also Fig. 3, “AIN-Enb” to switch “B.”
As for dep. claim 18 (part of 11 above) which deals with a feature of a switch in the processing device, not connected to a processing logic, this is taught in DONDINI ET AL. [0047-0048] wherein connection of an analog IP with respect to a GPIO is denied or forbidden, which would lead to a switch not directly connected to a processing logic of the processing device. Alternatively, it would have been obvious not to connect the switch to a processing logic of the processing device because it’s denied or forbidden and this would prevent malicious software for accessing the switch or IP logic for harming the device. Furthermore, as shown in [0024], when signals AINc, AIN-Enc are disabled and the coupled switch C in GPIO should be shown to be disabled to disable the IP-to-pad communication.
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As for dep. claim 19 (part of 11 above) which deals a condition of the switch, is read and determined to be in “disable connection” with a selected IP blocks, this is taught in DONDINI ET AL. Fig. 1, and [0028… are IPb, IPc, sharing the same pad are disabled.] above wherein IPb, IPc, and respective AINc, AIN-Enc are disabled and the coupled switch C in GPIO is shown to be disabled to disable the IP-to-pad communication, as taught in [0024].
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As for dep. claim 20 (part of 11 above) which deals with an operation of a switch, is read by a processor, this is taught in DONDINI ET AL. [0024-0026 and 0028].
[0024 … analog switch… enable signal … can be managed by software through analog IP digital interface in order to selectively activate the IP’s ….],
[0025-0026 … A programmable digital controller (GPIO-C) can be provided to manage the software configuration …, possibly via a certain number of analog switches…],
[0028…processor CP can configure a curtained analog IP (for instance IPa)..].
Dependent claim 2 (part of 1 above) and respective dependent claim 12 (part of 11 above) are rejected under 35 U.S.C. 103 as being unpatentable over DONDINI ET AL. /WO 2019/129704 / YU ET AL. as applied to claims 1, 4-7 and 11 above, and further in view of (3) GATHOO ET AL., US 7,574,679.
In a system for generating IP cores (blocks) using secure script, GATHOO ET AL. teaches one or more IP blocks implements a proprietary encryption that is specific to a certain customer, see Fig. 4, IP blocks, and pars. (31) and (32).
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Therefore, it would have been obvious to a person having ordinary skill in the art (PHOSITA) before the effective filing date of the claimed invention to modify a method for operating a processing device of DONDINI ET AL. /WO 2019/129704 by having IP blocks implements a proprietary encryption that is specific to a certain customer as taught by GATHOO ET AL. for IP blocks proprietary, see par. (31) above. Rational G/TSM, combine. Alternatively, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Dependent claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over DONDINI ET AL./WO 2019/129704/ YU ET AL. as applied to claims 1, 4-7 above, and further in view of (4) ENROUGHTY, US 2008/0.015.946.
ENROUGHTY the activation of a signal for service of a purchased device is based on a specific related to the device, i.e. a customer purchasing the device, see Fig. 1, customer service terminal 120, and purchasing device 110, signal transmission between the devices, see also [0025].
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Therefore, it would have been obvious to a person having ordinary skill in the art (PHOSITA) before the effective filing date of the claimed invention to modify a method for operating a processing device of DONDINI ET AL./WO 2019/129704 wherein the activation signal for a service on the device is based on a specific event such as a customer purchasing the device as taught by ENROUGHTY for starting the service, see [0025].
Dependent claim 8 (part of 1 above) and respective dependent claim 14 (part of 11 above) are rejected under 35 U.S.C. 103 as being unpatentable over DONDINI ET AL./WO 2019/129704 / YU ET. AL. as applied to claims 1, 4-7 and 11 above, and further in view of (5) LEE ET AL., US 10,296,065.
In a similar IP blocks management, LEE ET AL teaches is cited to teach a clock management unit (CMU) performing clock gating on at least one IP blocks, one of the IP blocks providing a request signal to enter a selected one of a mode, sleep or active, enable or disable, etc., see claim 1, [0081-0082].
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Therefore, it would have been obvious to a person having ordinary skill in the art (PHOSITA) before the effective filing date of the claimed invention to modify a method for operating a processing device of DONDINI ET AL./WO 2019/129704 by having a clock management unit perform clock gating on the IP blocks and the IP blocks desires to enter a sleep mode as taught by LEE ET AL on claim 1 for clock (time) management of the IP blocks. The selection of the IP blocks to be in “off” mode would inherently cause the at least one switch to disable a digital logic associated with the one or more selected IP blocks.
Dependent claim 10 (part of 1 above) and respective dependent claim 16 (part of 11 above) are rejected under 35 U.S.C. 103 as being unpatentable over DONDINI ET AL./WO 2019/129704 / YU ET AL. as applied to claims 1, 4-7 above, and further in view of (7) FENDER ET AL., US 2019/0.042.801.
In a similar privileged system components, FENDER ET AL. is cited to teach logic flow with security policies using an address range permission check to perform protocol validation on instruction whereby a security device performs memory address range permission on checks on an instruction specifying to access a memory address to determine whether a circuit is permitted to access the memory address. Doing so allow the security device to validate the instruction (if within permitted range of memory addresses) or invalidate the instruction (if not within permitted range of memory addresses), see par. [0046].
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Therefore, it would have been obvious to a person having ordinary skill in the art (PHOSITA) before the effective filing date of the claimed invention to modify a method for operating a processing device of DONDINI ET AL./WO 2019/129704 by having a logic flow using an address range permission check to perform protocol validation on instruction whereby a security device performs memory address range permission on checks on an instruction specifying to access a memory address to determine whether a circuit is permitted to access the memory address as taught by FENDER ET AL. on [0046]. It would have been obvious to apply the same teaching to the IP blocks management of DONDINI ET AL. by looking at operating security policies with respect to address range permission check to prevent access to the disabled IP blocks as taught by FENDER ET AL.
Response to Arguments
Applicant's amendments and arguments filed 03/06/26 have been fully considered and the results are as followed:
(1) 103 Rejection:
(1) Applicant’s comment that the combination of DONDINI /WO 2019/129.704 / YU ET AL. does not teach the amended feature of the feature of the activation signal is not persuasive in view of the teachings of YU ET AL. in [0081], as cited above.
(2) Applicant’s comment that the combination of WO 2019/129.704 into Dondini frustrates the purpose of the flexibility of Dondini and not combinable is not persuasive because (1) WO 2019/129704 deals with a conventional integrated circuit (IC) that is applicable to the IC system of Dondini, (2) WO 2019/129704 teaches in “some embodiments, the secure area has specific non-reversible memory configuration so that depending on its non-reversible lock of the direction. The one-time OTP switches includes a fuse which can be blown to prevent further operation of the switches or to disable the corresponding interconnect of each switch or preventing electrical connection. This is applicable to the scope of Dondini if desired and therefore the combination is obvious and desirable for the cited intent.
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Applicant’s comment on page 11, cited portion above, that the entire purpose of WO 2019/0.129,704 is to maintain the connection between the networks but only allow communication in a single direction is noted, however, this is one of the many embodiments cited by WO 2019/129.704 from pages 2-11. The examiner only uses one of many embodiments as shown on page 6, line 8-15, to show a specific embodiment wherein the OTP switches includes a fuse which can be blown to prevent further operation of the switches or to disable the corresponding interconnect of each switch.
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Relevant Citations
US 2015/0.227.462, by GROCUTT, discloses the feature of “checking access permission for a range of address”, see [0032].
No claims are allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tan "Dean" D NGUYEN whose telephone number is (571)272-6806. The examiner can normally be reached on M-F: 6:30-4:30 PM (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sarah M Monfeldt can be reached on 571-270-1833. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN D NGUYEN/Primary Examiner, Art Unit 3689