DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to communications filed on 8/11/2025.
Claims 11, 17, 29 and 35 have been amended.
Claims 1, 3-4, 9-12, 14, 16-18, and 20-38 are pending.
Response to Arguments
Applicant's arguments filed 8/11/2025 have been fully considered but they are not persuasive. In the response filed, applicant argues, in substance:
a) In page 9 of the response filed, applicant argues that the combination of Opastrakoon et al. (US 20220284974 A1) and Mishra et al. (US 20170168966 A1) fails to teach or disclose the limitation “wherein the trim controller is in an always-on power domain, and the one or more peripherals are in switchable power domains” because the “cited portions of Mishra do not teach “the one or more peripherals are in switchable power domains.”
In response to argument (a), the examiner respectfully disagrees.
As explained in page 3, lines 1-4 of the non-final Office action mailed on 4/11/2025, the term “switchable” may indicate that a power supply “may be turned on or off by any means”. Any electrically powered device is thus in a “switchable” domain as it would be impossible for a electrically powered device to remain powered on without a power supply.
b) In page 10 of the response filed, applicant argues that the “focus of the application is the arrangement of different components for a computing system […] instead of how to implement the nonswitchable power domain since it is known in the art.” Applicant cites, as an example, a KEYSTONE architecture user guide (SPRUGV4C) released by applicant in 2010.
In response to argument (b), the examiner respectfully disagrees.
The KEYSTONE architecture user guide was not incorporated to the specification at the time the invention was filed nor at any time thereafter. A Person of Ordinary Skill in the Art with possession of the current application would thus not be aware of the existence of the user guide or could not reasonably derive that the definitions to use for the limitations in the claimed invention is specifically that of the KEYSTONE architecture.
The examiner further notes that the term used by the KEYSTONE architecture user guide is “AlwaysOn” (page 8, section 2.2.1) and not “always-on” as claimed further raising questions as to the relevance of the document.
While the claims do create a relationship between elements, the system does require the addition of an “always-on power domain”, which is not defined, and one of ordinary skill in the art would not be able to stablish a relationship between two elements if one of the elements is undefined. It is thus unclear how the claimed system is made.
Examiner’s Note
While the current grounds of rejection are maintained, new grounds of rejection are further added by this Office action. See “2nd Rejection” below.
Claim Interpretation
The term “switchable” is interpreted to differentiate from an immutable state to a changeable or mutable state. Specifically, regarding the “always-on” power domain versus the “switchable” domain, “always-on” is interpreted to indicate a constant power source, while a “switchable” indicates that the power supply may be turned on or off by any means.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 11 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The claims recite the limitation “always on power domain” The limitation(s) in question do not satisfy the written description requirement under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph. The specification does not describe the limitation(s) in sufficient detail so that one of ordinary skill in the art would recognize that the applicant had possession of the claimed invention.
In this case, the specification does not provide sufficient details to “always on power domain”. No algorithm or steps/procedure/structure for performing the function can be found, explained at all or in sufficient detail. The portions of the specification relating to “always on power domain” are found in par. [0015]. However, the specification lacks any specific details as to how Applicant intends to achieve this function other than reciting a “nonswitchable power domain”. It is unclear by what means Applicant is achieving such a result.
Description as to how the applicant intends to implement an “always on power domain” is not described. Therefore, the specification does not provide a disclosure of the computer and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention under 35 U.S.C. 112(a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Opastrakoon et al. (US 20220284974 A1) filed on 3/2/2021 and in further view of Mishra et al. (US 20170168966 A1).
Regarding claim 1, Opastrakoon discloses A system, comprising:
a processor; (Opastrakoon, #117)
a nonvolatile memory (Opastrakoon, #130) comprising a trim sector (Opastrakoon, #134)
one or more peripherals; and (Opastrakoon, #130)
a trim controller external to the one or more peripherals and (Opastrakoon, #113) communicably coupled to the one or more peripherals, the trim controller configured to:
receive, for each of the one or more peripherals, trim values (Opastrakoon, #320) of the one or more peripherals from the trim sector of the nonvolatile memory, and provide the trim values to the one or more peripherals, (Opastrakoon, [0053] “As shown, configuration setting control component 113 of memory subsystem controller 115 can monitor the access operations performed on memory device 130. In various implementations, as described above, configuration setting control component 113 can monitor programming operations 301 performed on memory device 130 until the number of operations satisfies a threshold criterion associated with the configuration setting values (e.g., trim settings). In one embodiment, the threshold criterion is satisfied with the number of operations performed meets or exceeds a threshold value. Thus, the threshold criterion remains unsatisfied when the number of operations performed is below the threshold value. When the threshold criterion has been satisfied, configuration setting control component 113 can send a request 302 to configuration setting manager 134 to adjust the configuration settings 320 of memory device 130. Notably, the single request 302 can cause configuration setting manager 134 to update multiple configuration settings 320 using information included in the request.”)
Opastrakoon fails to explicitly disclose wherein the trim controller is in an always-on power domain, and the one or more peripherals are in switchable power domains.
However, Mishra teaches wherein the trim controller is in an always-on power domain, and the one or more peripherals are in switchable power domains. (Mishra, [0072] “FIG. 10 illustrates certain aspects of a finite state machine 1000 that can support virtual GPIO in an apparatus. The finite state machine 1000 may monitor state information from a plurality of input sources 1024, including hardware events 1002, configuration parameters 1004, masked data 1006 and/or configuration parameter register addresses 1008.”; [0073] “The finite state machine 1000 may be deployed in an always-on domain to ensure that circuits configured to monitor state and state changes are available when certain input/output states are of interest, including when an active peripheral device is associated with the input/output states of interest. In many implementations, it may be necessary to provide the finite state machine 1000 in the always-on domain to permit reliable monitoring of input/output state.”; [0075] “The finite state machine 1000 may be configured to transmit several different types of packets, and the finite state machine 1000 may select a type of packet in order to optimize latency in the communication link In one example, the finite state machine 1000 may select the packet type based on the GPIO data to be transmitted and an associated configuration of GPIO pins.”)
Mishra is directed to monitoring transfer interfaces. Specifically, Mishra teaches programmable configuration registers wherein, the associated peripheral interfaces must be monitored at all times. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon to incorporate the teachings of Mishra to include the above limitation. Such modification(s) would be motivated to ensure that circuits configured to monitor state changes (i.e. switchable domain peripherals) are available when input/output states are of interest. (Mishra, [0073])
Regarding claim 11, Opastrakoon discloses A system, comprising:
a nonvolatile memory (Opastrakoon, #130) comprising a trim sector; (Opastrakoon, #134)
one or more peripherals; and (Opastrakoon, #130)
a trim controller (Opastrakoon, #113) communicably coupled to the one or more peripherals; and
a processor (Opastrakoon, #117) configured to:
initiate a boot process of the system; (Opastrakoon, [0014] “This can lead to an increase in time to ready (TTR) during power up, a significant reduction in performance immediately during the adjustment cycle as well as over the life of the device, and an increase in risk of error as a result of an interrupted trim update.”; [0016] “Aspects of the present disclosure address the above and other deficiencies by accelerating configuration updates to memory devices.”)
during the boot process, read trim values of the one or more peripherals from the nonvolatile memory, and (Opastrakoon, [0014] “In such implementations, the memory sub-system controller can modify the trim values by reading the trim value from the memory device, adjusting the value, and rewriting the trim value back to the memory device.”)
provide the trim values (Opastrakoon, #320) to the trim controller, wherein the trim controller is configured to provide the trim values to the one or more peripherals. (Opastrakoon, [0053] “As shown, configuration setting control component 113 of memory subsystem controller 115 can monitor the access operations performed on memory device 130. In various implementations, as described above, configuration setting control component 113 can monitor programming operations 301 performed on memory device 130 until the number of operations satisfies a threshold criterion associated with the configuration setting values (e.g., trim settings). In one embodiment, the threshold criterion is satisfied with the number of operations performed meets or exceeds a threshold value. Thus, the threshold criterion remains unsatisfied when the number of operations performed is below the threshold value. When the threshold criterion has been satisfied, configuration setting control component 113 can send a request 302 to configuration setting manager 134 to adjust the configuration settings 320 of memory device 130. Notably, the single request 302 can cause configuration setting manager 134 to update multiple configuration settings 320 using information included in the request.”)
Opastrakoon fails to explicitly disclose and wherein the trim controller is in an always-on power domain, and the one or more peripherals are in switchable power domains.
However, Mishra teaches wherein the trim controller is in an always-on power domain, and the one or more peripherals are in switchable power domains. (Mishra, [0072] “FIG. 10 illustrates certain aspects of a finite state machine 1000 that can support virtual GPIO in an apparatus. The finite state machine 1000 may monitor state information from a plurality of input sources 1024, including hardware events 1002, configuration parameters 1004, masked data 1006 and/or configuration parameter register addresses 1008.”; [0073] “The finite state machine 1000 may be deployed in an always-on domain to ensure that circuits configured to monitor state and state changes are available when certain input/output states are of interest, including when an active peripheral device is associated with the input/output states of interest. In many implementations, it may be necessary to provide the finite state machine 1000 in the always-on domain to permit reliable monitoring of input/output state.”; [0075] “The finite state machine 1000 may be configured to transmit several different types of packets, and the finite state machine 1000 may select a type of packet in order to optimize latency in the communication link In one example, the finite state machine 1000 may select the packet type based on the GPIO data to be transmitted and an associated configuration of GPIO pins.”)
Mishra is directed to monitoring transfer interfaces. Specifically, Mishra teaches programmable configuration registers wherein, the associated peripheral interfaces must be monitored at all times. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon to incorporate the teachings of Mishra to include the above limitation. Such modification(s) would be motivated to ensure that circuits configured to monitor state changes (i.e. switchable domain peripherals) are available when input/output states are of interest. (Mishra, [0073])
Regarding claim 30, Opastrakoon in view of Mishra disclose The system of claim 1, wherein the trim controller is configured to provide the trim values using a dedicated output for each bit of the trim values, wherein each dedicate output is configured to provide a fixed signal representing the corresponding bit. (Opastrakoon, [0056] “Each updated configuration setting is subsequently stored in a register for that setting value.”; [0062] “Notably, the single request causes the memory device to perform adjustment operations on multiple configuration setting values. As noted above, the request can include information to direct the memory device to apply a multiplier value to one or more configuration adjustment definition equations to perform the adjustment operations on the configuration setting values. Additionally, the request can include information to specify which configuration setting values are to be adjusted by the adjustment operation.”)
Regarding claim 31, Opastrakoon in view of Mishra disclose The system of claim 1, wherein the trim controller is configured to provide the trim values to the one or more peripheral when the one or more peripherals are powered off. (Larsen, [cl.10 ln.10-15] “In one embodiment, this portion is a mini-array that is separate from the main flash array. Upon power-down, a system software routine writes the settings of each volatile register to the flash memory. A flash bit stores the setting for each volatile register. In this manner, the volatile register settings are maintained when the circuit is powered down.”)
Regarding claim 32, Opastrakoon in view of Mishra disclose The system of claim 1, wherein the trim controller is configured to provide the trim values to the one or more peripheral serially. (Opastrakoon, [0023] “The physical host interface can be used to transmit data between the host system 120 and the memory sub-system 110. The host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices 130) when the memory sub-system 110 is coupled with the host system 120 by the physical host interface (e.g., PCIe bus). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120.”)
Claim(s) 3-4, 29, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Opastrakoon in view of Mishra as applied above for claims 1 and 11, and in further view of Larsen et al. (US 6154819 A) and Rowley (US 20210026569 A1).
Regarding claim 29, Opastrakoon in view of Mishra teaches The system of claim 1, further comprising a counter, wherein the trim sector includes first trim registers, second trim registers, (Opastrakoon, #320-1..N, “Configuration Settings")
and a first lock register, wherein the first lock register is configured to unlock the second trim registers, (Larsen, Col. 5 ln. 33-34 “Conversely, a logic low ("0") block set/reset level will cause the corresponding block to be unlocked.”)
wherein the second trim registers are updateable when the second trim registers are unlocked, (Larsen, Col. 2 ln. 58-60 “A locked block is protected against modification from subsequent write or erase operations, while an unlocked block can be programmed or erased.”)
Larsen is directed to protecting memory blocks in a flash memory device. The volatile lock registers taught by Larsen function in a similar manner to the volatile lock register of the present invention. Similar to Opastrakoon, Larsen is directed to modifying configuration registers. This is analogous to the presently claimed invention modifying trim registers and falls in the scope of the broadest reasonable interpretation of the claimed limitations.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon to incorporate the teachings of Larsen to include wherein the trim sector further includes a volatile lock register. Such modification(s) would be motivated to allow real-time protection by minimizing lock and unlock cycle times.
wherein the counter is configured to be initiated upon occurrence of an update to the second trim registers, wherein expiration of the counter causes the first lock register to be relocked, and wherein, when the second trim registers are unlocked, the counter is configured to be restarted upon occurrence of another update to the second trim registers. (Rowley, Fig. 3, [0049] “In some embodiments, the method simply discards the message. In other embodiments, the method may employ a short counter to disable further write requests for a small number of clock cycles. In some embodiments, this counter may be employed to prevent brute force attempts to try all combinations of register values.”)
Rowley is directed to protecting the register file of a device. Rowley’s disclosure of a counter used prevent subsequent writes to a register is similar to the counter of the present invention, where, upon meeting a threshold, writing to a register is prevented. As shown in Fig. 3 and described in par. [0049] of Rowley, upon an occurrence of a write request (drawn to “updating” a register generically), the process of Fig. 3 is performed. The counter disclosed by Rowley meets the claim limitations.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Larsen to incorporate the teachings of Rowley to include a counter configured to be initiated upon occurrence of an update to an application-specific trim register, and expiration of the counter causes the volatile lock register to be relocked. Such modification(s) would be motivated to prevent brute force attacks. (Rowley, [0049])
Regarding claim 35, Opastrakoon in view of Mishra teaches The system of claim 11, further comprising a counter,
wherein the trim controller comprises an immutable aperture, a mutable aperture, and a first lock register, wherein the immutable aperture is configured to hold first trim values, wherein the mutable aperture is configured to hold second trim values, (Opastrakoon, [0012] “The trim settings can include parameters such as the programming signal magnitude (e.g., voltage and/or current level), erase signal magnitude (e.g., voltage and/or current level), sensing signal magnitude (e.g., voltage and/or level), programming signal length, erase signal length, sensing signal length, number of bits per cells, number of programming signals in a programming operation, number of sensing signals in a sensing operation, allowable programming operation rate for a memory device, or other similar information.”; [0040] “At operation 210, the processing logic receives a request to perform an adjustment operation on a set of configuration setting values for a memory device (e.g., memory device 130 in FIG. 1). As noted above, configuration setting values can be implemented as trim values stored in trim registers for a memory device. In various implementations, the configuration settings can be used to customize access operations of the memory device. Also as noted above, a firmware or control component of a memory sub-system controller (e.g., a configuration setting control component 113 of memory sub-system controller 115 in FIG. 1) can control the adjustment of the configuration settings during the lifetime of a memory device based on determined ranges of programming operations (e.g., program/erase cycles) performed on the memory device. These adjustments can be performed to maintain the performance and reliability of the memory device as the device ages.”)
It is noted, according to par. [0021]-[0023] and Fig. 2, Applicant appears to define an “aperture” as a group of registers in memory. Examiner notes, so long as the prior art discloses at least the registers that comprise the aperture, then the prior art meets the claim limitations. In this case, the mutable aperture holds a set of trim registers and the immutable aperture holds another set of trim registers. The only distinction between trim registers is the label “first” and “second”.
wherein the trim controller further comprises a mutable aperture unlock state in which the second trim values are modifiable, (Larsen, Col. 2 ln. 58-60 “A locked block is protected against modification from subsequent write or erase operations, while an unlocked block can be programmed or erased.”)
wherein the first lock register is configured to transition the mutable aperture to the mutable aperture unlock state, (Larsen, Col. 5 ln. 33-34 “Conversely, a logic low ("0") block set/reset level will cause the corresponding block to be unlocked.”)
wherein the counter is configured to be initiated upon occurrence of an update to the mutable aperture, wherein expiration of the counter causes the mutable aperture to exit the mutable aperture unlock state, and wherein, when the mutable aperture is in the mutable aperture unlock state, the counter is configured to be restarted upon occurrence of another update to the mutable aperture. (Rowley, Fig. 3, [0049] “In some embodiments, the method simply discards the message. In other embodiments, the method may employ a short counter to disable further write requests for a small number of clock cycles. In some embodiments, this counter may be employed to prevent brute force attempts to try all combinations of register values.”)
Rowley is directed to protecting the register file of a device. Rowley’s disclosure of a counter used prevent subsequent writes to a register is similar to the counter of the present invention, where, upon meeting a threshold, writing to a register is prevented. As shown in Fig. 3 and described in par. [0049] of Rowley, upon an occurrence of a write request (drawn to “updating” a register generically), the process of Fig. 3 is performed. The counter disclosed by Rowley meets the claim limitations.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Larsen to incorporate the teachings of Rowley to include a counter configured to be initiated upon occurrence of an update to an application-specific trim register, and expiration of the counter causes the volatile lock register to be relocked. Such modification(s) would be motivated to prevent brute force attacks. (Rowley, [0049])
Regarding claim 3, Opastrakoon in view of Larsen and Rowley discloses The system of claim 29, but fails to disclose wherein the trim sector further includes a second lock register.
However, Grafton teaches wherein the trim sector further includes a global lock register (Grafton, [0025] “global lock register”)
Grafton is directed to a security-aware master, where configuration of “slave” peripheral devices is managed by a global lock register, write protection register and other security registers. The “global lock register” of Grafton achieves the desired result of the present invention. While Grafton does not disclose a “trim sector” or “trim values”, Grafton’s “global lock register” is directed to controlling write-protection of registers associated with peripheral devices. The present disclosure is similarly directed to controlling access of registers associated with peripheral devices.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon to incorporate the teachings of Grafton to include wherein the trim sector further includes a global lock register. Such modification would be motivated to prevent access to peripheral devices’ associated registers. (Grafton, [0025])
Regarding claim 4, Opastrakoon in view of Larsen and Rowley disclose The system of claim 3, wherein the second lock register is configured to initiate a second lock mode, and wherein the first trim registers and second trim registers are write-protected in a global lock mode. (Grafton, [0025] “Enabling the global locking register can activate a global lock signal, such that when a lock enable portion of a peripheral's associated control register is set and the global lock signal is recognized, the peripheral blocks further access to its control register.”)
Grafton’s “global lock[ing] register” applies to all peripheral devices, similar to what is claimed. Examiner construes the term “lock” with “write-protection” as they are used interchangeably in par. [0025] of Grafton.
Regarding claim 10, Opakstrakoon in view of Larsen and Rowley discloses The system of claim 1, wherein the trim controller is configured to include configuration and status registers of one or more additional peripherals. (Opastrakoon, #320)
Opastrakoon discloses the configuration registers being included as part of the trim controller, these correspond to the configuration and status registers of the one or more additional peripherals as claimed by Applicant.
Regarding claim 12, Opastrakoon in view of Larsen and Rowley discloses The system of claim 11, wherein the trim values are configured to be provided to the one or more peripherals as sideband signals from the trim controller. (Opastrakoon, Fig. 3 #341-345)
Regarding claim 22, Opastrakoon in view of Larsen, Roweley, and Grafton disclose The system of claim 4, wherein the second lock register is configured to be loaded during a boot sequence of the system. (Opastrakoon, [0014] “This can lead to an increase in time to ready (TTR) during power up, a significant reduction in performance immediately during the adjustment cycle as well as over the life of the device, and an increase in risk of error as a result of an interrupted trim update.”; [0016] “Aspects of the present disclosure address the above and other deficiencies by accelerating configuration updates to memory devices.”)
Since Opastrakoon is being modified to incorporate the “global” lock register (drawn to “second”) of Grafton, and the process of Opastrakoon occurs during power up (drawn to boot), the combination of Opastrakoon in view of Larson, Rowley and Grafton meets the claim limitation.
Regarding claim 23, Opastrakoon in view of Larsen and Rowley disclose The system of claim 1, wherein first trim values of the first trim registers and second trim values of the second trim registers are configured to be stored in a contiguous manner and without any intermediary unused bits. (Opastrakoon, Fig. 3 #320-1…N; [0051] “As shown, memory device 130 can be configured with configuration settings (e.g., trim settings) 320-1 to 320-N, where N is a positive integer. In various implementations, as described above with respect to FIGS. 1-2, configuration settings 320-1 to 320-N can be used to customize the access operations for the memory cells of memory device 130.”)
Regarding claim 28, Opastrakoon in view of Larsen and Rowley disclose The system of claim 11, wherein the first trim values and the second trim values are configured to be stored in a contiguous manner and without any intermediary unused bits. (Opastrakoon, Fig. 3 #320-1…N; [0051] “As shown, memory device 130 can be configured with configuration settings (e.g., trim settings) 320-1 to 320-N, where N is a positive integer. In various implementations, as described above with respect to FIGS. 1-2, configuration settings 320-1 to 320-N can be used to customize the access operations for the memory cells of memory device 130.”)
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Opastrakoon in view of Larsen and Rowley as applied to claim 1 above, and in further view of Shin et al. (US 20150350206 A1).
Regarding claim 9, Opastrakoon in view of Larsen and Rowley disclose The system of claim 1, but fail to disclose wherein the first lock register is configured to unlock the second trim registers in accordance with receiving a valid password.
However, Shin teaches wherein the volatile lock register is configured to unlock the application-specific trim registers in accordance with receiving a valid password. (Shin, Fig. 11 S220/S240, [0106] “In step S240, HMAC authentication may be carried out. Whether to enable the secure WP masking in step S230 may be determined through the HMAC authentication in step S240. WP may be set using a conventional command (e.g., CMD 28) if a WP set enable value of the secure WP configuration masking field is set.”)
Shin is directed to a storage system configured to provide with secure write protection. The authentication method of Shin includes a password protection feature for lock/unlocking a secured register similar to the presently claimed method.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Grafton and Larsen to incorporate the teachings of Shin to include wherein the volatile lock register is configured to unlock the application-specific trim registers in accordance with receiving a valid password. Such modification(s) would be motivated to prevent unauthorized access to write-protected memory. (Shin, [0004])
Regarding claim 21, Opastrakoon in view of Larsen and Rowley disclose The system of claim 1, but fail to explicitly disclose wherein the counter is configured to be restarted in response to a reception of a second valid password.
However, Shin teaches wherein the counter is configured to be restarted in response to a reception of a second valid password. (Shin, Fig. 11 S220/S240, [0106] “In step S240, HMAC authentication may be carried out. Whether to enable the secure WP masking in step S230 may be determined through the HMAC authentication in step S240. WP may be set using a conventional command (e.g., CMD 28) if a WP set enable value of the secure WP configuration masking field is set.”)
Shin is directed to a storage system configured to provide with secure write protection. The authentication method of Shin includes a password protection feature for lock/unlocking a secured register similar to the presently claimed method.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Grafton and Larsen to incorporate the teachings of Shin to include wherein the volatile lock register is configured to unlock the application-specific trim registers in accordance with receiving a valid password. Such modification(s) would be motivated to prevent unauthorized access to write-protected memory. (Shin, [0004])
Regarding claim 24, Opastrakoon in view of Larsen and Rowley disclose The system of claim 11, but fail to explicitly disclose wherein the counter is configured to be restarted in response to a reception of a second valid password.
However, Shin teaches wherein the counter is configured to be restarted in response to a reception of a second valid password. (Shin, Fig. 11 S220/S240, [0106] “In step S240, HMAC authentication may be carried out. Whether to enable the secure WP masking in step S230 may be determined through the HMAC authentication in step S240. WP may be set using a conventional command (e.g., CMD 28) if a WP set enable value of the secure WP configuration masking field is set.”)
Claim(s) 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Opastrakoon in view of Larsen and Rowley as applied to claim 11 above, and in further view of Grafton (US 20150269396 A1).
Regarding claim 14, Opastrakoon in view of Larsen and Rowley discloses The system of claim 11, but fails to disclose wherein the trim sector further comprises a second lock register and wherein the second lock register is configured to initiate a lock state in which the first and second trim values are write-protected.
However, Grafton teaches wherein the trim sector further comprises a global lock and wherein the global lock is configured to initiate a lock state in which the infrastructure and application-specific trim values are write-protected. (Grafton, [0025] “Enabling the global locking register can activate a global lock signal, such that when a lock enable portion of a peripheral's associated control register is set and the global lock signal is recognized, the peripheral blocks further access to its control register.”)
Grafton is directed to a security-aware master, where configuration of “slave” peripheral devices is managed by a global lock register, write protection register and other security registers. The “global lock register” of Grafton achieves the desired result of the present invention.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon to incorporate the teachings of Grafton to include wherein the trim sector further comprises a global lock and wherein the global lock is configured to initiate a lock state in which the infrastructure and application-specific trim values are write-protected. Such modification would be motivated to prevent access to peripheral devices’ associated registers. (Grafton, [0025])
Regarding claim 16, Opastrakoon in view of Larsen, Rowley and Grafton discloses The system of claim 14, wherein the trim controller is further configured to:
export a global lock indicator to the one or more peripherals, wherein one or more internal registers of the one or more peripherals are write-protected in accordance with the exported global lock indicator. (Grafton, [0025] “Enabling the global locking register can activate a global lock signal, such that when a lock enable portion of a peripheral's associated control register is set and the global lock signal is recognized, the peripheral blocks further access to its control register.”)
Regarding claim 25, Opastrakoon in view of Larsen, Rowley and Grafton disclose The system of claim 14, wherein the second lock register is configured to be loaded during a boot sequence of the system. (Opastrakoon, [0014] “This can lead to an increase in time to ready (TTR) during power up, a significant reduction in performance immediately during the adjustment cycle as well as over the life of the device, and an increase in risk of error as a result of an interrupted trim update.”; [0016] “Aspects of the present disclosure address the above and other deficiencies by accelerating configuration updates to memory devices.”)
Since Opastrakoon is being modified to incorporate the “global” lock register (drawn to “second”) of Grafton, and the process of Opastrakoon occurs during power up (drawn to boot), the combination of Opastrakoon in view of Larson, Rowley and Grafton meets the claim limitation.
Claim(s) 17, 19, 20, 36 are rejected under 35 U.S.C. 103 as being unpatentable over Opastrakoon et al. (US 20220284974 A1) filed on 3/2/2021 in view of Mishra et al. (), Shin et al. (US 20150350206 A1) and Sekiya (US 20200366679 A1).
Regarding claim 17, Opastrakoon discloses A method comprising:
receiving a write request for a trim value for a peripheral, wherein the trim value is stored in a trim controller communicably coupled to the peripheral; (Opastrakoon, [0035] “Configuration setting control component 113 can be configured to send a single request to memory device 130 to cause memory device 130 to update its configuration settings.”; Fig. 3 #134)
Opastrakoon fails to explicitly disclose receiving, in accordance with the write request, a password for the trim value;
and in accordance with determining that the received password is valid:
initiating a timeout counter, and updating the trim value in accordance with the write request, wherein the trim value is updateable until the timeout counter elapses, wherein the trim controller is in an always-on power domain, and the peripheral is in a switchable power domain.
Mishra teaches wherein the trim controller is in an always-on power domain, and the peripheral is in a switchable power domain. (Mishra, [0072] “FIG. 10 illustrates certain aspects of a finite state machine 1000 that can support virtual GPIO in an apparatus. The finite state machine 1000 may monitor state information from a plurality of input sources 1024, including hardware events 1002, configuration parameters 1004, masked data 1006 and/or configuration parameter register addresses 1008.”; [0073] “The finite state machine 1000 may be deployed in an always-on domain to ensure that circuits configured to monitor state and state changes are available when certain input/output states are of interest, including when an active peripheral device is associated with the input/output states of interest. In many implementations, it may be necessary to provide the finite state machine 1000 in the always-on domain to permit reliable monitoring of input/output state.”; [0075] “The finite state machine 1000 may be configured to transmit several different types of packets, and the finite state machine 1000 may select a type of packet in order to optimize latency in the communication link In one example, the finite state machine 1000 may select the packet type based on the GPIO data to be transmitted and an associated configuration of GPIO pins.”)
Mishra is directed to monitoring transfer interfaces. Specifically, Mishra teaches programmable configuration registers wherein, the associated peripheral interfaces must be monitored at all times. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon to incorporate the teachings of Mishra to include the above limitation. Such modification(s) would be motivated to ensure that circuits configured to monitor state changes (i.e. switchable domain peripherals) are available when input/output states are of interest. (Mishra, [0073])
Shin teaches receiving, in accordance with the write request, a password for the trim value; and receiving, in accordance with the second write request, a second password;
(Shin, Fig. 11 S220/S240, [0106] “In step S240, HMAC authentication may be carried out. Whether to enable the secure WP masking in step S230 may be determined through the HMAC authentication in step S240. WP may be set using a conventional command (e.g., CMD 28) if a WP set enable value of the secure WP configuration masking field is set.”)
Shin is directed to a storage system configured to provide with secure write protection. The authentication method of Shin includes a password protection feature for lock/unlocking a secured register similar to the presently claimed method.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon to incorporate the teachings of Shin to include receiving, in accordance with the write request, a password for the application-specific trim value. Such modification(s) would be motivated to prevent unauthorized access to write-protected memory. (Shin, [0004])
Sekiya teaches and in accordance with determining that the received password is valid: initiating a timeout counter, and updating the trim value in accordance with the write request, wherein the trim value is updateable until the timeout counter elapses (Sekiya, Fig. 2, [0082] “In the relay apparatus 10, a sequence of the steps S1 to S5 in FIG. 2 may be preferably executed at a predetermined time interval (for instance, at each one second or the like). In this case, after the processes of the steps S1 to S5 in FIG. 2 have been executed in the relay apparatus 10, the authentication process in the step S1 in FIG. 2 is performed again when a built-in timer (not illustrated) indicates that the predetermined time has elapsed, and the steps S3 and S4 or the step S5 is executed according to the authentication result.”)
Sekiya is directed to authenticating communication to a peripheral device. Sekiya’s disclosure of using a timer to revoke authentication after an elapsed threshold time to a peripheral is similar to the presently claimed inventions use of a timer to prevent writing to the trim register. As Opastrakoon discloses one or more peripheral devices, the same steps that apply to one set of trim registers applies to another set for another peripheral device as reasoned above in Response to Arguments.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Shin to incorporate the teachings of Sekiya to include in accordance with determining that the received password is a valid password: initiating a timeout counter, and updating the trim value in accordance with the write request, wherein the trim value is updateable until the timeout counter elapses. Such modification(s) would be motivated to prevent unauthorized access to the peripheral device.
Regarding claim 20, Opastrakoon in view of Shin and Sekiya discloses The method of claim 36, further comprising:
receiving a third write request for a third trim value for a third peripheral; (Opastrakoon, [0035] “Configuration setting control component 113 can be configured to send a single request to memory device 130 to cause memory device 130 to update its configuration settings.”; Fig. 3 #134)
receiving, in accordance with the third write request, a third password; and in accordance with determining that the third password is invalid, initiating a lock state of the third trim value. (Shin, “In step S220, HMAC authentication may be performed. The secure mode in step S210 may be executed through HMAC authentication. The HMAC authentication may be performed as described with reference to FIG. 10. The request may be rejected when HMAC authentication indicates the request is not valid. When HMAC authentication indicates the request is valid, the method proceeds to step S230.”)
As reasoned above, the same steps for each subsequent request apply the same. In this case, the determination is an invalid password.
Regarding claim 36, The method of claim 17, further comprising:
receiving a second write request for a second trim value for a second peripheral; (Opastrakoon, [0035] “Configuration setting control component 113 can be configured to send a single request to memory device 130 to cause memory device 130 to update its configuration settings.”; Fig. 3 #134)
receiving, in accordance with the second write request, a second password; and (Shin, Fig. 11 S220/S240, [0106] “In step S240, HMAC authentication may be carried out. Whether to enable the secure WP masking in step S230 may be determined through the HMAC authentication in step S240. WP may be set using a conventional command (e.g., CMD 28) if a WP set enable value of the secure WP configuration masking field is set.”)
in accordance with determining that the second password is valid:
updating the second trim value in accordance with the second write request, and restarting the timeout counter. (Sekiya, Fig. 2, [0082] “In the relay apparatus 10, a sequence of the steps S1 to S5 in FIG. 2 may be preferably executed at a predetermined time interval (for instance, at each one second or the like). In this case, after the processes of the steps S1 to S5 in FIG. 2 have been executed in the relay apparatus 10, the authentication process in the step S1 in FIG. 2 is performed again when a built-in timer (not illustrated) indicates that the predetermined time has elapsed, and the steps S3 and S4 or the step S5 is executed according to the authentication result.”)
Claim(s) 18 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Opastrakoon in view of Mishra, Shin and Sekiya as applied to claim 17 above, and further in view of Larsen et al. (US 6154819 A).
Regarding claim 18, Opastrakoon in view of Mishra, Shin and Sekiya disclose The method of claim 17, but fail to explicitly disclose wherein an additional trim value for the peripheral remains locked during the update of the trim value.
However, Larsen teaches wherein an additional trim value for the peripheral remains locked during the update of the trim value. (Larsen, “Each of the latches can be individually set or reset by a user using a standard command format.”)
Larsen is directed to protecting memory blocks in a flash memory device. The volatile lock registers taught by Larsen function in a similar manner to the volatile lock register of the present invention. Larsen is capable of accessing individual lock registers so that changing one does not affect the others.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Shin and Sekiya to incorporate the teachings of Larsen to include wherein an additional trim value for the peripheral remains locked during the update of the trim value. Such modification(s) would be motivated to allow real-time protection by minimizing lock and unlock cycle times.
Shin is directed to a storage system configured to provide with secure write protection. The authentication method of Shin includes a password protection feature for lock/unlocking a secured register similar to the presently claimed method.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Grafton and Larsen to incorporate the teachings of Shin to include wherein the volatile lock register is configured to unlock the application-specific trim registers in accordance with receiving a valid password. Such modification(s) would be motivated to prevent unauthorized access to write-protected memory. (Shin, [0004])
Regarding claim 38, Opastrakoon in view of Mishra, Shin and Sekiya disclose The method of claim 17, but fail to teach further comprising providing the trim value to the peripheral when the peripheral is powered down.
However, Larsen teaches providing the trim value to the peripheral when the peripheral is powered down. (Larsen, [cl.10 ln.10-15] “In one embodiment, this portion is a mini-array that is separate from the main flash array. Upon power-down, a system software routine writes the settings of each volatile register to the flash memory. A flash bit stores the setting for each volatile register. In this manner, the volatile register settings are maintained when the circuit is powered down.”)
Larsen is directed to protecting memory blocks in a flash memory device. The volatile lock registers taught by Larsen function in a similar manner to the volatile lock register of the present invention. Larsen is capable of accessing individual lock registers so that changing one does not affect the others.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Shin and Sekiya to incorporate the teachings of Larsen to include wherein an additional trim value for the peripheral remains locked during the update of the trim value. Such modification(s) would be motivated to allow real-time protection by minimizing lock and unlock cycle times.
Claim(s) 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Opastrakoon in view of Larsen and Rowley as applied to claim 11 above, and further in view of Durham (US 20210117342 A1)
Regarding claim 26, Opastrakoon in view of Larsen and Rowley disclose The system of claim 35, but fail to explicitly disclose wherein the mutable aperture has a first size that is larger than a second size of the immutable aperture.
However, Durham teaches wherein the mutable aperture has a first size that is larger than a second size of the immutable aperture. (Durham, [0077] “As shown in FIG. 4, the power size 412 may indicate the number of bits that compose the immutable plaintext portion 414 and the mutable plaintext portion 416. In certain embodiments, the total number of bits that make up the immutable plaintext portion 414 and the mutable plaintext portion 416 may be constant, with the sizes of the respective portions being dictated by the size metadata portion 602. For example, if the power metadata value is 0, there are no mutable plaintext bits and all 32 remaining address bits (immutable plaintext portion 414) are used as a tweak to generate ciphertext portion 404 from an address slice (e.g., a subset of the linear address bits), where the ciphertext portion 404 is adjacent to and more significant than the immutable plaintext portion 414. As a further example, if the power metadata value is 1, then there is one bit of mutable plaintext, if the power metadata value is 2, then there are 2 bits of mutable plaintext, up to 32 bits of mutable plaintext resulting in no immutable plaintext bits (414)…”)
Durham is directed to encoded pointer based data encryption. Durham relates generally to the present disclosure by teaching a set size of an “immutable” and “mutable” region of memory. Durham’s teachings permit the mutable region to be larger than that of the immutable region.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Larsen and Rowley to incorporate the teachings of Durham to include wherein the mutable aperture has a first size that is larger than a second size of the immutable aperture. Such modification(s) would be motivated to proactively block out-of-bound accesses to memory while enforcing cryptographic isolation of memory regions within the memory. (Durham, [0019])
Regarding claim 27, Opastrakoon in view of Larsen, Rowley and Durham disclose The system of claim 26, wherein the first size is double the second size. (Durham, [0077] “As shown in FIG. 4, the power size 412 may indicate the number of bits that compose the immutable plaintext portion 414 and the mutable plaintext portion 416. In certain embodiments, the total number of bits that make up the immutable plaintext portion 414 and the mutable plaintext portion 416 may be constant, with the sizes of the respective portions being dictated by the size metadata portion 602. For example, if the power metadata value is 0, there are no mutable plaintext bits and all 32 remaining address bits (immutable plaintext portion 414) are used as a tweak to generate ciphertext portion 404 from an address slice (e.g., a subset of the linear address bits), where the ciphertext portion 404 is adjacent to and more significant than the immutable plaintext portion 414. As a further example, if the power metadata value is 1, then there is one bit of mutable plaintext, if the power metadata value is 2, then there are 2 bits of mutable plaintext, up to 32 bits of mutable plaintext resulting in no immutable plaintext bits (414)…”)
Durham teaches the size of the mutable portion is traded off with the immutable portion based on a “power” bit-field in the region, and is capable of a configuration wherein the size of the mutable portion is double the size of the immutable portion.
Claim(s) 33 is rejected under 35 U.S.C. 103 as being unpatentable over Opastrakoon in view of Mishra as applied to claim 1 above, and further in view of Colombo et al. (US 20180357012 A1).
Regarding claim 33, Opastrakoon in view of Mishra disclose The system of claim 1, but fail to teach wherein a peripheral of the one or more peripherals is an analog to digital converter (ADC) or digital to analog converter (DAC).
However, Colombo teaches wherein a peripheral of the one or more peripherals is an analog to digital converter (ADC) or digital to analog converter (DAC). (Colombo, [0046] “For example, this applies often to the calibration of analog components of the processing system, such as a temperature sensor, analog-to-digital converter, voltage reference, etc. For example, a voltage monitor threshold level of an analog comparator could be “trimmed” to the exact intended value by adjusting some levels with configuration/calibration data, which are written by the producer of the hardware of the processing systems, e.g. the micro-controller producer.”)
Colombo is directed to protecting the configuration data associated with a processing system. Colombo specifically teaches the processing system may have analog peripheral components such as an analog-to-digital converter in which is configurable through dedicated registers from configuration data. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Mishra to incorporate the teachings of Colombo to include the above limitations. Such modification(s) would be motivated to permit the configuration/calibration/trim data of analog components to be customizable by the processing device. (Colombo, [0047])
Claim(s) 34 is rejected under 35 U.S.C. 103 as being unpatentable over Opastrakoon in view of Mishra as applied to claim 1 above, and further in view of Rowley (US 20210026569 A1).
Regarding claim 34, Opastrakoon in view of Mishra disclose The system of claim 1, but fail to teach wherein a peripheral of the one or more peripherals is a voltage regulator.
However, Rowley teaches wherein a peripheral of the one or more peripherals is a voltage regulator. (Rowley, [0017] “The PMIC (100) has one or more voltage regulators (104) that convert the external power supply to the PMIC (100) to operating voltages used by various components of the device (or devices) powered by the PMIC (100) (e.g., solid-state storage devices, DRAM, etc.).”; [0021] “For example, voltage transition slew rates may be programmable via the I2C interface.”)
Rowley is directed to protecting the register file of a device. Specifically, Rowley teaches peripheral devices which are configurable, and including a voltage regulator. Rowley’s teaching of programmable voltage regulator via a controller falls under the broadest reasonable interpretation of the claimed limitations.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Mishra to incorporate the teachings of Rowley to the above limitations. Such modification(s) would be motivated to allow for programmable control of power functionality. (Rowley, [0006])
Claim(s) 37 is rejected under 35 U.S.C. 103 as being unpatentable over Opastrakoon in view of Mishra, Shin and Sekiyra as applied to claim 17 above, and further in view of Rowley (US 20210026569 A1).
Regarding claim 37, The method of claim 17, wherein the peripheral is a data converter or a voltage regulator. (Rowley, [0017] “The PMIC (100) has one or more voltage regulators (104) that convert the external power supply to the PMIC (100) to operating voltages used by various components of the device (or devices) powered by the PMIC (100) (e.g., solid-state storage devices, DRAM, etc.).”; [0021] “For example, voltage transition slew rates may be programmable via the I2C interface.”)
Rowley is directed to protecting the register file of a device. Specifically, Rowley teaches peripheral devices which are configurable, and including a voltage regulator. Rowley’s teaching of programmable voltage regulator via a controller falls under the broadest reasonable interpretation of the claimed limitations.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Opastrakoon in view of Mishra to incorporate the teachings of Rowley to the above limitations. Such modification(s) would be motivated to allow for programmable control of power functionality. (Rowley, [0006])
2nd Rejection
Claim(s) 1 and 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gulati et al. (US 20160049207 A1, hereinafter Gulati) in view of Rori et al. (US 20200210105 A1, hereinafter Rori).
Regarding claim 1, Gulati discloses a system comprising:
a processor (¶[0031], "SoC 10 include central processing unit (CPU)");
a memory comprising a sector (¶[0063], "SoC reconfiguration circuit 46 may be configured to store the programmable configuration data 56 for memory controller 22 and other components of SoC 10, to reprogram various components responsive to powering the components back up from a powered off state. Alternatively, configuration data 56 may be stored in memory 42, or in a combination of memory 42 and SoC reconfiguration circuit 46. Configuration data 56 may be written to the circuit 46 by CPU processors 30, e.g. as part of programming the corresponding component. That is, CPU processors 30 (executing operating system software, for example, as part of the boot of the device and/or at other times when the configuration is changed) may write configuration data 56 to SoC reconfiguration circuit 46. Alternatively, in some embodiments, SoC reconfiguration circuit 46 may have hardware that monitors and shadows a state of configuration of memory controller 22 and the other components of SoC 10" - shadowing implies reading memory values from another memory, see ¶[0064], "Configuration data 56 may include a series of register addresses to be written and the data to write to those registers"; see also ¶[0067], "For example, operating system software executing on the CPU processors 30 may capture the programmable configuration in memory 12 prior to powering down. The restoration of programmable configuration data stored in memory 12 may be performed by SoC reconfiguration circuit 46");
one or more peripherals (¶[0063], "memory controller 22 and other components of SoC 10"); and
a controller external to the one or more peripherals (Fig. 1, element 16, an always on component connected to MC 22 and other components) and
communicably coupled to the one or more peripherals (Fig. 1, element 16, an always on component connected to MC 22 and other components via communication fabric), the trim controller configured to:
receive, for each of the one or more peripherals, values of the one or more peripherals from the sector of the memory (¶[0063], "SoC reconfiguration circuit 46 may be configured to store the programmable configuration data 56 for memory controller 22 and other components of SoC 10, to reprogram various components responsive to powering the components back up from a powered off state. Alternatively, configuration data 56 may be stored in memory 42, or in a combination of memory 42 and SoC reconfiguration circuit 46. Configuration data 56 may be written to the circuit 46 by CPU processors 30, e.g. as part of programming the corresponding component. That is, CPU processors 30 (executing operating system software, for example, as part of the boot of the device and/or at other times when the configuration is changed) may write configuration data 56 to SoC reconfiguration circuit 46. Alternatively, in some embodiments, SoC reconfiguration circuit 46 may have hardware that monitors and shadows a state of configuration of memory controller 22 and the other components of SoC 10" - shadowing implies reading memory values from another memory, see ¶[0064], "Configuration data 56 may include a series of register addresses to be written and the data to write to those registers"; ¶[0067], "For example, operating system software executing on the CPU processors 30 may capture the programmable configuration in memory 12 prior to powering down. The restoration of programmable configuration data stored in memory 12 may be performed by SoC reconfiguration circuit 46"), and
provide the values to the one or more peripherals (¶[0063], "SoC reconfiguration circuit 46 may be configured to store the programmable configuration data 56 for memory controller 22 and other components of SoC 10, to reprogram various components responsive to powering the components back up from a powered off state"; ¶[0064], "SoC reconfiguration circuit 46 may include logic circuitry configured to process configuration data 56 and to write the data to corresponding components in SoC 10 after SoC 10 is powered up again"),
wherein the controller is in an always-on power domain (¶[0033], "dotted line 34 separating always-on component 16 from the other components may indicate an independent power domain for always-on component 16"), and
the one or more peripherals are in switchable power domains (¶[0033], "Similarly, in the illustrated embodiment, dotted line 36 may represent another independent power domain for memory controller 22 and clock gen 24. Other components, groups of components, and/or subcomponents may have independent power domains as well. Generally, a power domain may be configured to receive supply voltage (i.e. be powered on) or not receive supply voltage (i.e. be powered off) independent of other power domains. In some embodiments, power domains may be supplied with different supply voltage magnitudes concurrently. This independence may be implemented in a variety of fashions. For example, the independence may be implemented by providing separate supply voltage inputs from PMU 15, by providing power switches between the supply voltage inputs and components and controlling the power switches for a given domain as a unit, and/or a combination of the above. There may be more power domains than those illustrated in FIG. 1 as well. For example, CPU complex 14 may have an independent power domain (and each CPU processor 30 may have an independent power domain as well) in one embodiment. Peripheral components 18A-18B may be in one or more independent power domains in other embodiments").
Gulati does not disclose that memory is a nonvolatile memory; that the sector is a trim sector; that the controller is a trim controller; and that the values are trim values.
Rori discloses that the memory may be a nonvolatile memory comprising a trim sector (¶[0046], "With respect to trim storage, several options are available. As noted above, the memory controller 210 can be configured to store the trims within itself, in fact static storage media. This option can be useful between sleep and wake cycles of a device, such as a mobile phone. In an example, the array controller 220 can be configured to store trims in the array 225 and provide them to the memory controller 210 upon request. This arrangement is useful when, for example, the device is shut down and the memory controller's fast static media is cleared. It can also be useful when the memory controller 210 uses its fast static storage media for other purposes, evicting trim data"; ¶[0021], "Generally, when a NAND array is powered-up, controller circuitry in the array (e.g., an array controller) loads trim sets (e.g., from internal ROM or from the NAND array)" (ROM memory is non-volatile));
that the controller is a trim controller (¶[0041], "memory controller 210 is arranged to send an accelerated trim command to the array controller 220, which the array controller 220 is configured to recognize. It is via this accelerated trim command that the array controller 220 is made aware the traditional initialization procedure will be altered. In an example, the accelerated trim command is one of two types of accelerated trim commands, with the first type being a partial type and the second type being a complete type. More details of these two types are described below, however, it is sufficient to understand that the partial type implies that the array controller 220 will be responsible for loading some, but not all, trims—the remaining trims being handled by the memory controller 210—and the complete type implies that the memory controller 210 will process and load all of the trims that will be set"); and
that the values are trim values (¶[0041], "trims"; ¶[0020], "A trim is a value or parameter used by hardware or firmware to change electronic functionality such as speed, power, endurance, reliability, etc.").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Gulati and Rori to arrive at a system in which memory is a nonvolatile memory; the sector is a trim sector; the controller is a trim controller; and the values are trim values.
One of ordinary skill in the art would have been motivated because it would enable "enable robust, accurate, and consistent data storage" (Rori, ¶[0020]).
Regarding claim 10, the combined teachings of Gulati and Rori disclose the invention substantially as applied to claim 1, above, wherein the trim controller is configured to include configuration (Rori, ¶[0020], "A trim is a value or parameter used by hardware or firmware to change electronic functionality such as speed, power, endurance, reliability, etc.") and
status registers of one or more additional peripherals (Gulati, ¶[0067], "For example, operating system software executing on the CPU processors 30 may capture the programmable configuration in memory 12 prior to powering down. The restoration of programmable configuration data stored in memory 12 may be performed by SoC reconfiguration circuit 46").
Regarding claim 11, Gulati discloses a system comprising:
a memory comprising a sector (¶[0063], "SoC reconfiguration circuit 46 may be configured to store the programmable configuration data 56 for memory controller 22 and other components of SoC 10, to reprogram various components responsive to powering the components back up from a powered off state. Alternatively, configuration data 56 may be stored in memory 42, or in a combination of memory 42 and SoC reconfiguration circuit 46. Configuration data 56 may be written to the circuit 46 by CPU processors 30, e.g. as part of programming the corresponding component. That is, CPU processors 30 (executing operating system software, for example, as part of the boot of the device and/or at other times when the configuration is changed) may write configuration data 56 to SoC reconfiguration circuit 46. Alternatively, in some embodiments, SoC reconfiguration circuit 46 may have hardware that monitors and shadows a state of configuration of memory controller 22 and the other components of SoC 10" - shadowing implies reading memory values from another memory, see ¶[0064], "Configuration data 56 may include a series of register addresses to be written and the data to write to those registers"; see also ¶[0067], "For example, operating system software executing on the CPU processors 30 may capture the programmable configuration in memory 12 prior to powering down. The restoration of programmable configuration data stored in memory 12 may be performed by SoC reconfiguration circuit 46");
one or more peripherals (¶[0063], "memory controller 22 and other components of SoC 10");
a trim controller communicably coupled to the one or more peripherals (Fig. 1, element 16, an always on component connected to MC 22 and other components via communication fabric); and
a processor configured to: initiate a boot process of the system (¶[0057], "always-on component 16 may include processor 40"; ¶[0060], "processor 40 may be configured to wake memory controller 22 to update memory 12 and/or to wake SoC 10"; ¶[0061], "Processor code/data 54 may be initialized upon boot of a device including SoC 10");
during the boot process, read values of the one or more peripherals from the memory (¶[0063], "SoC reconfiguration circuit 46 may be configured to store the programmable configuration data 56 for memory controller 22 and other components of SoC 10, to reprogram various components responsive to powering the components back up from a powered off state. Alternatively, configuration data 56 may be stored in memory 42, or in a combination of memory 42 and SoC reconfiguration circuit 46. Configuration data 56 may be written to the circuit 46 by CPU processors 30, e.g. as part of programming the corresponding component. That is, CPU processors 30 (executing operating system software, for example, as part of the boot of the device and/or at other times when the configuration is changed) may write configuration data 56 to SoC reconfiguration circuit 46. Alternatively, in some embodiments, SoC reconfiguration circuit 46 may have hardware that monitors and shadows a state of configuration of memory controller 22 and the other components of SoC 10", see also ¶[0064], "Configuration data 56 may include a series of register addresses to be written and the data to write to those registers"; ¶[0067], "For example, operating system software executing on the CPU processors 30 may capture the programmable configuration in memory 12 prior to powering down. The restoration of programmable configuration data stored in memory 12 may be performed by SoC reconfiguration circuit 46") and
provide the values to the controller (¶[0063], "SoC reconfiguration circuit 46 may be configured to store the programmable configuration data 56 for memory controller 22 and other components of SoC 10, to reprogram various components responsive to powering the components back up from a powered off state. Alternatively, configuration data 56 may be stored in memory 42, or in a combination of memory 42 and SoC reconfiguration circuit 46. Configuration data 56 may be written to the circuit 46 by CPU processors 30, e.g. as part of programming the corresponding component. That is, CPU processors 30 (executing operating system software, for example, as part of the boot of the device and/or at other times when the configuration is changed) may write configuration data 56 to SoC reconfiguration circuit 46. Alternatively, in some embodiments, SoC reconfiguration circuit 46 may have hardware that monitors and shadows a state of configuration of memory controller 22 and the other components of SoC 10" - shadowing implies reading memory values from another memory, see ¶[0064], "Configuration data 56 may include a series of register addresses to be written and the data to write to those registers"; ¶[0067], "For example, operating system software executing on the CPU processors 30 may capture the programmable configuration in memory 12 prior to powering down. The restoration of programmable configuration data stored in memory 12 may be performed by SoC reconfiguration circuit 46"),
wherein the controller is configured to provide the values to the one or more peripherals (¶[0063], "SoC reconfiguration circuit 46 may be configured to store the programmable configuration data 56 for memory controller 22 and other components of SoC 10, to reprogram various components responsive to powering the components back up from a powered off state"; ¶[0064], "SoC reconfiguration circuit 46 may include logic circuitry configured to process configuration data 56 and to write the data to corresponding components in SoC 10 after SoC 10 is powered up again"), and
wherein the controller is in an always-on power domain (¶[0033], "dotted line 34 separating always-on component 16 from the other components may indicate an independent power domain for always-on component 16"), and
the one or more peripherals are in switchable power domains (¶[0033], "Similarly, in the illustrated embodiment, dotted line 36 may represent another independent power domain for memory controller 22 and clock gen 24. Other components, groups of components, and/or subcomponents may have independent power domains as well. Generally, a power domain may be configured to receive supply voltage (i.e. be powered on) or not receive supply voltage (i.e. be powered off) independent of other power domains. In some embodiments, power domains may be supplied with different supply voltage magnitudes concurrently. This independence may be implemented in a variety of fashions. For example, the independence may be implemented by providing separate supply voltage inputs from PMU 15, by providing power switches between the supply voltage inputs and components and controlling the power switches for a given domain as a unit, and/or a combination of the above. There may be more power domains than those illustrated in FIG. 1 as well. For example, CPU complex 14 may have an independent power domain (and each CPU processor 30 may have an independent power domain as well) in one embodiment. Peripheral components 18A-18B may be in one or more independent power domains in other embodiments").
Gulati does not disclose that memory is a nonvolatile memory; that the sector is a trim sector; that the controller is a trim controller; and that the values are trim values.
Rori discloses that the memory may be a nonvolatile memory comprising a trim sector (¶[0046], "With respect to trim storage, several options are available. As noted above, the memory controller 210 can be configured to store the trims within itself, in fact static storage media. This option can be useful between sleep and wake cycles of a device, such as a mobile phone. In an example, the array controller 220 can be configured to store trims in the array 225 and provide them to the memory controller 210 upon request. This arrangement is useful when, for example, the device is shut down and the memory controller's fast static media is cleared. It can also be useful when the memory controller 210 uses its fast static storage media for other purposes, evicting trim data"; ¶[0021], "Generally, when a NAND array is powered-up, controller circuitry in the array (e.g., an array controller) loads trim sets (e.g., from internal ROM or from the NAND array)" (ROM memory is non-volatile));
that the controller is a trim controller (¶[0041], "memory controller 210 is arranged to send an accelerated trim command to the array controller 220, which the array controller 220 is configured to recognize. It is via this accelerated trim command that the array controller 220 is made aware the traditional initialization procedure will be altered. In an example, the accelerated trim command is one of two types of accelerated trim commands, with the first type being a partial type and the second type being a complete type. More details of these two types are described below, however, it is sufficient to understand that the partial type implies that the array controller 220 will be responsible for loading some, but not all, trims—the remaining trims being handled by the memory controller 210—and the complete type implies that the memory controller 210 will process and load all of the trims that will be set"); and
that the values are trim values (¶[0041], "trims"; ¶[0020], "A trim is a value or parameter used by hardware or firmware to change electronic functionality such as speed, power, endurance, reliability, etc.").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Gulati and Rori to arrive at a system in which memory is a nonvolatile memory; the sector is a trim sector; the controller is a trim controller; and the values are trim values.
One of ordinary skill in the art would have been motivated because it would enable "enable robust, accurate, and consistent data storage" (Rori, ¶[0020]).
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gulati (US 20160049207 A1) in view of Rori (US 20200210105 A1), and further in view of Chauhan et al. (US 20230046592 A1, hereinafter Chauhan).
Regarding claim 32, the combined teachings of Gulati and Rori disclose the invention substantially as applied to claim 1, above.
The combined teachings of Gulati and Rori does not disclose that the trim controller is configured to provide the trim values to the one or more peripheral serially.
Chauhan discloses the trim controller is configured to provide the trim values to the one or more peripheral serially (¶[0022], "The test/trim circuit 150 is configured to decode trim control messages 120, provided to the IC as a serial bit stream through enable pin 136").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Gulati, Rori and Chauhan to arrive at a system in which the trim controller is configured to provide the trim values to the one or more peripheral serially.
One of ordinary skill in the art would have been motivated because communicating information serially simplifies system design since serial communication is a well-known technique in the art.
Claim(s) 33-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gulati (US 20160049207 A1) in view of Rori (US 20200210105 A1), and further in view of Mandal et al. (US 20180074532 A1, hereinafter Mandal).
Regarding claim 33, the combined teachings of Gulati and Rori disclose the invention substantially as applied to claim 1, above.
The combined teachings of Gulati and Rori does not disclose that a peripheral of the one or more peripherals is an analog to digital converter (ADC) or digital to analog converter (DAC).
Mandal discloses that a peripheral of the one or more peripherals is an analog to digital converter (ADC) or digital to analog converter (DAC) (abstract, "trimming switches provide fine trimming control of a reference output voltage"; ¶[0018], "reference voltage generator 100 generates and provides a reference output voltage to circuits such as power management circuits, power-on-reset (POR) circuits, low voltage detectors, high voltage detectors, ADCs, DACs, and the like").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Gulati, Rori and Mandal to arrive at a system in which a peripheral of the one or more peripherals is an analog to digital converter (ADC) or digital to analog converter (DAC).
One of ordinary skill in the art would have been motivated because the target of an output of a trim controller is a design choice. Choosing an ADC or DAC would be appropriate for applications requiring an ADC or DAC and trimming would ensure their proper operation (Mandal, suggested, ¶[0003], and ¶[0007]).
Regarding claim 34, the combined teachings of Gulati and Rori disclose the invention substantially as applied to claim 1, above.
The combined teachings of Gulati and Rori does not disclose that a peripheral of the one or more peripherals is a voltage regulator.
Mandal discloses that a peripheral of the one or more peripherals is a voltage regulator (abstract, "trimming switches provide fine trimming control of a reference output voltage"; ¶[0018], "reference voltage generator 100 generates and provides a reference output voltage to circuits such as power management circuits, power-on-reset (POR) circuits, low voltage detectors, high voltage detectors, ADCs, DACs, and the like"; ¶[0055], "voltage monitor signal may be used by a supply voltage regulator to calibrate the supply voltage based on the voltage monitor signal").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Gulati, Rori and Mandal to arrive at a system in which a peripheral of the one or more peripherals is a voltage regulator.
One of ordinary skill in the art would have been motivated because the target of an output of a trim controller is a design choice. Choosing an voltage regulator would be appropriate for applications requiring voltage regulation and trimming would ensure their proper operation (Mandal, suggested, ¶[0003], and ¶[0007]).
Claim(s) 17 and 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chauhan (US 20230046592 A1) in view of Gulati (US 20160049207), and further in view of Lambert et al. (US 20110258410 A1, hereinafter Lambert).
Regarding claim 17, Chauhan discloses a method comprising:
receiving a write request for a trim value for a peripheral (¶[0023], "processor or control logic can decode the trim control messages to extract an identifier of the resistor to be trimmed and a trimming value to be used. After the resistor is trimmed to a desired value, that value may be stored in the memory"),
receiving, in accordance with the write request, a password for the trim value (¶[0023], "the processor is configured to recognize an activation code which signals that additional bits transmitted through the enable pin are to be interpreted as resistor trimming messages. The activation code can serve as a password to limit use of the test/trim control circuit 150, so an end user of the circuit does not change the trimming values"); and
updating the trim value in accordance with the write request (¶[0023], "processor or control logic can decode the trim control messages to extract an identifier of the resistor to be trimmed and a trimming value to be used. After the resistor is trimmed to a desired value, that value may be stored in the memory").
Chauhan does not disclose that the trim value is stored in a trim controller communicably coupled to the peripheral; in accordance with determining that the received password is valid: initiating a timeout counter; and wherein the trim value is updateable until the timeout counter elapses, wherein the trim controller is in an always-on power domain, and the peripheral is in a switchable power domain.
Gulait discloses that the trim value is stored in a trim controller communicably coupled to the peripheral (¶[0063], "SoC reconfiguration circuit 46 may be configured to store the programmable configuration data 56 for memory controller 22 and other components of SoC 10, to reprogram various components responsive to powering the components back up from a powered off state. Alternatively, configuration data 56 may be stored in memory 42, or in a combination of memory 42 and SoC reconfiguration circuit 46. Configuration data 56 may be written to the circuit 46 by CPU processors 30, e.g. as part of programming the corresponding component. That is, CPU processors 30 (executing operating system software, for example, as part of the boot of the device and/or at other times when the configuration is changed) may write configuration data 56 to SoC reconfiguration circuit 46. Alternatively, in some embodiments, SoC reconfiguration circuit 46 may have hardware that monitors and shadows a state of configuration of memory controller 22 and the other components of SoC 10" - shadowing implies reading memory values from another memory, see ¶[0064], "Configuration data 56 may include a series of register addresses to be written and the data to write to those registers"; ¶[0067], "For example, operating system software executing on the CPU processors 30 may capture the programmable configuration in memory 12 prior to powering down. The restoration of programmable configuration data stored in memory 12 may be performed by SoC reconfiguration circuit 46" - in combination with Chauhan, the value may be a trim value);
wherein the trim controller is in an always-on power domain, and the peripheral is in a switchable power domain (¶[0033], "dotted line 34 separating always-on component 16 from the other components may indicate an independent power domain for always-on component 16. Similarly, in the illustrated embodiment, dotted line 36 may represent another independent power domain for memory controller 22 and clock gen 24. Other components, groups of components, and/or subcomponents may have independent power domains as well. Generally, a power domain may be configured to receive supply voltage (i.e. be powered on) or not receive supply voltage (i.e. be powered off) independent of other power domains. In some embodiments, power domains may be supplied with different supply voltage magnitudes concurrently. This independence may be implemented in a variety of fashions. For example, the independence may be implemented by providing separate supply voltage inputs from PMU 15, by providing power switches between the supply voltage inputs and components and controlling the power switches for a given domain as a unit, and/or a combination of the above. There may be more power domains than those illustrated in FIG. 1 as well. For example, CPU complex 14 may have an independent power domain (and each CPU processor 30 may have an independent power domain as well) in one embodiment. Peripheral components 18A-18B may be in one or more independent power domains in other embodiments").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Chauhan and Gulati to arrive at a system in which the trim value is stored in a trim controller communicably coupled to the peripheral; wherein the trim controller is in an always-on power domain, and the peripheral is in a switchable power domain.
One of ordinary skill in the art would have been motivated because it would reduce "latency associated with re-initializing" a circuit (Gulati, ¶[0030]).
The combined system of Chauhan and Gulati does not disclose that in accordance with determining that the received password is valid: initiating a timeout counter; and wherein the trim value is updateable until the timeout counter elapses.
Lambert discloses in accordance with determining that the received password is valid: initiating a timeout counter; and wherein the trim value is updateable until the timeout counter elapses (claim 14, "passing the private key to a cryptography engine; receiving an indication that the private key is authenticated from the cryptography engine; setting the host mapped GPIO register to an unlock state when the private key is authenticated; and setting the shared memory to a full read and write accessible state when the private key is authenticated"; claim 16, "determining that a specific amount of time has occurred; setting the host mapped GPIO register in the locked state when the specific amount of time has occurred; and setting a shared memory to a write protected state when the specific amount of time has occurred").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Chauhan, Gulati and Lambert to arrive at a system in which in accordance with determining that the received password is valid: initiating a timeout counter; and wherein the trim value is updateable until the timeout counter elapses.
One of ordinary skill in the art would have been motivated because it would improve security by preventing an update period from being indefinite.
Regarding claim 38, the combined teachings of Chauhan, Gulati and Lambert disclose the invention substantially as applied to claim 17, above, further comprising providing the trim value to the peripheral when the peripheral is powered down (Gulati, ¶[0037], "Using this memory-only communication mode, always-on component 16 may be able to access memory 12 and take advantage of the significant storage available in memory 12 while expending a relatively low amount of energy/power, since the remainder of SoC 10 remains powered down. Always-on component 16 may store programmable configuration data for memory controller 22, so that always-on component 16 may program memory controller 22 once power is restored. That is, always-on component 16 may be configured to program memory controller 22 in a manner similar to the way the operating system would program memory controller 22 during boot of the device including SoC 10. The programmable configuration data stored by the always-on component 16 may be the configuration data that was in memory controller 22 when SoC 10 (except for always-on component 16) was most recently powered down, in one embodiment. In another embodiment, the programmable configuration data may be a configuration that is known to work for any previous configuration of memory controller 22 and/or any configuration of memory 12. The known-good configuration may, e.g., be a configuration that is acceptable in performance for the memory accesses by always-on component 16").
Claim(s) 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chauhan (US 20230046592 A1) in view of Gulati (US 20160049207), and further in view of Lambert (US 20110258410 A1) and Chauhan (US 20230046592 A1).
Regarding claim 37, the combined teachings of Chauhan, Gulati and Lambert disclose the invention substantially as applied to claim 17.
The combined teachings of Chauhan, Gulati, and Lambert do not disclose that the peripheral is a data converter or a voltage regulator.
Mandal discloses that a peripheral is a data converter or a voltage regulator (abstract, "trimming switches provide fine trimming control of a reference output voltage"; ¶[0018], "reference voltage generator 100 generates and provides a reference output voltage to circuits such as power management circuits, power-on-reset (POR) circuits, low voltage detectors, high voltage detectors, ADCs, DACs, and the like"; ¶[0055], "voltage monitor signal may be used by a supply voltage regulator to calibrate the supply voltage based on the voltage monitor signal").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Chauhan, Gulati, Lambert and Mandal to arrive at a system in which a peripheral is a data converter or a voltage regulator.
One of ordinary skill in the art would have been motivated because the target of an output of a trim controller is a design choice. Choosing an voltage regulator would be appropriate for applications requiring voltage regulation and trimming would ensure their proper operation (Mandal, suggested, ¶[0003], and ¶[0007]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20150362980 A1, which discloses "A system on a chip (SOC) may include a component that remains powered when the remainder of the SOC is powered off. The component may be configured to power up other components of the SOC while keeping the central processing unit (CPU) processors powered down, in order to perform a task assigned to such other component(s)" (abstract).
US 20210357015 A1, which discloses "the enhanced microcontroller 400 may comprise components or peripherals that are not subject to power-reductions of an enhanced-power saving mode. Peripherals that are not subject to the power-reductions of an enhanced-power saving mode may continue to receive the same amount of power, or substantially the same amount, when the enhanced microcontroller 400 is in a power-saving mode. In various embodiments, this may include any peripherals or components that may need to operate at full power to keep the microcontroller running, initialize a wake-up routine, or both. Some embodiments of peripherals that are not subject to power-reductions of the enhanced-power saving mode may be directly coupled V.sub.DD" (¶[0035]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BORIS D GRIJALVA LOBOS whose telephone number is (571)272-0767. The examiner can normally be reached M-F 10:30AM to 6:30PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jorge L Ortiz-Criado can be reached at 571-272-7624. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BORIS D GRIJALVA LOBOS/ Primary Patent Examiner, Art Unit 2496
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