DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is Final and is in response to the claims filed 03/16/2026. Claims 1-20 are currently pending, of which claims 1-20 are currently rejected.
Response to Arguments
Applicant’s arguments filled on 03/16/2026 have been fully considered, but they are not persuasive.
35 U.S.C. 103: Applicant argues in pages 8-10 that Farooqui does not teach the upper shift circuit and the lower shift circuit receiving the same operand. Applicant argues Examiner’s response in Non-final rejection filed on 11/18/2025, and explains “Applicant finds the examiner's rebuttal to be puzzling. On the one hand, the examiner argues that both shifters 340b and 340a receive the same operand, but on the other hand, the examiner concedes that shifter 340b receives the upper portion of an operand while shifter 340a receives the lower portion of the operand, i.e., the shifters 340b and 340a receive different signals. Despite the examiner's seemingly conflicting statements, it is plainly clear from FIG. 7 that the shifters 340b and 340a receive different signals.”
Examiner respectfully disagrees. Claim limitation in claim 1 reads “receiving, by each of an upper shift circuit and a lower shift circuit, an operand for an arithmetic right shift operation”. Farooqui teaches shifters 340b and 340a receiving portions of the same operand a<31:0> representing a binary sum value (i.e., one operand). See Farooqui: Fig. 7 and Column 10 Lines 62-64. Hence, shifters 340b and 340a receive values representing only one operand, and are not interpreted to represent two different operands. There is no limitation in independent claim 1 that limits the operand to be the same signal for both the upper shift circuit and the lower shift circuit.
Applicant further argues in pages 10-12 that Farooqui in view of Desmonds do not teach independent claim 1. Specifically, Applicant argues in page 11 “claim 1 recites a "shift condition." The examiner maps this shift condition to Desmonds' Full Width signal, without explaining why Desmonds' Full Width signal qualifies as a shift condition. Applicant respectfully reminds the examiner that claim 1 expressly defines a shift condition as a condition "in which a portion of, but not all of, the operand could be shifted into bits corresponding to the lower output." The examiner has not carried his burden to show where Desmonds teaches that its Full Width signal indicates the presence of this specific type of condition.”
Examiner respectfully disagrees. Examiner explains in Non-final rejection filed on 11/18/2025 how Farooqui teaches a partition signal 305 (shift condition) which determines LSBs to be shifted from the 16-bit shifter 340b to 16-bit shifter 340a, which teaches the limitations of “in which a portion of, but not all of, the operand could be shifted into bits corresponding to the lower output”. See Non-final rejection: page 5. Additionally, Desmonds teaches a Full Width signal 44 also controlling the shifting of values from the upper half of the operand down to the lower half. Desmonds explains “Control line 44 is connected with AND gates 52, 54, 56 and 58 to control the gating of signals from the upper half of the shift network to the lower half during shifting of full width operands.” See Desmonds: Column 2 Line 66- Column 3 Line 1. Hence, both the Full Width signal taught by Desmonds and the partition signal taught by Farooqui control the amount of bits to be shifter from the upper portion of the operand to the lower portion of the operand. Therefore a combination of Farooqui in view of Desmonds is obvious given that they both disclose bitwise right shifting using upper and lower shift circuits based on a shift signal. See Non-final rejection: pages 5 and 6 for combination and motivation to perform said combination.
Applicant further argues in pages 11-12 that Desmonds does not teach a shift condition being detected responsive to the shift value. Applicant specifically argues in pages 11 and 12 “Because the examiner has mapped the claimed "shift value" to the upper shift count and the claimed "shift condition" to the Full Width signal, Desmonds must teach that the Full Width signal is detected responsive to the upper shift count. But Desmonds actually teaches the opposite in col. 3, II. 19-22, explaining that "in the full width mode, the control signal on line 46 [the Full Width signal] causes an AND gate 74 to transfer the upper shift count to OR gate 76 and thereafter to ranks 24, 26, 28, and 30" (emphasis added). In other words, the Full Width signal simply serves a gating function to determine whether the upper shift count is provided to OR gate 76 or not. Thus, by passing the upper shift count downstream, the Full Width signal enables the detection of the upper shift count-not the other way around.”
Examiner respectfully disagrees. Desmonds teaches the Full Width signal being inputted to AND gate 74 to determine if the network operates in Full Width mode. It is to be understood that logic gates have to detect signals in order to provide an output. Hence, a Full Width signal is inputted to an AND gate (detected) to provide an active output signal. See Page 5 of Non-final rejection filed on 11/18/2025.
Applicant further argues in page 12 that Farooqui and/or Desmonds fail to teach a middle shift circuit shifting part of the operand responsive to the shift condition. Applicant specifically argues “Applicant argued in the most recent response to office action why Farooqui fails to teach this feature, and the examiner has not mounted an argument as to why Desmonds remedies this deficiency in Farooqui.”
Examiner respectfully disagrees. Examiner explains in Non-final rejection filed on 11/18/2025 how Desmonds teaches a “detect a shift condition responsive to the shift value” by using AND gate 74 to detect Full Width signal 44 (shift condition) responsive to the upper shift count 72. See Page 5 of Non-final rejection filed on 11/18/2025. Examiner further explains “Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the AND gates receiving a shift value and a shift condition and the OR gate receiving the output of each AND gate as taught by Desmonds with the partitioned shift right logic circuits and their associated partition control logic (middle shift circuit) using a predetermined shift value as taught by Farooqui”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Apparatus claims 9-16 will be addressed before corresponding method claims 1-8.
Claim 1-4 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Farooqui et al. (U.S. Patent No.: US 6243728 B1), hereinafter “Farooqui”, further in view of Desmonds (U.S. Patent No.: US 3934132 A), hereinafter “Desmonds”.
Regarding Claim 9, Farooqui teaches:
A device, comprising:
an upper shift circuit configured to:
receive an operand for an arithmetic right shift operation (Fig. 7, e.g., shifter 340b (upper shift circuit) receives bits o<31:16> from line 384b, which is part of operand a<31:0> from line 384a-384b);
receive a shift value (Figs. 3 and 7, e.g., Shifter 340b (upper shift circuit) receives shift amount 350 (shift value); Column 10 Lines 62-65); and
provide an upper output responsive to the operand and the shift value (Figs. 3 and 7, e.g., Shifter 340b receives sum output 384b (operand) and shift amount 350 (shift value), and outputs 386b (upper output); Column 6 Lines 64-67 - Column 7 Lines 1-2, e.g., SRR circuit 300 outputs 32 bit result from the shifters based on a 5-bit shift amount);
a lower shift circuit configured to:
receive the operand (Figs. 3 and 7, e.g., Shifter 340a (lower shift circuit) receives operand c<15:0> from line 384a, which is part of operand a<31:0> from line 384a-384b); and provide a lower output responsive to the operand and the shift value (Figs. 3 and 7, e.g., Shifter 340a (lower shift circuit) receives operand 386a and shift value 350, and outputs 386a (lower output); Column 6 Lines 64-67 - Column 7 Lines 1-2, e.g., SRR circuit 300 outputs 32 bit result from the shifters based on a 5-bit shift amount), wherein the upper output concatenated with the lower output is a result of the arithmetic right shift operation (Fig. 7, e.g., Outputs 386 b and a are concatenated to form 32 bit output c<31:0>); and
a middle shift circuit configured to:
detect a shift condition … (Figs. 3 and 7, e.g., Partition Control Block (middle shift circuit) receives partition signal 305 (shift condition)), the condition being in which a portion of, but not all of, the operand could be shifted into bits corresponding to the lower output (Column 7 Lines 16-19, e.g., LSBs shifted out of the 16-bit shifter 340b (upper 16 bits of the operand) are passed down to 16-bit shifter 340a. Amount of LSBs shifted out depending on the shift value.); and
responsive to the shift condition being detected, provide at least a portion of the operand to the lower shift circuit as a selectable input (Column 7 Lines 16-19, e.g., LSBs shifted out of the 16-bit shifter 340b (upper 16 bits of the operand) are passed down to 16-bit shifter 340a; Column 10 Lines 43-46, e.g., Shifted LBSs from upper bits of operand are passed down through bus 378; Column 11 Lines 42-45, e.g., Inputs IN1, IN2 and IN3 receive inputs from 378a, 378b and 378c, which contain shifted LSBs from the upper bits of the operand (portion of the operand); Fig. 8, e.g., inputs IN 1-3 are inputs of multiplexers, hence they are selectable).
Farooqui does not explicitly teach:
detect a shift condition responsive to the shift value…
However, Desmonds teaches:
detect a shift condition responsive to the shift value (Fig. 5, e.g., signal 44 inputs Full Width signal (shift condition) to determine if upper half bits will be inputted to lower half network. Full Width signal is also input to AND gate 74 for AND operation with upper shift count (part of shift value), hence Full Width signal is responsive to the upper count value; Column 3 Lines 15-29)…
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the AND gates receiving a shift value and a shift condition and the OR gate receiving the output of each AND gate as taught by Desmonds with the partitioned shift right logic circuits and their associated partition control logic using a predetermined shift value as taught by Farooqui. One would have been motivated to combine these references because both references disclose bitwise right shifting using upper and lower shift circuits, and Desmonds enhances the model of Farooqui by allowing for the shift value to be determined based on the shift condition. See Desmond Column 3 Lines 15-29.
With Regards to Claim 10, Farooqui in view of Desmonds teach:
The device of claim 9, wherein the upper and lower shift circuits are configured to perform an arithmetic right shift of the operand responsive to the shift value (Farooqui: Column 7 Lines 6-8, e.g., Shifters can perform arithmetic right shift; Fig. 3, e.g., right shifters 340 b and a receive sign bit 356 (specifies arithmetic right shift)).
With Regards to Claim 11, Farooqui in view of Desmonds teach:
The device of claim 9, wherein, responsive to the shift condition not being detected, the middle shift circuit is further configured to provide sign bits of the operand to the lower shift circuit as a selectable input (Farooqui: Column 7 Lines 8-10, e.g., MSBs of shifters are replaced by sign bit; Column 11 Lines 7-11, e.g., Each right shifter 340 b and a can perform 16-bit shift operations, hence shifter 340a (lower shift circuit) can receive sign bit as MSB; Fig. 9B, e.g., Sign bit 356 can be selected by Multiplexers based on the F0 input 614. Sign bits would be inputted to shifter 340a by bus 378; Column 11 Lines 42-45, e.g., Inputs IN1, IN2 and IN3 receive inputs from 378a, 378b and 378c, which can contain sign bits; Fig. 8, e.g., inputs IN 1-3 are inputs of multiplexers, hence they are selectable).
With Regards to Claim 12, Farooqui in view of Desmonds teach:
The device of claim 9, wherein a maximum shift value is 2n - 1 bits and a width of the upper output is 2n-1 bits, n being an integer (Farooqui: Column 10 Lines 64-65, e.g., Shift value is 5 bits. Max shift amount is 11111, or 25-1 = 31; Fig. 7, e.g., Shift amount 350 is <4:0> (5 bits), and output is <31:16> (16 bits). 25-1 = 16), and wherein the shift condition includes a most-significant bit of the shift value being de-asserted, and a next most-significant bit of the shift value being asserted (Farooqui: Column 7 Lines 28 – 36, e.g., 4 LSBs of the shift amount 350 are inputted to decoders, hence MSB of shift amount is inactive (de-asserted). Partition control signal 305 (shift condition) causes the decoder to generate two 16-bit number, or a single 32-bit number with a "1" at the bit position of the decimal value of the shift amount).
With regards to Claim 1-4, they are method versions of the claimed device above (claims 9-12 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Claims 5-6 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Farooqui, in view of Desmonds, in view of Miyadai (U.S. Patent Application Publication No.: US 20180226970 A1), hereinafter “Miyadai”, further in view of Dao et al. (U.S. Patent Application Publication No.: US 20150378678 A1), hereinafter “Dao”.
With regards to Claim 13, Farooqui in view of Desmonds teaches the device of claim 9,
Farooqui in view of Desmonds also teaches:
and the shift condition includes a most-significant bit of SLx being de-asserted, and a next most- significant bit of SLx being asserted (Farooqui: Column 7 Lines 30-31, e.g., MSB of shift amount is inactive (de-asserted); Fig. 4, e.g., 4 remaining LSBs of shift amount are inputs of 4x16 decoder, hence the next MSB of the shift amount can be active (asserted)).
Farooqui in view of Desmonds does not teach:
wherein: a width of the upper output is x bits; x is not a power of 2; 2n-1 is a next power of 2 greater than x;
an offset is equal to (2n-1-x);the shift value comprises an upper shift value (SHx) and a lower shift value (SLx); SLx is equal to SHx plus the offset;
and the shift condition includes a most-significant bit of SLx being de-asserted, and a next most- significant bit of SLx being asserted.
However, Miyadai teaches:
a width of the upper output is x bits; x is not a power of 2 (Fig. 1, e.g., Output of Shift Circuit 20a is RH[159:33] which is 127 bits (not a power of 2));
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Shift circuit outputting RH[159:33] (127 bits) as taught by Miyadai with upper and lower shifters 340b and 340a as taught by Farooqui. One would have been motivated to combine these references because both references disclose bitwise right shifting partitioned operands divided into upper and lower circuits, and Miyadai enhances the model of Farooqui by allowing for the shifters to output more bits for better accuracy.
Farooqui in view of Desmonds in view of Miyadai do not teach:
2n-1 is a next power of 2 greater than x;
an offset is equal to (2n-1-x);the shift value comprises an upper shift value (SHx) and a lower shift value (SLx); SLx is equal to SHx plus the offset;
However, in the same field of endeavor, Dao teaches exponents representing the range of 0-255 using 8 bits. Dao explains “Eight bits represent the exponent component of the floating point number and provides a range of 256 values (0 to 255) the exponent can represent" ¶0013. Dao uses aligner 320 to align exponents by taking the difference and right shifting operand C. See Fig. 3 and ¶0047. Additionally, Miyadai teaches a subtractor SUB1 used to compute the difference between exponents. See Fig. 3. Miyadai also teaches the shift control circuit running SIMD more, where the MSB SAL1[6] (SLx) is set to 1, while MSB of SAH1[6] is set to 0. SAL covers the range 64-127, SAH covers range 0-63. See Miyadai: ¶0036 and Fig. 4. Combining the 8 bit wide exponent as taught by Dao with the subtractor taught by Miyadai would yield SAH and SAL being 8 bit wide. SAH would cover range 0-127, and SAL would cover range 128-255. Hence, combination teaches the limitations of:
2n-1 is a next power of 2 greater than x (28-1 = 128);
an offset is equal to (2n-1-x); the shift value comprises an upper shift value (SHx) and a lower shift value (SLx); SLx is equal to SHx plus the offset (MSB SAL1[6] (SLx) is set to 1, while MSB of SAH1[6] is equal to 0. SAH would cover range 0-127, and SAL would cover range 128-255. Using the 8 bits to represent the exponent difference, it is possible for SAH to be 0111111 (127), and 2n-1-x (n=8 from 8 bits to represent exponents as taught by Dao) = 128-127=1. 127 (SAL1[6:0]/SHx) + 1 (offset) = 128 (SAL1[6]/SLx));
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine 8 bit wide exponents as taught by Dao with the subtractor SUB1 as taught by Farooqui in view of Miyadai. One would have been motivated to combine these references because both references disclose bitwise right shifting, and Dao enhances the model of Farooqui in view of Miyadai by allowing for the shifters to shift more values to better align exponents.
With regards to Claim 14, Farooqui in view of Miyadai in view of Dao teach:
The device of claim 13, wherein the upper shift circuit is configured to receive SHx as a control signal, … , and wherein the lower shift circuit is configured to receive SLx as a control signal (Farooqui: Fig. 7, e.g., Upper and lower shift circuits 340 b and a receive shift amount 350 (SHx and SLx)).
Miyadai further teaches:
wherein the middle circuit is configured to receive at least a portion of SLx as a control signal (Fig. 1, e.g., Shift Control Circuit 11 receives SAL[6:0] to generate SAL1[6:0])
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine shift control circuit receiving shift amount SAL[6:0] as taught by Miyadai with the partition control circuit as taught by Farooqui in view of Miyadai in view of Dao. One would have been motivated to combine these references because both references disclose bitwise right shifting partitioned operands divided into upper and lower circuits, and Miyadai enhances the model of Farooqui in view of Miyadai in view of Dao by allowing for the circuit to run in either SIMD mode or in normal mode with a higher accuracy. See ¶0063-0064
With regards to Claims 5 and 6, they are method versions of the claimed device above (claims 13 and 14 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Claims 7-8 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Farooqui, in view of Desmonds, in view of Robinson et al. (U.S. Patent Application Publication No.: US 20190065145 A1), hereinafter “Robinson”.
With regards to Claim 15, Farooqui teaches the device of claim 9. Farooqui does not teach:
wherein the shift condition includes the operand being a double precision operand.
However, Robinson teaches:
wherein the shift condition includes the operand being a double precision operand (¶0064
Operand is a 64 bit input (double precision); Fig. 3, e.g., shifts double precision operand).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the right shifting of 64-bit operand by partitioning it into two 32-bit operands as taught by Robinson with the Right shifters 340 b and a as taught by Farooqui. One would have been motivated to combine these references because both references disclose bitwise right shifting partitioned operands using multiplexers, and Robinson enhances the model of Farooqui in view of Desmonds by allowing right shifting of operands double the size than the size Farooqui proposed for a higher accuracy.
With regards to Claim 16, Farooqui in view of Desmonds in view of Robinson teach:
The device of claim 15, wherein: the shift value comprises an upper shift value (SHx) and a lower shift value (SLx); the upper shift circuit is further configured to: receive a first single precision operand and SHx; and perform an arithmetic right shift of the first single precision operand responsive to SHx to provide a first shifted value as the upper output; and the lower shift circuit is further configured to: receive a second single precision operand and SLx; and perform an arithmetic right shift of the second single precision operand responsive to SLx to provide a second shifted value as the lower output (Farooqui: Fig. 7, e.g., Upper and lower shift circuits 340 b and a receive shift amount 350 (SHx and SLx) and operands 384 b and a. Shifters output 16-bit values 386 b and a (first and second outputs); Robinson: Fig. 3, e.g., Double precision operand is partitioned into two single precision numbers 301 and 302 and right shifted by multiplexers).
With regards to Claims 7 and 8, they are method versions of the claimed device above (claims 15 and 16 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Claims 17 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Farooqui, in view of Desmonds, in view of Miyadai, in view of Dao, further in view of Oklobzija et al. (U.S. Patent No.: US 11442696 B1), hereinafter, “Oklobzija”.
With regards to Claim 17, Farooqui teaches:
A method, comprising: receiving, by each of an upper shift circuit and a lower shift circuit, an operand for an arithmetic right shift operation (Fig. 3, e.g., 16 - bit shifters 340b (Upper shift circuit) and 340a (Lower shift circuit) receive sum outputs 384b and 384a (operand), respectively), wherein the upper shift circuit is configured to provide an upper output, wherein the lower shift circuit is configured to provide a lower output, and wherein the upper output concatenated with the lower output is a result of the arithmetic right shift operation (Fig. 3, e.g., 16 - bit shifters 340b (Upper shift circuit) and 340a (Lower shift circuit) output 386b (Upper output) and 386a (lower output), respectively; Fig. 7, e.g., Outputs 386 b and a are concatenated to form 32 bit output c<31:0>);
providing an upper shift value (SHx) and a lower shift value (SLx) (Figs. 3 and 7, e.g., Shifters 340b (upper shift circuit) and 340a (lower shift circuit) each receive shift amount 350 (upper and lower shift value)),
… detecting a shift condition in which a portion of, but not all of, the operand could be shifted into bits corresponding to the lower output (Column 7 Lines 16-19, e.g., LSBs shifted out of the 16-bit shifter 340b (upper 16 bits of the operand) are passed down to 16-bit shifter 340a. Amount of LSBs shifted out depending on the shift value; Fig. 7);
and responsive to detecting the shift condition, providing, by a middle shift circuit, at least a portion of the operand to the lower shift circuit as a selectable input (Column 7 Lines 16-19, e.g., LSBs shifted out of the 16-bit shifter 340b (upper 16 bits of the operand) are passed down to 16-bit shifter 340a; Column 10 Lines 43-46, e.g., Shifted LBSs from upper bits of operand are passed down through bus 378; Column 11 Lines 42-45, e.g., Inputs IN1, IN2 and IN3 receive inputs from 378a, 378b and 378c, which contain shifted LSBs from the upper bits of the operand (portion of the operand); Fig. 8, e.g., inputs IN 1-3 are inputs of multiplexers, hence they are selectable).
Farooqui does not teach:
wherein a width of the upper output is x bits, wherein x is not a power of 2, wherein 2n-1 is a next power of 2 greater than x;
the method further comprising: calculating an offset equal to (2n-1 - x);
providing an upper shift value (SHx) and a lower shift value (SLx), wherein SLx is equal to SHx plus the offset;
responsive to SLx, detecting a shift condition in which a portion of, but not all of, the operand could be shifted into bits corresponding to the lower output;
However, Desmonds teaches:
responsive to SLx, detecting a shift condition in which a portion of, but not all of, the operand could be shifted into bits corresponding to the lower output; (Fig. 5, e.g., signal 44 inputs Full Width signal (shift condition) to determine if upper half bits will be inputted to lower half network. Full Width signal is also input to AND gate 74 for AND operation with upper shift count (part of shift value), hence Full Width signal is responsive to the upper count value; Column 3 Lines 15-29)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the AND gates receiving a shift value and a shift condition and the OR gate receiving the output of each AND gate as taught by Desmonds with the partitioned shift right logic circuits and their associated partition control logic using a predetermined shift value as taught by Farooqui. One would have been motivated to combine these references because both references disclose bitwise right shifting using upper and lower shift circuits, and Desmonds enhances the model of Farooqui by allowing for the shift value to be determined based on the shift condition. See Desmond Column 3 Lines 15-29.
Farooqui in view of Desmonds do not teach:
wherein a width of the upper output is x bits, wherein x is not a power of 2, wherein 2n-1 is a next power of 2 greater than x;
the method further comprising: calculating an offset equal to (2n-1 - x);
providing an upper shift value (SHx) and a lower shift value (SLx), wherein SLx is equal to SHx plus the offset;
However, Miyadai teaches:
a width of the upper output is x bits; x is not a power of 2 (Fig. 1, e.g., Output of Shift Circuit 20a is RH[159:33] which is 127 bits (not a power of 2));
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Shift circuit outputting RH[159:33] (127 bits) as taught by Miyadai with upper and lower shifters 340b and 340a as taught by Farooqui. One would have been motivated to combine these references because both references disclose bitwise right shifting partitioned operands divided into upper and lower circuits, and Miyadai enhances the model of Farooqui by allowing for the shifters to output more bits for better accuracy.
Farooqui in view of Desmonds in view of Miyadai do not teach:
wherein 2n-1 is a next power of 2 greater than x;
the method further comprising: calculating an offset equal to (2n-1 - x);
… wherein SLx is equal to SHx plus the offset;
However, in the same field of endeavor, Dao teaches exponents representing the range of 0-255 using 8 bits. Dao explains “Eight bits represent the exponent component of the floating point number and provides a range of 256 values (0 to 255) the exponent can represent" ¶0013. Dao uses aligner 320 to align exponents by taking the difference and right shifting operand C. See Fig. 3 and ¶0047. Additionally, Miyadai teaches a subtractor SUB1 used to compute the difference between exponents. See Fig. 3. Miyadai also teaches the shift control circuit running SIMD more, where the MSB SAL1[6] (SLx) is set to 1, while MSB of SAH1[6] is set to 0. SAL covers the range 64-127, SAH covers range 0-63. See Miyadai: ¶0036 and Fig. 4. Combining the 8 bit wide exponent as taught by Dao with the subtractor taught by Miyadai would yield SAH and SAL being 8 bit wide. SAH would cover range 0-127, and SAL would cover range 128-255. Hence, it would cover limitations:
2n-1 is a next power of 2 greater than x (28-1 = 128, next power of 2 greater than x (127));
Farooqui in view of Miyadai in view of Dao do not teach:
the method further comprising: calculating an offset equal to (2n-1 - x);
wherein SLx is equal to SHx plus the offset;
However, in the same field of endeavor, Oklobzija teaches how an operand can be passed down to an accumulator when the bits are shifted out of range using a bypass multiplexer. Oklobzija explains: “If the difference between operand exponents is greater than 3, that means that one of the operands shifts to the right over 24 bits, which aligns the operand too far to the right to be within the range of the greater operand. This case is equivalent to adding zero to the greater operand, or simply passing the greater operand to the accumulator unchanged using a bypass multiplexer (FIG. 7c)" Column 14 Lines 15-21. Additionally, Farooqui teaches how LSBs shifted out of the 16-bit shifter 340b (upper 16 bits of the operand) are passed down to 16-bit shifter 340a. See Column 7 Lines 16-19.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine bypass multiplexer to pass operand directly to accumulator if operand shifts outside of range as taught by Oklobzija with the upper and lower shift circuits 340b and 340a as taught by Farooqui in view of Desmonds in view of Miyadai in view of Dao. One would have been motivated to combine these references because both references disclose bitwise right shifting, and Oklobzija enhances the model of Farooqui in view of Desmonds in view of Miyadai in view of Dao by skipping unnecessary shift operations for faster processing. This combination teaches the method further comprising: calculating an offset equal to (2n-1 - x), since the lower shifter 340a would include a bypass multiplexer to directly receive operand shifted out of the upper shift circuit 340b based on a calculation to determine if the value goes out of range (offset), and wherein SLx is equal to SHx plus the offset, since the bypass multiplexer would be active when bits are shifted out of the range to provide it to the next shift circuit. Hence, the lower shift value would be the upper shift amount plus the offset (1 at the MSB position)
With regards to Claim 18, Farooqui in view of Desmonds in view of Miyadai in view of Dao in view of Oklobzija teach:
The method of claim 17, wherein detecting the shift condition includes a most-significant bit of SLx being de-asserted, and a next most-significant bit of SLx being asserted (Farooqui: Column 7 Lines 28 – 36, e.g., 4 LSBs of the shift amount 350 are inputted to decoders, hence MSB of shift amount is inactive (de-asserted). Partition control signal 305 (shift condition) causes the decoder to generate two 16-bit number, or a single 32-bit number with a “1” at the bit position of the decimal value of the shift amount).
With regards to Claim 19, Farooqui in view of Desmonds in view of Miyadai in view of Dao in view of Oklobzija teach the method of Claim 18.
Miyadai further teaches:
wherein detecting the shift condition includes the operand being a double precision operand (Miyadai: Fig. 1, e.g., Operand D[63:0] is a double precision operand).
It would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the right shifting of 64-bit operand by partitioning it into two 32-bit operands as taught by Miyadai with Right shifters 340 b and a as taught by Farooqui in view of Miyadai in view of Dao in view of Oklobzija. One would have been motivated to combine these references because both references disclose bitwise right shifting partitioned operands using multiplexers, and Miyadai enhances the model of Farooqui in view of Miyadai in view of Dao in view of Oklobzija by allowing right shifting of operands double the size than the size Farooqui proposed for a higher accuracy.
With regards to Claim 20, Farooqui in view of Miyadai in view of Dao in view of Oklobzija teach:
The method of claim 17, further comprising: providing SHx as a control signal to the upper shift circuit; … and providing SLx as a control signal to the lower shift circuit (Farooqui: Fig. 7, e.g., Upper and lower shift circuits 340 b and a receive shift amount 350 (SHx and SLx))
Miyadai further teaches:
providing at least a portion of SLx as a control signal to the middle shift circuit (Miyadai: Fig. 1, e.g., Shift Control Circuit 11 receives SAL[6:0] to generate SAL1[6:0]);
It would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the shift control circuit receiving shift amount SAL[6:0]as taught by Miyadai with the partition control circuit as taught by Farooqui in view of Miyadai in view of Dao in view of Oklobzija. One would have been motivated to combine these references because both references disclose bitwise right shifting partitioned operands using multiplexers, and Miyadai enhances the model of Farooqui in view of Miyadai in view of Dao in view of Oklobzija by allowing for the circuit to run in either SIMD mode or in normal mode. See Miyadai ¶0063-0064.
Prior Art Made of Record
US 12591412 B1 – teaches performing left and right shift of a first numeric input by a number of bits indicated by second numeric input. See Fig. 1 and corresponding description.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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