Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Remarks
The Examiner acknowledges the applicant’s remarks, including amendments to claims 1-3, and newly added claims 6-11.
35 U.S.C. 112(b)
The Examiner acknowledges the amendments made to claims 1-3. The Examiner withdraws 112(b) rejections from claims 1-3 due to amendments to the claims.
35 U.S.C. 103
The Examiner acknowledges and has fully considered the applicant’s arguments. The applicant makes arguments, (Remarks page 9 – page 16), which includes the combination of Willcock, (U.S.
Patent Application Publication 2022/0171605 A1), hereinafter, “Willcock”, and Korthikanti et al.
(U.S. Patent Application Publication 2018/0189236 A1), hereinafter, “Korthikanti” having different architectures from one another, and that the combination of elements do not work due in part due to the different structures, such as the systolic array which can shift data from one PE to another of Willcock and an array of clusters (PEs) with bi-directional connections between the clusters. The Examiner is persuaded by the applicant’s arguments and withdraws the 103 rejections made to claims 1-3 due to being persuaded by the applicant’s arguments.
New Claims
The Examiner acknowledges the applicant, (Remarks page 17-18), has added new claims, claims 6-11 to the application. The Examiner further acknowledges that the applicant describes support in the specification for the newly added claims, (Remarks page 17-18), and describes additional limitations in each of the new claims in an effort to suggest they are patentable, (Remarks page 18-19). The Examiner has withdrawn the prior art rejections previously made, including the independent claim 1, see above, as well as the Examiner has withdrawn the 112(b) rejections regarding claims 1-3 due to amendments, see above, which would put the dependent claims, including the newly added claims, 6-11, into a possible patent eligible position over prior art, making the arguments for patentability for the newly added claims, 6-11, moot.
Conclusion
The Examiner acknowledges the applicant’s conclusion statements.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “each channel of the point-to-point link comprises a FIFO buffer” of claim 8, and the “shared memory comprises a plurality of memory banks, each memory bank being connected to a single respective processing element by a respective N-bit access, such that no processing element accesses a memory bank connected to another processing element”, of claim 9 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10, claim 10 recites the limitation of “groups each containing data for a single submatrix”. It is unclear if this limitation is meant to be understood as each group contains data for a same single submatrix, or if it is meant to be understood as each group contains data for a different single submatrix each. For purposes of Examination, the Examiner interprets the limitation as meaning that each group contains data for a different submatrix.
Indication of Allowable Subject Matter
Claims 1-3, 6-9, and 11 are allowed.
Claim 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regards to claim 1, the applicant claims a method of block processing two matrices, with the method comprising:
“A method of block processing two matrices stored in a same shared memory, one being stored by rows and the other being stored by columns, using a plurality of processing elements, where each processing element is connected to the shared memory by a respective N-bit access and to a first adjacent processing element by a bidirectional N-bit point- to-point link, the method comprising the following steps carried out in one processor instruction cycle: receiving, in each of the processing elements a respective different N-bit segment of a same one of the two matrices by a respective memory access; and exchanging, between a given processing element and its first adjacent processing element, by means of a corresponding point-to-point link, N-bit segments of a first of the two matrices, which N-bit segments were previously received in the given processing element and the first adjacent processing element in a previous instruction cycle.”
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Willcock teaches a method of block processing using a plurality of processing elements with processing elements connected to at least two neighboring PEs (Fig. 2). Furthermore Willcock teaches segments from loaders received in the PEs, and shifting that data to a neighboring PE during one clock cycle ([0039] regarding loaders loading submatrix data to cells; [0047] regarding cells hardwired to one another, with the output wire matching the number value for the output bit value; As interpreted by the Examiner, the data input to the processing element is an N-bit access, with Willcock teaching that the output value wires between cells (the bus) match the size of the output, indicating that the segment, or submatrix, is of the same value, thus N-bit segments with connection to loader and connection to the neighboring cells being N-bit in size; [0039]-[0040] regarding loaders connected to buffers to receive submatrices; [0043] regarding a clock cycle in which each cell (as processing elements) can process weight input; [0041] regarding a cell in an array of cells (as processing elements) shifting a submatrix to the neighboring cell to the right in a clock cycle; [0047] regarding cells hardwired to one another, with the output wire matching the number value for the output bit value; As interpreted by the Examiner, the data input to the processing element is an N-bit access, with Willcock teaching that the output value wires between cells (the bus) match the size of the output, indicating that the segment, or submatrix, is of the same value, thus N-bit segments with connection to loader and connection to the neighboring cells being N-bit in size; Fig. 2 items 214 (cell), 215 (cell); [0041] regarding shifting submatrix data to neighboring cell to the right (214 to 215); [0043] regarding processing a given input in each clock cycle, and then shifting data into a neighboring cell). However, Willcock fails to teach or suggest two matrices stored by rows and columns in a shared memory, with each processing element connected to the shared memory. Furthermore, Willcock fails to teach bi-directional or point-to-point communication between the PEs as well as exchanging between the PEs via a point-to-point connection.
Korthikanti teaches matrices stored in a shared memory, as well as the capability of storing matrices by rows or by columns (Fig. 2B items 240 (high bandwidth memory), 230 (clusters as processing elements); [0047] regarding the high bandwidth memory being able to be shared by the processing clusters (230), furthermore regarding the high bandwidth memory able to store and retrieve data in multiple dimensions including rows and columns). Korthikanti further teaches each processing element connected to a shared memory, ([0057] regarding matrix data in high bandwidth memory distributed to each matrix processing cluster; Fig 2B items 240 (High bandwidth memory), 230 (clusters as processing elements)), bi-directional or point-to-point links between processing elements, (Fig. 2B items 230 (array of clusters with bidirectional communication)), and exchanging data between neighboring PEs, ([0056] regarding input matrices partitioned based on number of available processing resources (210), or partitioned across the rows of the matrix operands with each partition distributed to a processing resource. Furthermore, simultaneously sending and receiving data to and from its neighboring processing resources(210); [0121] regarding in each stage, of partial matrix operations, partial results are shifted to a neighbor; Fig. 2B items 230 (array of clusters with bidirectional communication)). However, Korthikanti fails to teach or suggest steps carried out in a single instruction cycle as well as exchanging data between PEs which was received in the PEs in a previous instruction cycle.
Chen et al. (U.S. Patent Application Publication 20180267936 A1), hereinafter, “Chen”, teaches a systolic array of processing elements, with processing elements connected to at least two adjacent neighbors (Fig. 2). Figure 2 of Chen appears to show a bi-directional connection between the array of processing elements, however, [0038] seemingly describes that the processing elements are not bi-directionally connected, but rather are connected in either a direction flowing down/right, or flowing up/left, in a systolic manner. Chen fails to teach or suggest the limitations highlighted above.
Dupont De Dinechin et al. (U.S. Patent Application Publication 20150339256 A1), hereinafter, “Dinechin”, teaches bi-directionally linked processing elements (Fig. 1). Furthermore, Dinechin teaches exchanging data between processing elements in one instruction cycle, (Fig. 4; [0077]-[0084]). However, Dinechin fails to teach or suggest the limitations highlighted above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.A.K./Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182