Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-2, 4-6, 9-12, 14-15, 19-20, and 23-29 are pending. Claims 3, 7-8, 13, 16-18, and 21-22 are canceled by Applicant.
Examiner Notes
Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant’s claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The prompt development of a clear issue requires that the replies of the Applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
As per claim 1, it is objected to because in ll. 2-3, “an internal hardware resource” should be “a hardware resource internal to the controller”.
As per claim 12, it is objected to because in ll. 3-4, “the controller being associated with an internal memory” should be “the controller having a memory internal to the controller”.
As per claim 15, “first one or more signals” should be “first signal”.
As per claim 20, it is objected to because in ll. 2-3, “at least one internal hardware resource of the apparatus” should be “at least one hardware resource internal to the apparatus”.
35 USC § 112(f) – Claim Interpretation
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f), is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) (i.e., claim 20, “means for pre-emptively changing” and claims 23-26, “means for changing” / “means for dynamically changing”), except as otherwise indicated in an Office action (e.g., see at least [0005] and [0095]-[0096] of the instant specification). Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 11-12, 14-15, 20, and 24-29 are rejected under 35 U.S.C. 103 as being unpatentable over
Biswas et al. (US 2014/0095777) (hereinafter Biswas as previously cited) in view of
Jeter et al. (US 2018/0074743) (hereinafter Jeter as previously cited) in view of
Jarrar et al. (US 2014/0002132) (hereinafter Jarrar as previously cited).
As per claim 1, Biswas primarily teaches the invention as claimed including an electronic device (Biswas fig. 1, block 10 electronic device), comprising:
a controller (Biswas fig. 1, block 14 memory controller) comprising an internal hardware resource (Biswas fig. 1, block 16 system cache internal to the memory controller), the internal hardware resource having a first partition and a second partition different from the first partition (Biswas abstract system cache is divided into multiple small sections), wherein the first partition the first partition is in a second readiness state, the second readiness state that is different from the first readiness state (Biswas [0008] cache may be divided into multiple small sections and the power supplied to each section may be controlled independently of the other sections. If a section is inactive, then the voltage supplied to the inactive section may be reduced to a first voltage sufficient for retention. Prior to being accessed, the voltage supplied to the section may be increased to a second voltage which is higher than the first voltage); and
a readiness component (Biswas fig. 2, blocks 34 and 46 switch interface and memory controller switch) associated with the controller and operable to:
receive a parameter associated with an upcoming workload for the controller, the parameter being associated with a parameter value (Biswas [0088] total number of requests stored in a queue); and
when the parameter value is greater than at least one threshold ([0088] it may be determined if the total number of requests that are stored in the queue assigned to the given section have reached a predetermined threshold);
send a first signal to the first partition (Biwas [0021] well-known signals and [0040] signal definitions and electrical properties), the first signal pre-emptively changing the second readiness state of the first partition to the first readiness state to increase a first amount of power consumed by the first partition (Biswas abstract incoming requests are grouped together based on which section of the system cache they target. When enough requests that target a given section have accumulated, the voltage supplied to the given section is increased to a voltage sufficient for access. Then, once the given section has enough time to ramp-up and stabilize at the higher voltage, the waiting requests may access the given section in a burst of operations and [0008] prior to being accessed, the voltage supplied to the section may be increased to a second voltage which is higher than the first voltage); and
send
a second signal to the second partition (Biwas [0021] well-known signals and [0040] signal definitions and electrical properties), the second signal pre-emptively changing the third readiness state of the second partition to the second readiness state to increase a second amount of power consumed by the second partition ([0088] when the number of requests in the queue is greater than a threshold then increase voltage supplied to a given section of the cache memory being targeted by the requests and allow the requests to access the given section of memory and fig. 8, blocks 172, 174, 182, and 184 responsive to the number of requests in the queue being greater than a threshold, increase voltage supplied to the given section to be accessed by the requests, wait for ramp-up delay before accessing the given section, and then access the given section in a burst of operations).
Biswas does not explicitly teach:
an ordered sequence of readiness states consisting of the first readiness state, the second readiness state, and the third readiness state that is different from the first readiness state and the second readiness state,
the first readiness state is sequential with the second readiness state in the ordered sequence of readiness states and the second readiness state is sequential with the third readiness state in the ordered sequence of readiness states,
the second partition is in the third readiness state, and
a set of thresholds.
However, Jeter teaches a set of thresholds (Jeter [0050] monitor number of incoming memory requests and number of requests stored in the pending request queues and compare these numbers to various thresholds).
Jeter and Biswas are both concerned with computer memory management and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Biswas in view of Jeter because it would provide for improved memory controller power management techniques. If the queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device is reduced. The clock frequency is reduced by one half if the queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.
Biswas in view of Jeter do not explicitly teach:
an ordered sequence of readiness states consisting of the first readiness state, the second readiness state, and the third readiness state that is different from the first readiness state and the second readiness state,
the first readiness state is sequential with the second readiness state in the ordered sequence of readiness states and the second readiness state is sequential with the third readiness state in the ordered sequence of readiness states,
the second partition is in the third readiness state.
However, Jarrar teaches:
an ordered sequence of readiness states consisting of the first readiness state, the second readiness state, and the third readiness state that is different from the first readiness state and the second readiness state (Jarrar fig. 9 at least three different adjacent power modes in an ordered sequence; [0057] signals for various logic modules are used to transition the modules of the memory to different power states; and [0075] transition between immediately adjacent power modes); and
the first readiness state is sequential with the second readiness state in the ordered sequence of readiness states and the second readiness state is sequential with the third readiness state in the ordered sequence of readiness states (Jarrar fig. 9 at least three different adjacent power modes in an ordered sequence; [0057] signals for various logic modules are used to transition the modules of the memory to different power states; and [0075] transition between immediately adjacent power modes),
the second partition is in the third readiness state (Jarrar fig. 9 at least three different adjacent power modes in an ordered sequence; [0057] signals for various logic modules are used to transition the modules of the memory to different power states; and [0075] transition between immediately adjacent power modes).
Jarrar and Biswas are both concerned with computer memory management and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Biswas in view of Jeter in view of Jarrar because it would provide for a way to transition an integrated circuit die between power modes by transitioning logic modules of the integrated circuit between power states without intervention by the logic modules.
As per claim 2, Biswas further teaches wherein the at least one internal hardware resource comprises an internal memory (fig. 1, block 16).
As per claim 4, Biswas further teaches wherein the third readiness state is a standby state for the second partition ([0008] inactive memory section and [0060] pending state for each cache line).
As per claim 5, Jeter teaches wherein the signal gates a clock signal for the first partition ([0005] and [0033] memory power gating exit).
As per claim 11, Biswas further teaches wherein the parameter comprises a command queue depth ([0088] total number of requests stored in a queue).
As per claim 12, it has similar limitations as claim 1 and is therefore rejected using the same rationale as claim 1. Biswas further teaches receiving a command from a host device (Biswas fig. 8, block 162 and [0066] host electronic device); and storing the command in a command queue of a controller (Biswas fig. 8, block 170).
As per claim 14, Biswas teaches wherein at least one power state of the sequence of power states is a standby state ([0008] inactive memory section and [0060] pending state for each cache line).
As per claim 15, Jeter teaches wherein the first one or more signals gates a clock signal for the first partition ([0005] and [0033] memory power gating exit).
As per claim 20, it has similar limitations as claim 1 and is therefore rejected using the same rationale as claim 1.
As per claim 24, the combination of references above teaches means for changing the second readiness state of the second partition to the first readiness state In the ordered sequence of readiness states (Jarrar fig. 9 at least three different adjacent power modes in an ordered sequence; [0057] signals for various logic modules are used to transition the modules of the memory to different power states; and [0075] transition between immediately adjacent power modes) when the value of one or more additional parameters exceeds at least one threshold of the set of thresholds, thereby increasing the second amount of power used by the second partition (Biswas fig. 8, blocks 162-174 and [0088] when the number of requests in the queue is greater than a threshold then increase voltage supplied to a given section of the cache memory being targeted by the requests and allow the requests to access the given section of memory).
As per claim 25, Biswas further teaches means for changing the first readiness state of the first partition back to the second readiness state when the value of one or more additional parameters is less than at least one threshold of a set of thresholds, thereby decreasing the first amount of power used by the first partition (abstract when a section of memory is not being accessed i.e., the number of requests in the queue is less than the threshold, then reduce the voltage to the section of memory not being accessed; [0008] if a section is inactive, then the voltage supplied to the inactive section may be reduced; [0075]-[0076] if a section is not being accessed, the voltage supplied to the section may be the lower supply voltage; [0080] separate power supply for each memory section which may either be high or low voltage depending on the size of a queue of requests for each respective memory section).
As per claim 26, the combination of references above teaches means for changing at least one of the second readiness state of the first partition to the third readiness state and the third readiness state of the second partition to a fourth readiness state that is sequential with the third readiness state in the ordered sequence of readiness states (Jarrar fig. 9 at least three different adjacent power modes in an ordered sequence; [0057] signals for various logic modules are used to transition the modules of the memory to different power states; and [0075] transition between immediately adjacent power modes) when the parameter value is less than at least one threshold of the set of thresholds (Biswas abstract when a section of memory is not being accessed i.e., the number of requests in the queue is less than the threshold, then reduce the voltage to the section of memory not being accessed; [0008] if a section is inactive, then the voltage supplied to the inactive section may be reduced; [0075]-[0076] if a section is not being accessed, the voltage supplied to the section may be the lower supply voltage; [0080] separate power supply for each memory section which may either be high or low voltage depending on the size of a queue of requests for each respective memory section).
As per claim 27, the combination of references above teaches wherein the controller is further configured to send a third signal to at least one of the first partition and the second partition (Biwas [0021] well-known signals and [0040] signal definitions and electrical properties), the third signal changing at least one of the second readiness state of the first partition to the third readiness state and the third readiness state of the second partition to a fourth readiness state In the ordered sequence of readiness states (Jarrar fig. 9 at least three different adjacent power modes in an ordered sequence; [0057] signals for various logic modules are used to transition the modules of the memory to different power states; and [0075] transition between immediately adjacent power modes) when the parameter value is less than at least one threshold of the set of thresholds, to decrease an amount of power consumed by the at least one of the first partition and the second partition (Biswas abstract when a section of memory is not being accessed i.e., the number of requests in the queue is less than the threshold, then reduce the voltage to the section of memory not being accessed; [0008] if a section is inactive, then the voltage supplied to the inactive section may be reduced; [0075]-[0076] if a section is not being accessed, the voltage supplied to the section may be the lower supply voltage; [0080] separate power supply for each memory section which may either be high or low voltage depending on the size of a queue of requests for each respective memory section).
As per claim 28, the combination of references above teaches wherein the ordered sequence of states comprises three or more of a power off state (Biswas [0089] power down), a standby state (Jarrar [0004] standby state and [0025] and [0027] sleep state), a clock gated state (Jarrar [0025] gating a power signal used by a logic module), and a ready state (Biswas [0089] power up).
As per claim 29, the combination of references above teaches sending a third signal to at least one of the first partition and the second partition (Biwas [0021] well-known signals and [0040] signal definitions and electrical properties), the third signals changing at least one of the power state of the first partition to the third power state and the third power state of the second partition to a fourth power state in the ordered sequence of power states (Jarrar fig. 9 at least three different adjacent power modes in an ordered sequence; [0057] signals for various logic modules are used to transition the modules of the memory to different power states; and [0075] transition between immediately adjacent power modes) when the parameter value is less than at least one threshold of the set of thresholds thereby decreasing an amount of power consumed by the at least one of the first partition and the second partition (Biswas abstract when a section of memory is not being accessed i.e., the number of requests in the queue is less than the threshold, then reduce the voltage to the section of memory not being accessed; [0008] if a section is inactive, then the voltage supplied to the inactive section may be reduced; [0075]-[0076] if a section is not being accessed, the voltage supplied to the section may be the lower supply voltage; [0080] separate power supply for each memory section which may either be high or low voltage depending on the size of a queue of requests for each respective memory section).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Biswas in view of Jeter in view of Jarrar, and further in view of Jain et al. (US 2007/0005998) (hereinafter Jain as previously cited).
As per claim 6, Biswas in view of Jeter in view of Jarrar do not explicitly teach wherein the set of thresholds comprises at least a first subset of thresholds corresponding to the second readiness state of the first partition and a second subset of thresholds corresponding to the third readiness state of the second partition, the second subset being different from the first subset.
However, Jain teaches wherein the set of thresholds comprises at least a first subset of thresholds corresponding to the second readiness state of the first partition and a second subset of thresholds corresponding to the third readiness state of the second partition, the second subset being different from the first subset (Jain [0043]-[0044] and [0047] different thresholds correspond to different portions/zones of memory).
Jain and Biswas are both concerned with memory management in computing systems and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Biswas in view of Jeter in view of Jarrar in view of Jain because it would provide for memory power management which would enable a computing device to turn memory zones on and off for improved power management especially in portable devices such that zones of memory not available for use by the operating system may be completely powered off to save on power consumption.
Claims 9, 19, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Biswas in view Jeter in view of Jarrar, and further in view of Lefurgy et al. (US 2005/0125703) (hereinafter Lefurgy as previously cited).
As per claim 9, Biswas in view of Jeter in view of Jarrar do not explicitly teach wherein the controller is further configured to change the set of thresholds over time based, at least in part, on a usage history of the internal hardware resource.
However, Lefurgy teaches wherein the controller is further configured to change the set of thresholds over time based, at least in part, on a usage history of the internal hardware resource (Lefurgy [0035] an adaptive power/energy threshold may be adjusted based on historical access to the memory).
Lefurgy and Biswas are both concerned with memory management in computing systems and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Biswas in view of Jeter in view of Jarrar in view of Lefurgy because it would provide for local control and evaluation of power management settings at a memory device controller level within a processing system, in conjunction with global control that sets maximum power consumption bounds for groups of memory devices within the processing system. The controller-based power management scheme provides improved responsiveness to local resource demands, while reducing power consumption of attached devices with a granularity much finer than is possible with global-only power management control schemes. This provides enhancements to local control of power management settings by local controllers that sets a local maximum power consumption level/bound for each group of devices within a processing system. The local controllers then manage power consumption on a local level, while ensuring that the overall global system power consumption requirement is met. A local minimum power consumption level/bound for each group of memory devices is also determined so that changes in power consumption level are reduced, thus reducing current spikes.
As per claim 19, it has similar limitations as claim 9 and is therefore rejected using the same rationale as claim 9.
As per claim 23, it has similar limitations as claim 9 and is therefore rejected using the same rationale as claim 9.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Biswas in view of Jeter in view of Jarrar, and further in view of Sicola et al. (US 5,479,413) (hereinafter Sicola as previously cited).
As per claim 10, Jeter teaches wherein the at least one internal hardware resource comprises an internal memory (Jeter fig. 1, block 130 and [0028] internal cache).
Biswas in view of Jeter in view of Jarrar do not explicitly teach the controller is configured to write to the internal memory in a lowest available address order.
However Sicola teaches the controller is configured to write to the internal memory in a lowest available address order (Sicola col. 1, ll. 12-18 upon power-up or reset writing a unique data pattern to every memory location starting at the lowest address and ending at the highest address).
Sicola and Biswas are both concerned with memory management in computing systems and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Biswas in view of Jeter in view of Jarrar in view of Sicola because it would provide a way to determine if the stored data pattern is correct thus ensuring correct addressing and data integrity by verifying the integrity of individual memory cells of the entire array without significant delay to the start of system operation. This would provide a way to reduce delay associated with a system startup sequence due to memory testing and, in so doing, accelerate the availability of system memory for use by functional software.
Response to Arguments
Applicant's arguments have been considered but are not persuasive.
In the Remarks on pg. 10-11, Applicant argues that the combination of prior art references do not disclose “pre-emptively changing readiness states of two different partitions based on or in response to a determined upcoming workload”. The examiner respectfully disagrees. It should be noted that (a) the instant independent claims as most recently amended do not state “pre-emptively changing readiness states of two different partitions based on or in response to a determined upcoming workload” as stated in Applicant’s arguments of the Remarks, and (b) that Biswas does indeed teach the instant claim limitations as recited as well as “pre-emptively changing readiness states of two different partitions based on or in response to a determined upcoming workload”. Regarding (a), the instant claims recite receiving a parameter associated with the upcoming workload and then pre-emptively changing the readiness states of the partitions based on a comparison of the parameter value to at least one threshold. This is different than “pre-emptively changing readiness states of two different partitions based on or in response to a determined upcoming workload” as stated in Applicant’s arguments of the Remarks because the claims recite pre-emptively changing the readiness states of the partitions based on a comparison of the parameter value to at least one threshold and not the upcoming workload itself. The parameter value is associated with a parameter and the parameter is associated with the upcoming workload. The claim does not recite determining the upcoming workload, nor does it state that the readiness states are changed in response to the upcoming workload. It should be noted that the parameter itself is received and the upcoming workload is not received in the recited claims. Furthermore, the claim language is sufficiently broad enough to not require any specific interpretation relating the recited “upcoming” and “pre-emptively” terms with each other. In other words, the claim does not specifically recite particular sequences of timings for what to consider “upcoming” and “pre-emptively”. As such, regarding (b), Biswas successfully teaches both the appropriately cited claim limitations as above as well as “pre-emptively changing readiness states of two different partitions based on or in response to a determined upcoming workload”. Non-limiting examples of Biswas that teach the aforementioned concept include:
The abstract: “Incoming requests are grouped together based on which section of the system cache they target. When enough requests that target a given section have accumulated, the voltage supplied to the given section is increased to a voltage sufficient for access. Then, once the given section has enough time to ramp-up and stabilize at the higher voltage, the waiting requests may access the given section in a burst of operations”. Here, the upcoming workload is equivalent to the requests that target a given section of memory. The requests then accumulate to a particular threshold, and then once the threshold is met then the voltage for that given section is increased. Finally the requests are then given access to the given section after the voltage for that given section is increased. Hence, Biswas teaches that readiness states of the partitions i.e., the voltage levels of the sections are pre-emptively changed based on or in response to a determined upcoming workload as well as based on or in response to a comparison of the parameter value i.e., the number of requests to a threshold.
[0008]: “Prior to being accessed, the voltage supplied to the section may be increased to a second voltage which is higher than the first voltage”. The voltage is pre-emptively increased in the given section before or in anticipation of the upcoming requests accessing the given section.
[0088]: When the number of requests in the queue is greater than a threshold then increase voltage supplied to a given section of the cache memory being targeted by the requests and then allow the requests to access the given section of memory.
Fig. 8, blocks 172, 174, 182, and 184: Responsive to the number of requests in the queue being greater than a threshold, increase voltage supplied to the given section to be accessed by the requests, wait for ramp-up delay before accessing the given section, and then access the given section in a burst of operations. Here again the voltage is pre-emptively increased in the given section before or in anticipation of the upcoming requests utilizing the given section.
In summary, in Biswas the queued requests are equivalent to the claimed upcoming workload because they are queued first and they have not accessed the given section of memory yet until the voltage/power is increased to that given section prior to access. Therefore, they are considered to be upcoming. The readiness/power/voltage state of the given section is pre-emptively changed because it is first changed prior to the requests/workload actually accessing the given section. Thus, for at least the reasons provided above, Applicant’s arguments are unpersuasive and the rejections are sustained.
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
Secatch et al. (US 2022/0100407) in at least [0118] disclose proactive operational policy changes that set a workload trigger to prompt execution of at least one policy change action as prescribed by a power strategy. With one or more workload triggers set for each namespace while each namespace workload is compiled and tracked by the power module, a decision can determine if a workload trigger has been met, is imminently met, or is predicted to be met with a sufficiently high reliability. That is, the power module can associate workload values for the assorted namespaces of a data storage system with workload trigger thresholds that can be previously, currently, or likely met, which prompts step to execute one or more namespace operational policy change that alters the power consumption of at least one memory cell in response to the workload trigger being met.
Rahman et al. (US 7,498,835) in at least col. 11, ll. 65-67 and col. 12, ll. 1-2 and 23-49 disclose selectively asserting gating control signals to sequentially power up and power down different configurable portions of memory.
Ise et al. (US 2013/0326252) in at least [0144] disclose sequential orders of power states of memory segments.
Sharon et al. (US 2012/0210082) in at least [0088] disclose different ranges of threshold voltages for memory cells.
Balakrishnan et al. (US 2010/0275049) in at least abstract, [0009]-[0012] disclose turning off banks of memory based on memory access latencies.
Zheng et al. (US 2009/0248994) in at least [0027] disclose putting individual memory ranks in power states of intermediate memory readiness levels.
Chang (US 2019/0369685) in at least the abstract discloses comparing an indication of a temperature of a memory block with a temperature threshold associated with the memory block, and based on the comparison changing the power consumption of the memory block.
Woodbridge et al. (US 2005/0210206) disclose anticipatory power control of memory.
Porzio et al. (US 2022/0350532) disclose memory system configuration using queue refill time.
Berard et al. (US 2011/0145609) disclose power aware memory allocation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam Lee whose telephone number is (571) 270-3369. The examiner can normally be reached on M-TH 8AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached on 571-272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam Lee/Primary Examiner, Art Unit 2198 February 2, 2026