DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This communication is considered fully responsive to the amendment filed on 12/30/2024.
Claims 1, 6, and 7 have been amended.
Response to Arguments
Applicant’s amendments with respect to claims 1 and 6 filed on 12/30/2024 have been considered but are not persuasive because the applicant’s arguments were drawn to newly added features to independent claims, which have been addressed in the instant office action with prior art, Ogawa et al. (US 20190252439 A1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
a patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating
obviousness or nonobviousness.
Claims 1-3, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al. (US 20190252439 A1), hereinafter Ogawa, in view of Kang et al. (US 20160315088 A1), hereinafter Kang, and further in view of Yutaro et al. (WO 2021085171 A1), hereinafter Yutaro.
Regarding Claim 1, Ogawa discloses a backside-illuminated image sensor of a type configured to be illuminated on a back side of a semiconductor substrate ([0017]) having a front side opposite the back side,
comprising an array of photodiodes (20) (FIG. 1A, [0018]) formed in a semiconductor substrate (10) (FIG. 1A, [0017]), the photodiodes (20) (FIG. 1A, [0018]) electrically isolated from each other by isolation structures (30, 31, 32, 33) (FIG. 1A, [0018]),
an interlayer dielectric (Part of 120) (See FIG. 1A attached below) disposed between a first layer of conductive interconnect (130) (FIG 1A, [0021]) and the front side (101) (FIG.1, [0017]) of the semiconductor substrate (10) (FIG. 1A, [0017]);
wherein an improvement comprises:
a barrier conductive wall (110) (FIG. 1A, [0021]) disposed in the interlayer dielectric (Part of 120) (See FIG. 1A attached below) on the front side (101) (FIG.1A, [0017]) of the semiconductor substrate (10) (FIG. 1A, [0017]) between the isolation structures (30,31, 32, 33) (FIG. 1A, [0018]) and the first layer of conductive interconnect (130),
the barrier conductive wall (110) being aligned with the isolation structures (30,31, 32, 33) (FIG. 1A, [0018]) and disposed between the isolation structures (30,31, 32, 33)) (FIG. 1A, [0018]) and the first layer of metal interconnect (130).
Ogawa does not disclose that the barrier conductive wall is a barrier metal wall and the first layer of conductive interconnect is a first layer of metal interconnect.
Kang teaches the barrier conductive wall is a barrier metal wall (307) (FIG. 9, [0115]; 307 is gate made of tungsten).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have modified Ogawa’s barrier conductive wall to be barrier metal wall as taught by Kang to improve light-shielding effect.
Ogawa in view of Kang does not disclose that the first layer of conductive interconnect is a first layer of metal interconnect
Yutaro discloses the first layer of conductive interconnect is a the first layer of metal interconnect (67) (FIG. 2, [0035]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have modified Ogawa’s first layer of conductive interconnect to include the first layer of metal interconnect, to improve light-shielding effect (Yutaro; [0035]).
PNG
media_image1.png
515
735
media_image1.png
Greyscale
Regarding Claim 2, Ogawa, Kang, and Yutaro disclose the backside-illuminated image sensor of claim 1
Kang discloses wherein the barrier metal wall (307) (FIG. 9, [0115]; 307 is gate made of tungsten) comprises tungsten (FIG. 9, [0115]; 307 is gate made of tungsten; this transistor can be used in image sensor [0248]) .
Regarding claim 3, Ogawa, Kang, and Yutaro disclose the backside-illuminated image sensor of claim 1,
Ogawa, Kang, and Yutaro do not disclose specially wherein the barrier metal wall comprises mask-defined shapes having a length to width ratio greater than or equal to four.
Generally, the ratio of length to width in shape will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ratio is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding Claim 6, Ogawa discloses a backside-illuminated image sensor ([0017]) of the type comprising an array of photodiodes (20) (FIG. 1A, [0018]) formed in a semiconductor substrate (10) (FIG. 1A, [0017]),
the photodiodes (20) (FIG. 1A, [0018]) configured to be illuminated from a backside (102) (FIG. 1A, [0017]) of the semiconductor substrate (10) (FIG. 1A, [0017]) and electrically isolated from each other by isolation structures (30, 31, 32, 33) (FIG.1A; each pixel is isolated electrically.),
an interlayer dielectric (Part of 120) (See FIG. 1A attached below) disposed between a first layer of conductive interconnect (130) (FIG. 1A, [0021]) and a front side (101) (FIG. 1A, [0017]) the semiconductor substrate (10) (FIG. 1A, [0017]), the front side (101) of the semiconductor substrate (10) being opposite the backside (102) of the semiconductor substrate (10);
wherein an improvement comprises:
a barrier conductive wall (110) (FIG. 1A, [0021]) disposed in the interlayer dielectric (See FIG. 1A attached below) between the isolation structures (30, 31, 32, 33) (FIG. 1A, [0018]) and the first layer of conductive interconnect (130) (FIG. 1A, [0021]), the barrier conductive wall (110) being aligned with the isolation structures (30, 31, 32, 33) and disposed between the isolation structures (30, 31, 32, 33) and the first layer of conductive interconnect (130);
the barrier conductive wall (110) being capped by a dielectric layer (See FIG. 1A attached below) disposed between the first layer of conductive interconnect (130) and the interlayer dielectric (See FIG. 1A attached below), wherein the barrier conductive wall (110) is electrically isolated from the first layer of conductive interconnect (130).
Ogawa does not disclose a barrier conductive wall is a barrier metal wall and the first layer of conductive interconnect is a first layer of metal interconnect.
Kang discloses a barrier metal wall (307) (FIG. 9, [0115]; 307 is gate made of tungsten)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have modified Ogawa’s barrier conductive wall to be barrier metal wall as taught by Kang, in order to improve light-shielding effect.
Ogawa in view of Kang does not disclose that the first layer of conductive interconnect is a first layer of metal interconnect
Yutaro discloses the first layer of metal interconnect (67) (FIG. 2, [0035]).
PNG
media_image1.png
515
735
media_image1.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have modified Ogawa’s barrier wall and interconnect to include barrier metal wall and metal interconnect, to improve light-shielding effect (Yutaro; [0035]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa in view of Kang and Yutaro, and further in view of Kim et al. (US 20120104465 A1), hereinafter Kim.
Regarding Claim 4, Ogawa, Kang, and Yutaro disclose the backside-illuminated image sensor of claim 1
The combined device of Ogawa, Kang, and Yutaro discloses wherein the barrier metal wall is separated from the isolation structures disposed in the semiconductor substrate
Ogawa, Kang, and Yutaro do not disclose an etch-stop layer comprising material having etching selectivity over the semiconductor substrate.
Kim teaches an etch-stop layer (235) (FIG. 8, [0103]) comprising material having etching selectivity over the semiconductor substrate (200) (FIG. 8, [0098]; typically etch-stop layer is dielectric, therefore dielectric has the etching selectivity over semiconductor).
the etching stop-layer of Kim is incorporated with the device of Ogawa because etching of etch-stop layer does not etch the semiconductor substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Ogawa’s structure the etch-stop layer as taught by Kim, to prevent etching of the semiconductor substrate.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa, in view of Kang, Yutaro, and Kim, and further in view of Hsieh et al. (US 20070048965 A1), hereinafter Hsieh.
Regarding Claim 5, Ogawa, Kang, Yutaro, and Kim disclose the backside-illuminated image sensor of claim 4
Ogawa, Kang, Yutaro, and Kim do not discloses wherein the etch- stop layer comprises silicon oxynitride .
Hsieh teaches wherein the etch- stop layer comprises silicon oxynitride ([0037]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Ogawa, Kang, Yutaro, and Kim to include silicon oxynitride etch-stop layer, to introduce the etching selectivity between etch-stop layer and semiconductor substrate and to prevent etching of substrate.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa, in view of Kang, and Yutaro, and in view of Mao et al. (US 20210358993 A1), hereinafter Mao.
Regarding claim 7, Ogawa, Kang, and Yutaro disclose the backside-illuminated image sensor of claim 6
The combined device of Ogawa, Kang, and Yutaro discloses further comprising:
a metal grid (80) (FIG. 4A, [0019]) defining a plurality of apertures each aligned with a photodiode of the array of photodiodes (20) (FIG. 4A, [0018]), the metal grid (80) (FIG. 4A, [0019]) being aligned with the barrier metal wall (110) (FIG. 1A; metal grid and barrier wall are aligned with isolation structure 30.);
The combined device of Ogawa, Kang, and Yutaro does not discloses
a plurality of neutral-density filters in a first group of the plurality of apertures that are aligned with a first group of photodiodes of the array of photodiodes and wherein a second group of the plurality of apertures lacks neutral-density filters, and a plurality of color filters disposed in the first group of apertures wherein the metal grid separates adjacent color filters.
FIG. 2 of Mao discloses a plurality of neutral-density filters (220 in 204A and 204B) (See FIG. 2, [0026]) in a first group of the plurality of subpixels that are aligned with a first group of photodiodes (S in 204A and 204B) (FIG. 2, [0022]) of the array of photodiodes (L and S in 204A and 204B) (FIG. 2, [0022]) and wherein a second group of the plurality of subpixels (L in 204A and 204B) lacks neutral-density filters (the second group photodiodes L do not have neutral density filters), and a plurality of color filters (B) (FIG. 2, [0024]) disposed in the first group of subpixels.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Ogawa, Kang, and Yutaro, in order to include neutral density filters, to control the intensity of light .
FIG. 2 of Mao does not disclose a first group of the plurality of apertures and a second group of plurality of apertures and the metal grid separates adjacent color filters.
FIGS. 5A and 5B of Mao discloses a first group of aperture (See FIG. 5B attached below; each pixel includes aperture and a first group aperture is the aperture correspond to photodiode SPD [514] with neutral density filter [554]) and a second group of plurality of apertures (See FIG. 5B attached below; each pixel includes aperture and the second group apertures are the apertures correspond to photodiode LPD [516] without neutral density filter).
The combination of FIGs. 5A and 5B with FIG. 2 shows that there is a aperture between each subpixel.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Ogawa, Kang, Yutaro and fig. 2 of Mao with the apertures and metal grids of figs. 5A and 5B of Mao because they can prevent interferences of light between adjacent photodiodes.
The neutral density filter and color filters in FIG. 2 of Mao and aperture structure in FIG. 5B of Mao are incorporated with Ogawa’s structure to discloses a plurality of neutral-density filters and a plurality of color filters in a first group of the plurality of apertures that are aligned with a first group of photodiodes of the array of photodiodes and wherein a second group of the plurality of apertures lacks neutral-density filters, and a plurality of color filters disposed in the second group of apertures that are aligned with a second group of photodiodes of the array of photodiodes.
PNG
media_image2.png
783
691
media_image2.png
Greyscale
Regarding claim 8, Ogawa, Kang, Yutaro, and Mao disclose the backside-illuminated image sensor of claim 7,
The combined device of Ogawa, Kang, and Yutaro discloses barrier metal wall (110).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the Ogawa’s barrier metal wall structure disposed between the first photodiode of the first group of photodiodes and a second photodiode of the of the second group of photodiodes adjacent the first photodiode in Mao because the gate (barrier metal wall) can be used to drive the photodiode.
Regarding claim 9, Ogawa, Kang, Yutaro, and Mao disclose the backside-illuminated image sensor of claim 8,
The combined device of Ogawa, Kang, Yutaro, and Mao discloses the barrier metal wall partially surround the first photodiode of the first group of photodiode
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa in view of Kang and Yutaro, and further in view of Kim et al. (US 20130026384 A1), hereinafter Kim1.
Regarding claim 10, Ogawa, Kang, and Yutaro disclose the backside-illuminated image sensor of claim 1,
The combined device of Ogawa, Kang, and Yutaro does not disclose wherein the barrier metal wall is electrically connected to the first layer of metal interconnect to receive a ground voltage.
Kim1 discloses a gate (86) (FIG.15, [0070]) of the transistor (83) (FIG. 15, [0071]) connected to a terminal and to ground voltage (AGND) (FIG 15, [0070]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the ground voltage connection of Kim1 in the combined device of Ogawa, Kang, and Yutaro in order to reset the photodiode.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAESUN LEE whose telephone number is (571)272-0943. The examiner can normally be reached Mon- Fri, 8 - 5 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAESUN LEE/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights