DETAILED ACTION
In view of the appeal brief filed on 3/26/2026, PROSECUTION IS HEREBY REOPENED. A new grounds of rejection is set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/EDUARDO COLON SANTANA/ Supervisory Patent Examiner, Art Unit 2837
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 30-36, 40, 42-43, 45-48, and 50-52 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Andreas et al. (DE 102016010777A1).
Regarding claim 30,
Andreas discloses (Fig. 2):
An apparatus for providing at least one drive signal for an electrical load (Fig. 2, M), comprising: an enabling device (15, 1a, 1b) adapted to receive at least one input signal (5a, 5b,7a, 7b, 8a) and, based on the at least one input signal (5a, 5b, 7a, 7b, 8a) , to output, at least temporarily, the at least one drive signal (9a, 8b, 9b), wherein the at least one input signal is a logic signal or a binary signal (5a, 5b, 7a, 7b, 8a, ¶0053-¶0057), and wherein the at least one drive signal is a logic signal or a binary signal (control signals and PWM signals are binary, ¶0059-¶0060), wherein the enabling device (15, 1a, 1b) comprises at least one logic circuit (Fig. 2, 1A, 1B, 16, 10), and wherein the at least one logic circuit comprises at least a first inverter (16) in series with a second inverter (10), wherein the at least one input signal is supplied to the first inverter (from 1a and 1b), wherein an output signal of the first inverter (16) is supplied to an input of the second inverter (10), and wherein the enabling device is adapted to output an output signal of the second inverter as the at least one drive signal for the electrical load (M, ¶0046-¶0047, ¶0050); and an activating device (13, 14) adapted to selectively activate or deactivate the enabling device (15, 1a, 1b), wherein the activating device is adapted to receive an enable signal (from 14) and, based on the enable signal, to activate or deactivate the enabling device (15, deactivates 1a and 1b to interrupt signal using output enable signals 6a and 6b, ¶0052).
Regarding claim 31,
Andreas discloses (Fig. 2):
wherein the enabling device (Fig. 2, 15, 1a, 1b) outputs the at least one drive signal (9b) ) to a power drive stage (16) in a load device (M, ¶0061-¶0062)
Regarding claim 32,
Andreas discloses (Fig. 2):
wherein the activating device (Fig. 2, 13, 14) is adapted to supply the enabling device (15, 1a, 1b) with an electrical operating voltage (via 16 and 10) in order to activate the enabling device (¶0052, ¶0061-¶0062).
Regarding claim 33,
Andreas discloses (Fig. 2):
wherein the activating device (Fig. 2, 13, 14) is adapted to disconnect the enabling device (15, 1a, 1b) from an or the electrical operating voltage (Fig. 1, 5) in order to deactivate the enabling device (¶0045-¶0046).
Regarding claim 34,
Andreas discloses (Fig. 2):
wherein the activating device (13, 14) is adapted to generate, at least temporarily, the electrical operating voltage (¶0047).
Regarding claim 35,
Andreas discloses (Fig. 2):
wherein the activating device (13,14) is adapted to receive a first voltage as the enable signal (¶0057, powers 1a and 1b) and to generate the electrical operating voltage based on the first voltage (¶0057, ¶0059-¶0062).
Regarding claim 36,
Andreas discloses (Fig. 2):
wherein at least one of the activating device (13, 14) and the enabling device (15, 1a, 1b) are supplied with electrical energy via the enable signal (13 is enabled from 14, ¶0056-¶0057).
Regarding claim 40,
Andreas discloses (Fig. 2):
wherein the enabling device (Fig. 2, 15, 1a, 1b) is adapted to receive a plurality of input signals (from 14, 7a, 7b)and based on the plurality of input signals, to output, at least temporarily, a plurality of drive signals (output from 1a, 1b, 9a, 8b, 9b, ¶0059-¶0061).
Regarding claim 42,
Andreas discloses (Fig. 2):
An apparatus for processing at least one input signal (From 14, 7a, 7b), comprising: a first apparatus (15) including a first enabling device (15, 1a, 1b), wherein the first enabling device (1a) is adapted to receive the at least one input signal (5a, 6a, 7a, 8a), wherein the at least one input signal is a logic signal or a binary signal (¶0059-¶0060) and, based on the at least one input signal (5a, 6a, 7a, 8a), to output, at least temporarily, at least a one first signal S1 (9a, 8b), wherein the at least one input signal (5a, 6a, 7a, 8a) is supplied to a first inverter (16) of the first enabling device (15, via 1b), wherein an output signal of the first inverter (16) of the first enabling device (15) is supplied to a second inverter (10) of the first enabling device (15), and wherein the first enabling device is adapted to output an output signal of the second inverter as at least the one first signal S1 (¶0046-¶0047, ¶0050);and a second apparatus (17) including a second enabling device (1b), wherein the second enabling device is adapted to receive at least the one first signal S1 from the first enabling device (9a, 8b) and output, based on at least the one first signal S1, at least temporarily, at least one second signal S2 (9b) as at least one drive signal, wherein the at least one drive signal is a logic signal or a binary signal (¶0059-¶0060).
Regarding claim 43,
Andreas discloses (Fig. 2):
A method for providing at least one drive signal for an electrical load (Fig. 2, M), comprising: receiving at least one input signal (5a, 5b,7a, 7b, 8a) by an enabling device (15, from 14), wherein the at least one input signal is a logic signal or a binary signal (¶0059-¶0062); applying the at least one input signal to an input of a first inverter (Fig. 2, 16, from 1a and 1b) in the enabling device (15) to generate a first output signal (output fr0m 16);applying the first output signal of the first inverter (from 16) to an input of a second inverter (10) in the enabling device (15) to generate a second output signal (from 10); outputting, based on the second output signal (from 10),at least temporarily, the at least one drive signal by the enabling device operates motor, M, ¶0046-¶0047, ¶0050 ); and selectively activating or deactivating the enabling device (15) by the activating device (13, 14) based on the enable signal (13, 14, signals 5a, 6a, 6b, 7a, 8a, ¶0059-¶0062).
Regarding claim 45,
Andreas discloses (Fig. 2):
wherein the activating device (Fig. 2, 13, 14) supplies the enabling device (15, 1a, 1b) with an electrical operating voltage (¶0057)in order to activate the enabling device (15, 1a, 1b), and/or wherein the activating device (13, 14) disconnects the enabling device (15, 1a, 1b) from the electrical operating voltage in order to deactivate the enabling device (¶0056-¶0057).
Regarding claim 46,
Andreas discloses (Fig. 2):
wherein the activating device (Fig. 2, 13, 14) generates, for example at least temporarily, the electrical operating voltage (¶0057).
Regarding claim 47,
Andreas discloses (Fig. 2):
wherein the activating device (Fig. 2, 13, 14) receives a first voltage (from 14) as the enable signal (from 14 to 13) based on the first voltage (¶0057, ¶0059-¶0062).
Regarding claim 48,
Andreas discloses (Fig. 2):
wherein at least one of the activating device (13, 14) and the enabling device (15) is supplied with electrical energy via the enable signal (from, 5a, 5b,¶0057).
Regarding claim 50,
Andreas discloses (Fig. 2):
wherein the enabling device (Fig. 2, 15, 1a, 1b) receives a plurality of input signals (from 14) and based on the plurality of input signals, outputs a plurality of drive signals (9b, ¶0059-¶0062).
Regarding claim 51,
Andreas discloses (Fig. 2):
A computer-readable storage device (Fig. 2, ¶0044, 14, 15), comprising instructions which, when executed by a computer, cause the computer (¶0044) to: selectively activate or deactivate an activating device (13, 14) to supply an enabling device (15, 1a, 1b) with an electrical operating voltage (via 5a, 5b) in order to activate the enabling device (15, 1a, 1b,¶0057, ¶0059-¶0062 ); and selectively activate or deactivate at least one input signal (5a, 5b, 8a) to the enabling device (15, 1a, 1b), wherein the enabling device, when activated by the electrical operating voltage, is configured to output, based on the at least one input signal (5a, 5b, 8a), at least temporarily, at least one drive signal (output from 1b, ¶0060-¶0062), wherein the at least one input signal (5a, 5b, 8a) is a logic signal or a binary signal and the at least one drive signal (9b) is a logic or a binary signal (¶0059-¶0060), wherein the enabling device (15, 1a, 1b) includes at least a first inverter (16) and a second inverter (10) wherein the at least one input signal (Fig. 2, From 1a and 1b) is supplied to the first inverter (16), wherein an output signal of the first inverter is supplied to the second inverter (10), and wherein the enabling device is adapted to output an output signal of the second inverter as the at least one drive signal (to M, ¶0046-¶0047, ¶0050).
Regarding claim 52,
Andreas discloses (Fig. 2):
wherein the instructions which, when executed by a computer, further cause the computer to: generate an enable signal to the activating device (from 14, activate as 13, 5a, 5b, ¶0052-¶0057); and selectively activate or deactivate the activating device (13, 14) to supply the enabling device (15, 1a, 1b) with an electrical operating voltage based on the enable signal (¶0052-¶0057).
Response to Arguments
Appellant’s arguments, see appeal brief, filed 3/26/2026, with respect to the rejection(s) of the claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Andreas et al. (DE 102016010777A1), since Andreas discloses inverter 16 and 10. Appellant contents that these are not logic inverters in a logic circuit. However, the examiner wants to reiterate that the claim only calls for a first inverter and second inverter and does not specifically state that the inverters are “logic inverters”. The term “logic circuit” is broad enough to consider that logical operations on one or more binary or logic input signals can produce an output signal. It is well known in digital electronics, that voltage signals are the physical manifestation of logic circuits. They represent logical values on specific voltage thresholds, for example, logic HIGH (1) can be represented by a high voltage (5V or 3.3V) and logic LOW (0) can be represented by a low voltage (0V or ground). Moreover, Andreas et al. discloses (see par. 0015 and 0053-0060) that PWM signals are used, which are fundamentally digital logic signals. They typically oscillate between two discrete voltage levels (i.e. 0 V for logic LOW and 3.3 V or 5 V for logic HIGH). Therefore, because PWM is comprised purely of on/off logic, one can easily generate and process these signals using standard digital hardware in a logic circuit as taught by Andreas et al. (see figure 2). Therefore, the rejection has been revise as a anticipation rejection under 35 USC 102(a1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wei et al. (US 2013/0241451) -inverter device
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/C.S.L./Examiner, Art Unit 2837
/EDUARDO COLON SANTANA/Supervisory Patent Examiner, Art Unit 2837
Prosecution Insights