Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
This Office Action is in response to applicant’s amendment filed on March 23, 2026, under which claims 1-6, 8-19, 21-24 and 26 are pending and under consideration.
Response to Arguments
Applicant’s amendments have overcome the previous § 112 and § 103 rejections. However, new grounds of rejection have been made under § 112 and § 103 in view of applicant’s amendments.
In regards to the § 103 rejection, upon further consideration, new grounds of rejection have been made based on newly cited art to account for the newly recited claim limitations. Applicant’s arguments are moot under the new grounds of rejection.
In regards to the issue of the § 112(f) interpretation, the addition of “processor” for the modules of claim 18 is regarded as incorporating sufficient structure for the recited acts. Therefore, the “module” limitations are no longer interpreted under § 112(f). However, the previous § 112(f) interpretation for the terms in claim 19 still applies.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Claim 19 include limitations that invoke § 112(f). The limitations that invoke § 112(f) are:
“accumulator configured to accumulate” recited in dependent claim 19.
“comparator configured to compare” recited in dependent claim 19.
In the above limitations, the terms “accumulator,” and “comparator” are considered to be generic placeholder because the instant specification generally uses these terms (as well as the “accumulator” and “comparator”) as being generic to both hardware and software implementations. See [0066]: “The neuron module circuit device may be implemented by one or more hardware modules, one or more software modules, or various combinations thereof”; [0164]: “In other examples, one or more of the hardware components that perform the operations described in this application are implemented by computing hardware, for example, by one or more processors or computers… software, such as an operating system (OS) and one or more software applications that run on the OS, to perform the operations described in this application” (i.e., teaching that the modules may be functions of a general-purpose computer). Therefore, these terms, as used in the context of elements of a system, do not having a sufficiently definite meaning as the name for structure in the form of specific hardware.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Support can be found in paragraph [0164], which teaches hardware and software implementations of the above elements. In the case of software implementations, [0164] teaches that the above elements can be implemented on a general-purpose computer that is programmed to perform the functions described in the specification.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4 and 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 3 and 13, the “the synapse modules” is an ambiguous as to whether it is referring to the “one or more synapse modules” recited in the preceding part of these claims or the “synapse modules of the neuron modules” of their parent independent, which are two distinct elements that both use the term “synapse modules.” Therefore, it is unclear which one of these elements is being referred to. For purposes of examination, the synapse modules been understood as referring to the “one or more synapse modules.”
Claims 4 and 14 are rejected on the same grounds due to their dependency on claims 3 and 13, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-4, 6, 8-13, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Imam et al. (US 2018/0174041 A1) (“Imam”) in view of Cherubini et al. (US 2021/0357725 A1) (“Cherubini”) and Nadafian et al., “Bio-plausible Unsupervised Delay Learning for Extracting Temporal Features in Spiking,” arXiv:2011.09380v1 [cs.NE] 18 Nov 2020 (“Nadafian”).
As to claim 1, Imam teaches a processor-implemented method, the method comprising:
constructing a neuron array comprising a plurality of neuron modules; [[0026]: “FIG. 2A is a simplified block diagram 200 illustrating an example of at least a portion of such a neuromorphic computing device 205. As shown in this example, a neuromorphic computing device 205 may be provided with a network 210 of multiple neural network cores (e.g., 215) interconnected by an on-device network such that multiple different connections may be potentially defined between the cores… Each core (e.g., 215) may possess processing and memory resources and logic to implement some number of primitive nonlinear temporal computing elements to implement one or more neurons using the neuromorphic core.” As shown in FIGS. 2A-2B, the neuromorphic cores 110 (neuron modules) are in an array. The limitation of “constructing” is met by the use of the neuromorphic cores collectively as an array.]
mapping a target pattern to the neuron array, including constructing a subarray of the neuron array [In general, [0002]: “ANNs represent one of the most relevant and widespread techniques used to learn and recognize patterns.” [0056]: “FIG. 5C illustrates how an SNN may be configured such that activation of a single neuron (e.g., Neuron 6) may cause a wave of spikes to propagate outward from the activated neuron throughout the network in response. Such outward propagation of a spike wave may include not only the spikes sent by Neurons 4, 8, and 9 at t=1…” See also [0055] for an additional description of FIG. 5C, which shows the mapping of a pattern onto portion of the neuron array, which corresponds to a subarray. That is, propagating a spike wave constitutes mapping it to the subarray. Additionally, non-hazard neurons also constitute a sub-array. See [0090]: “Non-hazard neurons within an SNN configured for path finding and planning within a particular network may be configured such that, prior to training, any spike received at the neuron will result in the neuron's spiking threshold potential being met and the neuron sending additional spikes to its neighbors (i.e., to propagate the spike wave used to train the SNN).”] and, determining operation modes of the neuron modules included in the subarray, the operation modes of the neuron modules including a visible mode […], determining which one neuron module of the neuron modules, included in the subarray, is in the visible mode, and receiving, by the one neuron module being in the visible mode, the target pattern; [[0055]: “Turning to FIG. 5C, a certain one of the neurons in the SNN (e.g., Neuron 6) may be activated 505 (e.g., by providing an input to the neuron or externally driving the neuron (through a controller internal or external to the neuromorphic computing device)) to cause the neuron to send a spike to its neighboring neurons (e.g., Neurons 4, 8, and 9).” [0031]: “signals may be provided by a controller (e.g., 224) internal or external to the neuromorphic computing device (e.g., in connection with a particular application or algorithm utilizing the SNN)…” [0108]: “The core may then use time multiplexing to turn to another, second one of the neurons implemented by the core during the same time step n=0 (i.e., but in another portion of the time step), process 1384 any inputs (e.g., external input currents or spike messages from other neurons in the SNN) and determine whether any such inputs caused the potential of the neuron to meet or exceed its firing threshold (and cause a spike to be sent (either in the same or an immediately subsequent time step, depending on the configuration of the SNN)).” See also [0031] (“neurons in an output layer of the SNN”). That is, referring to FIG. 5C for example, neuron 6 may be regarded as being determined to be in a visible mode because it is subject to an input external to the neuromorphic computing device. In other words, use of a neuron to receive an external input constitutes determining that its operational mode is that of a visible mode. Furthermore, inputs into the visible neuron result in other neurons receiving a subsequent spike.]
adapting the neuron modules to the target pattern in response to a reception of the target pattern; [[0040]: “an output soma process (e.g., 285) that receives each dendrite compartment's accumulated neurotransmitter amounts for the current time and evolves each dendrite and soma's membrane potential state, generating outgoing spike messages at the appropriate times (e.g., when a threshold potential of the soma has been reached).”]
training the neuron modules to cause the neuron array to mimic the target pattern, [[0059]: “In the parlance of machine learning, the example of FIG. 5C may correspond to a training phase of an example SNN modeling a particular network topography.” [0069]: “As in the examples of FIGS. 4A-5H, a destination neuron (corresponding to a physical destination) may be selected and activated to train the SNN to bias subsequent spike chains to be directed along a shortest path toward the destination.” [0097]: “upon training a particular SNN for path finding toward a particular destination node, paths may be found between a particular source node and the destination node by activating a neuron associated with the particular source node. If conditions of the network do not change and the destination(s) remain the same, the trained SNN may be reused to find the path from any source to the designated destinations.” That is, the SNN is trained to find a path, which is mimicry of a target pattern.]
wherein the training comprises:
measuring a processing timing latency from a first point in time […] to a second point in time at which the corresponding neuron module outputs an output spike signal triggered by the input spike signal, [[0048]: “In one model, STDP within a neuromorphic computing device may be implemented such that whenever there is a spike in the presynaptic neuron or the postsynaptic neuron, the weight at the associated synapse is changed according to Equation (9) [see equation in text]… where Δw is the change in weight applied to a synapse between a presynaptic neuron and a postsynaptic neuron, tpost is the latest time of spike of the postsynaptic neuron, tpre is the latest time of spike of the presynaptic neuron, δ1 and δ2 are tunable parameters that set the rate and direction of learning, and d is another tunable parameter that sets a time window in which co-occurring pre- and post-synaptic spikes may lead to a change in the synaptic weight. If tpost−tpre do not meet either of the two criteria in Equation (9), the weight is not changed, i.e. Δw=0.” That is, “tpost−tpre” corresponds to a processing timing latency based on a time that corresponds to the input to a neuron (tpre, the presynaptic neuron’s spike) and a time that corresponds to the output of the neuron. Furthermore, in this context, pre-synaptic constitutes an “adjacent” neuron because it inputs into the neuron that fires (i.e. the postsynaptic neuron).] and
updating synaptic weights of synapse modules of the neuron modules based on the processing timing latency from the first point to the second point, using a synaptic weight update function that receives the measured processing timing latency as a variable input for calculating a delta weight value. [[0048]: “where Δw is the change in weight applied to a synapse between a presynaptic neuron and a postsynaptic neuron, tpost is the latest time of spike of the postsynaptic neuron, tpre is the latest time of spike of the presynaptic neuron, δ1 and δ2 are tunable parameters that set the rate and direction of learning, and d is another tunable parameter that sets a time window in which co-occurring pre- and post-synaptic spikes may lead to a change in the synaptic weight. If tpost−tpre do not meet either of the two criteria in Equation (9), the weight is not changed, i.e. Δw=0.” That is, the latency tpost−tpre is used to update the weights as represented by the equation for Δw. This weight update and its associated equations correspond to a synaptic weight update function. See [0059]: “In the parlance of machine learning, the example of FIG. 5C may correspond to a training phase of an example SNN modeling a particular network topography and FIG. 5D may reflect the resulting trained SNN. With the synaptic weights of the bi-directionally connected neurons strengthened in a direction opposite to the direction of the spike wave generated by one of the neurons (e.g., Neuron 6) according to an STDP rule defined for the SNN, the adjusted synaptic weights may be leveraged to determine a shortest path from any one of the neurons to the neuron (e.g., Neuron 6).”]
Imam does not explicitly teach:
(1) the limitation that the operation modes also include a “hidden mode;” and
(2) the first point in time is “at which a corresponding neuron module receives an input spike signal from an adjacent neuron module.”
However, Cherubini teaches a “hidden mode” for a neuron of a neural network hardware device [[0041]: “According to an embodiment of the method, the spiking neural network may comprise at least one hidden layer of spiking neurons connected between the input layer and the output layer of the spiking neural network for supervised learning.” See also [0031], [0034], and [0063]. Additionally, the neural network 514 includes a hidden layer as shown in FIG. 5.] and training “to cause the neuron array to mimic the target pattern” [[0075]: “The spiking neural network 514 produces output spike patterns. In case of the output of the SNN is rate encoded, the class is predicted from the neuron that spikes with highest rate. In case of a time encoded output, for each class a target output pattern is predetermined. For inference, the class is predicted from the target spike pattern which is closest to the output spike pattern [the neuron array to mimic the target pattern] using, e.g., the van Rossum distance metric.” (Note: forecasting outcomes based on learned relationship.)]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Imam with the teachings of Cherubini by modifying the operation modes to further includes a hidden mode, and to perform the training to cause the neuron array to mimic the target pattern. The motivation would have been to enable and facilitate a spiking neural network to perform classification, as suggested by Cherubini ([0075]: “The spiking neural network 514 produces output spike patterns. In case of the output of the SNN is rate encoded, the class is predicted from the neuron that spikes with highest rate. In case of a time encoded output, for each class a target output pattern is predetermined.”).
The combination of references thus far does not teach the limitation that the first point in time is “at which a corresponding neuron module receives an input spike signal from an adjacent neuron module.”
Nadafian teaches a first point in time “at which a corresponding neuron module receives an input spike signal from an adjacent neuron module.” [§ 1, paragraph 1: “Normally, the synaptic delay (d) is not considered in firing time difference (Dt) of typical STDP, but in the case of existing delays over synapses, we need to take it into account so that the STDP correctly adjusts the synaptic weights by considering the effect of the delay on the spike timing of the post-synaptic neuron. Therefore, for two connected neurons and j, the STDP adjusts their synaptic weight wi,j with respect to the firing time difference as well” as the current synaptic delay (di,j). The equations for delay-related STDP are as follow…[see equation in text].” That is, referring to the equation referred to in the above part of the text, the factor of (ti + di,j) corresponds to the time at which a corresponding neuron module receives an input spike signal from an adjacent neuron module, since the time at which the neuron receives the input spike signal is the firing time of the presynaptic neuron (i.e., ti) plus the synaptic delay di,j. Note that ti and tj here refer to the same times as tpre and tpost, and that since (ti + di,j) is subtracted from tj, it is written as -ti -di,j in the equation. Note that the equation for Δwi,j is an extension of the standard STDP weight update equation.]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of the references combined thus far with the teachings of Nadafian by implementing the technique of taking into account the synaptic delay such that the first point in time is a time at which a corresponding neuron module receives an input spike signal from an adjacent neuron module. Doing so would have enabled consideration of delays over synapses, in order to make computational models more effective in providing aligned insights with experimental evidences (see Nadafian, § 1, second-to-last paragraph: “However, ignoring the delays makes these computational models ineffective in providing aligned insights with the experimental evidences.”).
As to claim 2, the combination of Imam, Cherubini, and Nadafian teaches the method of claim 1, wherein the adapting comprises activating the neuron modules in response to the reception of the target pattern and performing signal transmission between the neuron modules. [Imam, [0034]: “The soma 285 may be a hardware-implemented process that receives each dendrite's accumulated neurotransmitter amounts for the current time and evolves each dendrite and soma's potential state to generate outgoing spike messages at the appropriate times. A dendrite 280 may be defined for each connection receiving inputs from another source (e.g., another neuron). … When the neuron's activation exceeds a threshold set for the neuron 275, the neuron may generate a spike message that is propagated to a fixed set of fanout neurons via the output interface 270.” That is, activation occurs when the accumulation exceeds a threshold, which then results in performing a transmission to another neuron. The accumulation is caused by receipt of a signal from another source, which in the case of training is the target pattern.]
As to claim 3, the combination of Imam, Cherubini, and Nadafian teaches the method of claim 1, wherein
each of the neuron modules comprises any one or any combination of any two or more of a soma module, one or more axon modules, one or more synapse modules, and an external signal input/output module, [Imam, [0033]: “Components, or architectural resources, of a neuromorphic core 215 may further include an input interface 265 to accept input spike messages generated by other neurons on other neuromorphic cores and an output interface 270 to send spike messages to other neuromorphic cores over the mesh network.” Imam, [0034]: “The dendrite 280 may be a hardware-implemented process that receives spikes from the network. The soma 285 may be a hardware-implemented process that receives each dendrite's accumulated neurotransmitter amounts for the current time and evolves each dendrite and soma's potential state to generate outgoing spike messages at the appropriate times.” See also [0031] (external interfaces). That is, the alternatives of a soma module, a synapse module (in the form of a dendrite), and a signal input/output module (in the form of input and output interfaces) are taught. Additionally, output interfaces can also be regarded as an axon module.] and
the training comprises updating synaptic weights of the synapse modules. [Imam, [0051]: “Further, as the presynaptic spikes sent on synapses 465, 470 by neurons 404 and 430 at t=2 to neurons 405, 425 followed the post-synaptic spikes sent by neurons 405, 425 at t=1, the synaptic weights of synapses 465, 470 may likewise be adjusted based on the STDP learning rule, resulting in an SNN with the enhanced post-learning weights represented by diagram 480.”]
As to claim 4, the combination of Imam, Cherubini, and Nadafian teaches the method of claim 3, wherein the neuron modules are configured to operate in any one or any combination of any two or more of the visible mode, the hidden mode, a relay mode, and a block mode, [As noted in the rejection of claim 1, Imam teaches neurons that operate in a visible mode. Imam also teaches a “block mode” (see [0083]: “In some cases, a node may be designated as an absolute or impassible hazard, such that no network paths should be determined that traverse the hazard node.”).] and
the updating comprises:
determining whether each of the neuron modules operates in at least one of the visible mode and the hidden mode; [As noted in the rejection of claim 1, referring to FIG. 5C of Imam, for example, neuron 6 may be regarded as being determined to be in a visible mode because it is subject to an input external to the neuromorphic computing device. In other words, use of a neuron to receive an external input constitutes determining that its operational mode is that of a visible mode. Furthermore, the use of hidden neurons is taught by Cherubini in the existing combination of references, and such use also includes the determination of those neurons.].
updating, for each of neuron modules operating in the at least one of the visible mode and the hidden mode, the synaptic weights [Imam, [0045]: “Accordingly, in some implementations, in addition to the state variables of a neuron, there are several other configurable parameters, including the time constant of individual dendritic compartment τs1,…, τss, a single τm, θ, Ibias for each neuron, and a configurable weight value wij for each synapse from neuron j to i, which may be defined and configured to model particular networks.” [0059]: “In the parlance of machine learning, the example of FIG. 5C may correspond to a training phase of an example SNN modeling a particular network topography and FIG. 5D may reflect the resulting trained SNN. With the synaptic weights of the bi-directionally connected neurons strengthened in a direction opposite to the direction of the spike wave generated by one of the neurons (e.g., Neuron 6) according to an STDP rule defined for the SNN, the adjusted synaptic weights may be leveraged to determine a shortest path from any one of the neurons to the neuron (e.g., Neuron 6), from which the spike wave originated.” [0060]: “Turning to FIG. 5F, a representation of an SNN is shown with synaptic weights adjusted based on an STDP rule and in response to a spike wave generated by Neuron 6.”] based on a time period from a point in time […] to another point in time at which the corresponding neuron module outputs the spike signal. [[0048]: “In one model, STDP within a neuromorphic computing device may be implemented such that whenever there is a spike in the presynaptic neuron or the postsynaptic neuron, the weight at the associated synapse is changed according to Equation (9) [see equation in text]… where Δw is the change in weight applied to a synapse between a presynaptic neuron and a postsynaptic neuron, tpost is the latest time of spike of the postsynaptic neuron, tpre is the latest time of spike of the presynaptic neuron, δ1 and δ2 are tunable parameters that set the rate and direction of learning, and d is another tunable parameter that sets a time window in which co-occurring pre- and post-synaptic spikes may lead to a change in the synaptic weight. If tpost−tpre do not meet either of the two criteria in Equation (9), the weight is not changed, i.e. Δw=0.” That is, “tpost−tpre” corresponds to a processing timing latency based on a time that corresponds to the input to a neuron (tpre, the presynaptic neuron’s spike) and a time that corresponds to the output of the neuron. That is, the latency tpost−tpre is used to update the weights as represented by the equation for Δw. This weight update and its associated equations correspond to a synaptic weight update function.]
Nadafian further teaches “at which a spike signal is received from an adjacent neuron module” [§ 1, paragraph 1: “Normally, the synaptic delay (d) is not considered in firing time difference (Dt) of typical STDP, but in the case of existing delays over synapses, we need to take it into account so that the STDP correctly adjusts the synaptic weights by considering the effect of the delay on the spike timing of the post-synaptic neuron. Therefore, for two connected neurons and j, the STDP adjusts their synaptic weight wi,j with respect to the firing time difference as well” as the current synaptic delay (di,j). The equations for delay-related STDP are as follow…[see equation in text].” That is, referring to the equation referred to in the above part of the text, the factor of (ti + di,j) corresponds to the time at which a corresponding neuron module receives an input spike signal from an adjacent neuron module, since the time at which the neuron receives the input spike signal is the firing time of the presynaptic neuron (i.e., ti) plus the synaptic delay di,j. Note that ti and tj here refer to the same times as tpre and tpost, and that since (ti + di,j) is subtracted from tj, it is written as -ti -di,j in the equation. Note that the equation for Δwi,j is an extension of the standard STDP weight update equation.]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of the references combined thus, including the teachings of Nadafian, so as to have also arrived at the claimed invention of the instant dependent claim. The motivation for doing so is covered by the motivation given for Nadafian in the rejection of the parent independent claim.
As to claim 6, the combination of Imam, Cherubini, and Nadafian teaches the method of claim 1, as set forth above.
Cherubini further teaches “wherein the constructing comprises determining at least one of connectivities of the plurality of neuron modules and a connection distance between the plurality of neuron modules.” [Cherubini “[0056] The method 100 further comprises classifying, at step 110, an element into a class (such as out of a group of classes) depending on a distance measure value between output spiking patterns at output spiking neurons of the spiking neural network and a predefined target pattern related to the class [i.e., determining at least one of connectivities of the plurality of neuron modules and a connection distance between the plurality of neuron modules]. Cherubini, [0057]: “FIG. 2a shows a block diagram 200 of a theoretical neuron 202. The neuron 202 receives a plurality of spike patterns of spike trains 204, 206, and 208. It may be understood that synapses exist over the inter-neuronal connections indicated by the arrows touching the neuron 202. Based on the received spike patterns, an output signal 210 is generated.”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further combined the teachings of Imam and Cherubini, including the teachings of Cherubini noted for the above limitations of instant dependent claim, so as to arrive at the claimed invention. The motivation would have been to utilize a measure that enables classification of an element into a class, as suggested by Cherubini (see part cited above).
As to claim 8, the combination Imam, Cherubini, and Nadafian teaches the method of claim 1, wherein
the operation mode comprises any one or any combination of any two or more of the visible mode, the hidden mode, a relay mode, and a block mode, [As noted in the rejection of claim 1, referring to FIG. 5C of Imam, for example, neuron 6 may be regarded as being determined to be in a visible mode because it is subject to an input external to the neuromorphic computing device.] and
the determining comprises determining an operation mode of one neuron module of the neuron modules included in the subarray to be the visible mode. [The use of the neuron to be subject to the input external to the neuromorphic computing device, as described in Iman in connection with FIG. 5C, constitutes “determining” it.]
As to claim 9, the combination of Imam and Cherubini teaches the method of claim 8, wherein the mapping comprises mapping the target pattern to the one neuron module operating in the visible mode. [Imam, [0055]: “Turning to FIG. 5C, a certain one of the neurons in the SNN (e.g., Neuron 6) may be activated 505 (e.g., by providing an input to the neuron or externally driving the neuron (through a controller internal or external to the neuromorphic computing device)) to cause the neuron to send a spike to its neighboring neurons (e.g., Neurons 4, 8, and 9).” Imam, [0031]: “signals may be provided by a controller (e.g., 224) internal or external to the neuromorphic computing device (e.g., in connection with a particular application or algorithm utilizing the SNN)…” Imam, [0108]: “The core may then use time multiplexing to turn to another, second one of the neurons implemented by the core during the same time step n=0 (i.e., but in another portion of the time step), process 1384 any inputs (e.g., external input currents or spike messages from other neurons in the SNN) and determine whether any such inputs caused the potential of the neuron to meet or exceed its firing threshold (and cause a spike to be sent (either in the same or an immediately subsequent time step, depending on the configuration of the SNN)).”]
As to claim 10, the combination of Imam, Cherubini, and Nadafian teaches a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, configure the processor to perform the operating method of claim 1. [Imam, [0112]: “Processor 1400 can execute any type of instructions associated with algorithms, processes, or operations detailed herein.” Imam, [0113]: “Code 1404, which may be one or more instructions to be executed by processor 1400, may be stored in memory 1402”]
As to claims 11-15, these claims recite substantially the same limitations as claims 1-4 and 6 in the form of a device, and are therefore rejected under the same rationale given for claims 1-4 and 6, respectively.
Furthermore, Imam teaches “a device comprising a processor” [[0022]: “As used in this document, the term “computer,” “processor,” “processor device,” or “processing device” is intended to encompass any suitable processing apparatus. For example, elements shown as single devices within the computing environment 100 may be implemented using a plurality of computing devices and processors, such as server pools including multiple server computers.”]
As to claim 16, the combination of Imam, Cherubini, and Nadafian teaches the device of claim 11,
wherein the neuron modules are configured to operate in any one or any combination of any two or more of a visible mode, a hidden mode, a relay mode, and a block mode, [As noted in the rejection of claim 1, Imam teaches neurons that operate in a visible mode. Imam also teaches a “block mode” (see [0083]: “In some cases, a node may be designated as an absolute or impassible hazard, such that no network paths should be determined that traverse the hazard node.”).] and
the processor is further configured to construct determine an operation mode of one neuron module of the neuron modules included in the subarray to be the visible mode, [As noted in the rejection of claim 1, referring to FIG. 5C of Imam, for example, neuron 6 may be regarded as being determined to be in a visible mode because it is subject to an input external to the neuromorphic computing device. In other words, use of a neuron to receive an external input constitutes determining that its operational mode is that of a visible mode. Furthermore, the use of hidden neurons is taught by Cherubini in the existing combination of references, and such use also includes the determination of those neurons.] and map the target pattern to the neuron module operating in the visible mode. [Imam, [0055]: “Turning to FIG. 5C, a certain one of the neurons in the SNN (e.g., Neuron 6) may be activated 505 (e.g., by providing an input to the neuron or externally driving the neuron (through a controller internal or external to the neuromorphic computing device)) to cause the neuron to send a spike to its neighboring neurons (e.g., Neurons 4, 8, and 9).” Imam, [0031]: “signals may be provided by a controller (e.g., 224) internal or external to the neuromorphic computing device (e.g., in connection with a particular application or algorithm utilizing the SNN)…” Imam, [0108]: “The core may then use time multiplexing to turn to another, second one of the neurons implemented by the core during the same time step n=0 (i.e., but in another portion of the time step), process 1384 any inputs (e.g., external input currents or spike messages from other neurons in the SNN) and determine whether any such inputs caused the potential of the neuron to meet or exceed its firing threshold (and cause a spike to be sent (either in the same or an immediately subsequent time step, depending on the configuration of the SNN)).”]
2. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Imam in view of Cherubini and Nadafian, and further in view of Van Der Made et al. (US 2020/0143229 A1) (hereinafter “Van Der Made”).
As to claim 5, the combination of Imam, Cherubini, and Nadafian teaches the method of claim 4, as set forth above, but does not teach the further limitations of the instant dependent claim.
Van Der Made teaches “wherein a neuron module of the neuron modules is configured to, when operating in the relay mode, store a direction in which the spike signal is input to the synapse module in a previous cycle, determine another direction in which the spike signal is to be transmitted in a subsequent cycle based on the direction in which the spike signal is input, and transmit the spike signal in the determined another direction.” [Van Der Made, [0073]: “In some embodiments, each layer can include two data structures that describe the connectivity between spiking neuron circuits in the layer and the inputs to the neurons. The first data structure can be referred to as a connection list array. Entries in the connection list array can correspond to a list of spiking neuron circuits to which a specific input is connected. The connection list array can contain connectivity information from source to destination.” Van Der Made, [0074]: “The second data structure can be referred to as a weight vector array. Each entry in the weight vector array corresponds to a vector of inputs to which a specific spiking neuron circuit is connected. The weight vector array can contain destination to source information.” (Note: an array can contain connectivity information from source to destination, it implies storing direction, since destination to source is a direction.). Van Der Made, [0075]: “In some embodiments, each spiking neuron circuit in a fully connected layer type has a single entry in the potential array. In contrast, in some embodiments, the spiking neuron circuits of a convolution layer can share a single set of synaptic weights that is applied to x-y coordinates across every input channel. The synaptic weight can be stored in destination to source format in the weight vector array [store a direction].” (Note: the network records the directional relationship between neurons, aligning with the concept of storing directional information) Van Der Made, [0079]: “FIG. 1 is a block diagram of a neural network model, according to some embodiments. In FIG. 1, spikes can be communicated over a local bus 101. For example, local bus 101 can be a network on a chip (NoC) bus. The spikes can be communicated in the form of network packets. A network packet can contain one or more spikes and a code indicating origin and destination addresses.”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have combined the teachings of the references combined thus far with the teachings of Van Der Made by modify the method of Imam, as already modified thus far, to incorporate storing the direction of the spike signal in relay mode. Doing so would enable connections between neurons and synapses of a SNN to be reprogrammed based on a user defined configuration (see Van der Made, [0039]: “Embodiments herein solve this technological problem by allowing the connections between neurons and synapses of a SNN to be reprogrammed based on a user defined configuration. For example, the connections between layers and neural processors can be reprogrammed using a user defined configuration file.”), and to enable the use of a connection list to update all membrane potential values of connected neurons (see Van der Made, [0044]: “This enables embodiments herein to only have to consider a single connection list to update all the membrane potential values of connected neurons in the current layer.”).
3. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Imam in view of Cherubini and Nadafian, and further in view of Sengupta et al. (US 2018/0189648 A1) (hereinafter “Sengupta”).
As to claim 17, the combination of Imam, Cherubini, and Nadafian teaches the limitations of claim 11, but does not teach the further limitation of the instant dependent claim.
Sengupta teaches “wherein the device is a smartphone.” [Sengupta, [0098]: “In FIG. 9, an embodiment of a system on-chip (SOC) design in accordance with the disclosures is depicted. In a particular embodiment, an SOC may include a neural network as described herein. As a specific illustrative example, SOC 900 is included in user equipment (UE). In one embodiment, UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Often a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have combined the teachings of the references combined thus far with the teachings of Sengupta by modifying the device in Imam, as modified thus far, to be a smartphone as taught in Sengupta. Doing so would have been an obvious combination of prior art elements according to known methods to yield predictable results (MPEP § 2143(I)(A)). Specifically, one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately (since Imam, [0022] teaches that the computer can be implemented in diverse forms, including those that run Android and iOS, and Sengputa teaches that smartphones are a known type of general purpose computer); and one of ordinary skill in the art would have recognized that the results of the combination were predictable (specifically, the predictable result of using a smartphone as the device to perform the operations recited in the instant claim).
4. Claims 18-19 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Imam in view of Nadafian.
As to claim 18, Imam teaches a device, comprising:
a synapse module comprising a first processor; [[0026]: “each core houses the computing elements including neurons, synapses with on-chip learning capability, and local memory to store synaptic weights and routing tables.” [0032]: “the router network of the device may similarly enable connections, or artificial synapses (or, simply, “synapses”), to be defined between any two of the potentially many (e.g., 30,000+) neurons defined using the network of neuromorphic cores provided in a neuromorphic computing device.” That is, a core, is a processor, is regarded as a synapse module when performing the functions of a synapse.]
a soma module comprising a second processor; [[0034]: “Each neuromorphic core may additionally include logic to implement, for each neuron 275, an artificial dendrite 280 and an artificial soma 185 (referred to herein, simply, as “dendrite” and “soma” respectively). The dendrite 280 may be a hardware-implemented process that receives spikes from the network. The soma 285 may be a hardware-implemented process that receives each dendrite's accumulated neurotransmitter amounts for the current time and evolves each dendrite and soma's potential state to generate outgoing spike messages at the appropriate times.” That is, the core, when performing the functions of a soma, constitutes a second processor. The Examiner notes that the first, second, third, etc. processors of the instant claim can be the same physical device.]
an axon module comprising a third processor; [[0029]: “a neuromorphic computing device 205 may be provided with additional logic to implement various features and models of an artificial neuron, artificial synapse, soma, or axon, etc.” That is, the core, when performing the functions of an axon, constitutes a third processor.] and
an external signal input/output module comprising a fourth processor, [[0031]: “An external interface 260 may be provided through which external systems may receive, inspect, or otherwise access data (e.g., traffic on routers of the neuromorphic computing device describing spike messaging between neurons implemented using the neuromorphic computing device). As an example, outputs of an SNN (e.g., from neurons in an output layer of the SNN or specific neurons connected to a controller of a consumer system) may be provided to an outside system via external interfaces 260 of the neuromorphic computing device.” See also [0028]: “providing inputs to an implemented SNN on the neuromorphic computing device 205 (e.g., in connection with a particular algorithm or procedure), among other examples.”].
wherein the synapse module is configured to transmit a synaptic weight to the soma module based on an input spike signal received from a first axon module of a first adjacent neuron module, [[0026]: “local memory to store synaptic weights and routing tables.” [0035]: “Computation occurs in each neuron as a result of the dynamic, nonlinear integration of weighted spike input.” [0041]: “Spike messages may identify a particular distribution set of dendrites within the core. Each element of the distribution set may represent a synapse of the modeled neuron…The soma process, at each time step, receives an accumulation of the total spike weight received (WeightSum) via synapses mapped to specific dendritic compartments of the soma.” That is the synapses transmits weights to the soma processes (and thus the system components corresponding to a “soma module”). The spike message corresponds to an input spike from an adjacent neuron (see, e.g., FIG. 5C for an illustration of transmissions of spike messages between adjacent neurons).] including measuring a processing timing latency from a first point in time […] to a second point in time at which the soma module outputs an output spike signal triggered by the input spike signal [[0048]: “In one model, STDP within a neuromorphic computing device may be implemented such that whenever there is a spike in the presynaptic neuron or the postsynaptic neuron, the weight at the associated synapse is changed according to Equation (9) [see equation in text]… where Δw is the change in weight applied to a synapse between a presynaptic neuron and a postsynaptic neuron, tpost is the latest time of spike of the postsynaptic neuron, tpre is the latest time of spike of the presynaptic neuron, δ1 and δ2 are tunable parameters that set the rate and direction of learning, and d is another tunable parameter that sets a time window in which co-occurring pre- and post-synaptic spikes may lead to a change in the synaptic weight. If tpost−tpre do not meet either of the two criteria in Equation (9), the weight is not changed, i.e. Δw=0.” That is, “tpost−tpre” corresponds to a processing timing latency based on a time that corresponds to the input to a neuron (tpre, the presynaptic neuron’s spike) and a time that corresponds to the output of the neuron. Furthermore, in this context, pre-synaptic constitutes an “adjacent” neuron because it inputs into the neuron that fires (i.e. the postsynaptic neuron).] and updating the synaptic weight based on the processing timing latency from the first point to the second point, using a synaptic weight update function that receives the measured processing timing latency as a variable input for calculating a delta weight value, [[0048]: “where Δw is the change in weight applied to a synapse between a presynaptic neuron and a postsynaptic neuron, tpost is the latest time of spike of the postsynaptic neuron, tpre is the latest time of spike of the presynaptic neuron, δ1 and δ2 are tunable parameters that set the rate and direction of learning, and d is another tunable parameter that sets a time window in which co-occurring pre- and post-synaptic spikes may lead to a change in the synaptic weight. If tpost−tpre do not meet either of the two criteria in Equation (9), the weight is not changed, i.e. Δw=0.” That is, the latency tpost−tpre is used to update the weights as represented by the equation for Δw. This weight update and its associated equations correspond to a synaptic weight update function. See [0059]: “In the parlance of machine learning, the example of FIG. 5C may correspond to a training phase of an example SNN modeling a particular network topography and FIG. 5D may reflect the resulting trained SNN. With the synaptic weights of the bi-directionally connected neurons strengthened in a direction opposite to the direction of the spike wave generated by one of the neurons (e.g., Neuron 6) according to an STDP rule defined for the SNN, the adjusted synaptic weights may be leveraged to determine a shortest path from any one of the neurons to the neuron (e.g., Neuron 6).”]
the soma module is configured to accumulate signals received from the synapse module and the external signal input/output module, and output an output spike signal in response to a value of the accumulated signals being greater than or equal to a predetermined threshold value, [[0033]: “Each neuromorphic core 215 may additionally provide local memory in which a routing table may be stored and accessed for a neural network, accumulated potential of each soma of each neuron implemented using the core may be tracked, parameters of each neuron implemented by the core may be recorded, among other data and usage.” [0041]: “The soma process, at each time step, receives an accumulation of the total spike weight received (WeightSum) via synapses mapped to specific dendritic compartments of the soma.” [0042]: “As neuron 305 receives spike messages from the other neurons it is connected to, the potential of the neuron 305 may exceed a threshold defined for the neuron 305 (e.g., defined in its soma process) to cause the neuron 305 itself to generate and transmit a spike message.”] and
the axon module is configured to transmit the output spike signal to a second synapse module of a second adjacent neuron module. [[0042]: “As neuron 305 receives spike messages from the other neurons it is connected to, the potential of the neuron 305 may exceed a threshold defined for the neuron 305 (e.g., defined in its soma process) to cause the neuron 305 itself to generate and transmit a spike message.” Note that the process of transmitting a spike is an axon process, as described in [0092]: “In one example, a neuron response delay may be configured by adjusting an axonal delay parameter of synapses providing incoming spikes to the neuron. The axonal delay parameter may be tuned to cause a delay in the neuron processing an incoming spike (e.g., using its soma process), thereby leading to a corresponding delay in the response of the neuron to incoming spikes.”]
Imam does not teach does not teach the limitation of the first time being a time “at which the soma module receives the input spike signal from the first axon module of the first adjacent neuron module.”
Nadafian teaches a first point in time “at which a corresponding neuron module receives an input spike signal from an adjacent neuron module.” [§ 1, paragraph 1: “Normally, the synaptic delay (d) is not considered in firing time difference (Dt) of typical STDP, but in the case of existing delays over synapses, we need to take it into account so that the STDP correctly adjusts the synaptic weights by considering the effect of the delay on the spike timing of the post-synaptic neuron. Therefore, for two connected neurons and j, the STDP adjusts their synaptic weight wi,j with respect to the firing time difference as well” as the current synaptic delay (di,j). The equations for delay-related STDP are as follow…[see equation in text].” That is, referring to the equation referred to in the above part of the text, the factor of (ti + di,j) corresponds to the time at which a corresponding neuron module receives an input spike signal from an adjacent neuron module, since the time at which the neuron receives the input spike signal is the firing time of the presynaptic neuron (i.e., ti) plus the synaptic delay di,j. Note that ti and tj here refer to the same times as tpre and tpost, and that since (ti + di,j) is subtracted from tj, it is written as -ti -di,j in the equation. Note that the equation for Δwi,j is an extension of the standard STDP weight update equation.]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Imam with the teachings of Nadafian by implementing the technique of taking into account the synaptic delay such that the first point in time is a time at which a corresponding neuron module receives an input spike signal from an adjacent neuron module. Doing so would have enabled consideration of delays over synapses, in order to make computational models more effective in providing aligned insights with experimental evidences (see Nadafian, § 1, second-to-last paragraph: “However, ignoring the delays makes these computational models ineffective in providing aligned insights with the experimental evidences.”).
As to claim 19, the combination of Imam and Nadafian teaches the device of claim 18, wherein the soma module comprises:
an accumulator configured to accumulate the signals received from the synapse module and the external signal input/output module; [Imam, [0041]: “The soma process, at each time step, receives an accumulation of the total spike weight received (WeightSum) via synapses mapped to specific dendritic compartments of the soma. In the simplest case, each dendritic compartment maps to a single neuron soma. In other instances, a neuromorphic core mesh architecture may additionally support multi-compartment neuron models. Core memory may store the configured attributes of the soma and the state of the soma, the total accumulated potential at the soma, etc.”] and
a comparator configured to compare the value of the accumulated signals to the threshold value. [Imam, [0042]: “As neuron 305 receives spike messages from the other neurons it is connected to, the potential of the neuron 305 may exceed a threshold defined for the neuron 305 (e.g., defined in its soma process) to cause the neuron 305 itself to generate and transmit a spike message.” Note that the comparison is described in the equations mentioned in Imam, [0043]-[0044]. See [0044]: “Equation (3) may define the spiking event of a neuron. When a neuron's membrane potential reaches a particular threshold potential θ defined for the neuron, the neuron (e.g., through its soma process) resets the membrane potential to zero, and sends out a spike to neighboring neurons connected by corresponding synapses.”]
As to claims 23-24, these claims are directed to an operating method including the same or substantially the same operations as those of claims 18-19. Therefore, the rejections made to claims 18-19 are applied to claims 23-24, respectively.
5. Claims 21 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Iman in view of Nadafian, and further in view of Chen et al. (US 9,984,326 B1)
As to claim 21, the combination of Imam and Nadafian teaches the device of claim 18, wherein the axon module […] transmit the received output spike signal to the second synapse module after a predetermined time period. [[0090]: “Neurons designated as corresponding to hazard nodes (or “hazard neurons”) may be configured instead to send postsynaptic spikes on a delay (or not at all) in response to presynaptic spikes received (in spike waves) at the hazard neuron.”]
The function of “receive the output spike signal from the soma module” and the limitation of that the axon modules comprises a “delay buffer” configured to perform the receive and transmit operations.
Chen teaches “receive the output spike signal from the soma module” and a “delay buffer” configured to perform the receive and transmit operations. [Col. 11, lines 19-39: “The module output spike buffer (i.e., outBuffer 408) can hold a certain history of output spikes in a FIFO (first-in-first-out) fashion. The length of the spike history is determined by parameter D 506 in module status 402 described above. D 506 represents the maximum axon delays for the spikes going out from this module. Different amounts of delays (up to D time steps) can be specified in the input spike buffer (inputBuffer 404) of the modules receiving the spikes from current module. These spikes can then be extracted by the receiving modules (including the current module itself in a recurrent network) as input spikes with the specified delays in the spike propagation step. Non-limiting examples of how the module output spike buffer (i.e., outBuffer 408) can be updated and how the spikes it stores can be delivered to the receiving modules are described below…. storing delayed spikes in the output spike buffer can save both memory and computation in general.”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have to combined the teachings of the references combined thus war with the teachings of Chen by implementing the axon module to include a delay buffer configured to receive the output spike signal from the soma module and perform the transmit. Doing so would have enabled the implementation of specified delays in spike propagation in a manner that that save both memory and computation, as suggested by Chen (see parts quoted above, including last paragraph of the quoted section which states: “storing delayed spikes in the output spike buffer can save both memory and computation in general”).
As to claim 26, the further limitations recited in this claim are the same or substantially the same as those included in claim 21. Therefore, the rejection 21 is applied to claim 26.
6. Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Iman in view of Nadafian, and further in view of Sengupta et al.
As to claim 22, the combination of Imam and Nadafian teaches the limitations of claim 11, but does not teach the further limitation of the instant dependent claim.
Sengupta teaches “wherein the device is a smartphone.” [Sengupta, [0098]: “In FIG. 9, an embodiment of a system on-chip (SOC) design in accordance with the disclosures is depicted. In a particular embodiment, an SOC may include a neural network as described herein. As a specific illustrative example, SOC 900 is included in user equipment (UE). In one embodiment, UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Often a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have combined the teachings of the references combined thus far with the teachings of Sengupta by implementing the device in Imam, as modified thus far, to be a smartphone as taught in Sengupta. Doing so would have been an obvious combination of prior art elements according to known methods to yield predictable results (MPEP § 2143(I)(A)). Specifically, one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately (since Imam, [0022] teaches that the computer can be implemented in diverse forms, including those that run Android and iOS, and Sengputa teaches that smartphones are a known type of general purpose computer); and one of ordinary skill in the art would have recognized that the results of the combination were predictable (specifically, the predictable result of using a smartphone as the device to perform the operations recited in the instant claim).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following document depicts the state of the art.
Wang et al., “A Delay Learning Algorithm Based on Spike Train Kernels for Spiking Neurons,” Front. Neurosci., 26 March 2019 Sec. Neuromorphic Engineering teaches the modeling of the synaptic delay to account for the time when the receiving neuron receives a spike.
Rodriguez (US 11875245 B1) teaches the modeling of the synaptic delay (see column 6).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAO DAVID HUANG whose telephone number is (571)270-1764. The examiner can normally be reached Monday - Friday 9:00 am - 5:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Miranda Huang can be reached at (571) 270-7092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Y.D.H./Examiner, Art Unit 2124
/Kevin W Figueroa/Primary Examiner, Art Unit 2124
Prosecution Insights