Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This is in reply to arguments filed on 10/22/2025. Status of claims are:
** Claims 1-10 are pending.
** Claim 1 is amended.
Response to Arguments
2. Applicant’s arguments filed in the amendment filed 10/22/2025, have been fully considered but are moot in view of new grounds of rejection. The reasons set forth below.
Prior Art
3. U. S. Patent Pub No. 20180121506 A1 to Barbosa Fagnani Gomez Lotz et al., (hereinafter Barbosa).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 20210160712 A1 to Tadayon et al., (hereinafter Tadayon) in view of US 20160110228 A1 to Zhang (hereinafter Zhang) and in further view of US 20180121506 A1 to Barbosa Fagnani Gomez Lotz et al., (hereinafter Barbosa).
Claim 1. A method of clock synchronization for a distributed network, the method comprising the steps of:
(a) representing the distributed network as a graphical model, the graphical model comprising a set of nodes, wherein selected pairs of nodes in direct electronic communication with one another are shown connected by edges; (Tadayon: See para[0205] and Fig. 18 for a “connectivity graph” (i.e., a graphical model) consisting of a set of nodes in direct communication with one another, including edges)
each sub-graph connecting the selected pairs of nodes in direct electronic communication with one another, (Tadayon: See para[0211], and Fig. 19 for pairs of nodes connected together and in direct communication with one another via edges in bi-directional paths.) wherein each sub-graph includes a selection of closed loops between the plurality of nodes; (Tadayon: See para[0211] and Fig. 19, for each sub-graph, consists of one connectivity circle (i.e. one closed loop) including plurality of nodes communicating via links)
(c) determining the influence of each closed loop within each sub-graph; (Tadayon: See para[0248] for connectivity graphs (i.e. sub-graphs) are determined based on a comparison of any of the three graphs (i.e., three subgraphs), wherein each of three graph (i.e., subgraph) includes edges as shown in Fig. 18 and 19 that can be removed from the map)
(d) dynamically identifying a selection of edges for deletion in the graphical model based on the influence of each closed loop within each sub-graph, (Tadayon: See para[0239] for connectivity graph may be pruned by removing edges when their received signal power falls below a threshold amount.) and
(e) applying a synchronization algorithm to the optimized graphical model to calculate a clock synchronization solution. (Tadayon: See para[0146]-[0153] for estimating clock synchronization errors among nodes/edges of graph is done by using “a formula” (i.e., a synchronization algorithm) in order to correct the clock synchronization between different nodes/edges of the connectivity graph)
the deletion of edges from the graphical model yielding an optimized graphical model;
(Tadayon: See para[0239] for the graph may be pruned (i.e., specific form of optimization in machine learning and computer science) by removing edges for which received power falls below a threshold)
Tadayon does not seem to explicitly disclose:
(b) dissecting the graphical model into a sequence of time-varying directed sub-graphs,
However, in a similar field, Zhang in para[0022] and Fig. 1, teaches a graph can be divided into subgraphs during a first-time subdivision and then further performing a second-time subdivision on the first-time subdivided sub-graphs (i.e., time-varying sub-graphs).
Tadayon teaches synchronizing clocks of a network graph, wherein the graph can consists of various subgraphs by applying a specific formula or algorithm, among other things. (Tadayon: See para[0146]-[0153])
Zhang teaches a graph can be divided into subgraphs during a firt-time subdividion and theun further performing a second time subdivision on the first-time subdivided sub-graphs. (Zhang: see para[0022])
It would have been obvious to one of ordinary skill in the art before the effective time of filing, to have included, graph subdividing at different times, as taught by Zhang, with the teachings of Tadayon in view of Bouton, in order to benefit from the functional ability to subdivide a graph into subgraphs at different times. (Zhang: See para[0022])
Tadayon in view of Zhang does not specifically teach the notion of directed edges that connect a source to a destination via a single one-way direction as understood by:
using directed edges having at most a single one-way directional path
However, in a similar field, Barbosa in para[0016] teaches that certain edges can be directed edges that have a direction connecting a source to a destination node, that only works in one way path. (Barbosa: See para[0016])
Tadayon teaches synchronizing clocks of a network graph, wherein the graph can consists of various subgraphs by applying a specific formula or algorithm, among other things. (Tadayon: See para[0146]-[0153])
Zhang teaches a graph can be divided into subgraphs during a firt-time subdividion and theun further performing a second time subdivision on the first-time subdivided sub-graphs. (Zhang: see para[0022])
Barbosa teaches that certain edges can be directed edges that have a direction connecting a source to a destination node, that only works in one way path. (Barbosa: See para[0016])
It would have been obvious to one of ordinary skill in the art before the effective time of filing, to have included directed edges having a one way path, as taught by Barbosa, with the teachings of Tadayon and Zhang, in order to benefit from having one way directional edges that connect a source node to a destination node in only one way. (Barbosa: See para[0016])
Claim 2. The method as claimed in claim 1 wherein the synchronization algorithm utilized in the algorithm application step is a message-passing algorithm. (Tadayon: See para[0270] for message passing algorithm used for optimization)
Claim 3. The method as claimed in claim 2 wherein the synchronization algorithm utilized in the algorithm application step is a sum-product message-passing algorithm. (Tadayon: See para[0147] synchronization errors are estimated by using a specific formula/algorithm (i.e., a sum-product massage-passing algorithm)).
Claim 4. The method as claimed in claim 2 further comprising the step of, prior to the algorithm application step, compensating for message-passing errors. (Tadayon: See para[0003] for the transmitter compensating error increases when the signal to noise ratio drops resulting in increased bit error rates.)
Claim 5. The method as claimed in claim 4 further comprising the step of, prior to the algorithm application step, compensating for message noise. (Tadayon: See para[0003] for the transmitter compensating error increases when the signal to noise ratio drops resulting in increased bit error rates.)
Claim 6. The method as claimed in claim 2 wherein, in the determining step, the influence of each closed loop within each sub-graph is quantified by comparing differences between multiple sub-graphs. (Tadayon: See para[0248] for connectivity graphs (i.e. sub-graphs) is based on a comparison of any of the three graphs (i.e., three subgraphs), wherein each of three graph (i.e., subgraph) includes nodes and edges)
Claim 7. The method as claimed in claim 6 wherein, as part of the determining step, closed loops which are determined to be biased are mitigated. (Tadayon: See para[0239] the connectivity graph (i.e., graphs/sub-graphs or circles/closed loops) may be pruned by removing edges from it if their received signal power falls below a threshold amount.)
Claim 8. The method as claimed in claim 7 wherein, as part of the determining step, closed loops which are determined to be benign are maintained. (Tadayon: See para[0239] the connectivity graph (i.e., graphs/sub-graphs or circles/closed loops) may be pruned by removing edges from it if their received signal power falls below a threshold amount)
Claim 9. The method as claimed in claim 2 wherein an edge deletion algorithm is applied in the edge identification step to identify a selection of edges for deletion in the graphical model. (Tadayon: See para[0239] the connectivity graph (i.e., graphs/sub-graphs or circles/closed loops) may be pruned by removing edges from it if their received signal power falls below a threshold amount)
Claim 10. The method as claimed in claim 2 wherein the edge deletion algorithm utilizes a hierarchically semiseparable (HSS) structure. (Tadayon: See para[0089] for each processing units includes any suitable processing device configured to perform one or more operations (e.g., edge deletion), such as microprocessors, digital signal processors, programmable gate arrays, or application specific integrated circuits(i.e., hierarchically semiseparable (HSS) structure))
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAJID ESMAEILIAN whose telephone number is (571)270-7830. The examiner can normally be reached on M-F. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Gregory Sefcheck can be reached on 571-272-3098. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M. E./
Examiner, Art Unit 2477
/GREGORY B SEFCHECK/Primary Examiner, Art Unit 2477