DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim interpretation. Interpretation of claim limitations under 35 USC 112(f) is withdrawn based on amendment to claims.
Specification. The objection to the specification is withdrawn based in amendment to claims, wherein claim limitations are no longer interpreted under 35 USC 112(f).
35 USC 112(a). The rejection of claims 18-20 under 35 USC 112(b) is withdrawn based on amendment to claims, wherein claim limitations are no longer interpreted under 35 USC 112(f).
35 USC 112(b).
The rejection of claim 17 under 35 USC 112(b) for being indefinite as the bounds of the claim are unclear is withdrawn based on amendment to claims.
The rejection of claims 18-20 under 35 USC 112(b) is withdrawn based on amendment to claims, wherein the claim limitations are no longer interpreted under 35 USC 112(f).
35 USC 101.
Applicant asserts the claims are directed to a specific data structure that improves computer memory efficiency, not to an abstract mathematical concept (Remarks p. 23).
Examiner respectfully disagrees. What is specific is in the description and ordering of the look up table based on the mathematical relationships and as one might do with pen and paper. The additional elements related to the memory which stores the table is merely generically recited, and recited in a manner with the processor that merely “applies it” in a computer. Furthermore, the application to a k-cluster residue number system of an edge artificial intelligence (AI) computing system merely generally links the abstract idea to a technological environment or field of use.
Applicant further asserts the claims are like the “self-referential table” of Enfish and the programmable memory system of Visual Memory (Remarks p. 23-264).
Examiner respectfully disagrees. As to Enfish, no particular structure is claimed as in Enfish which included structural limitations based on interpretation of claim elements under 35 USC 112f. Similarly, the claims do not recite structural limitations as in Visual Memory related to programmable characteristics of the memory system. The instant claims merely recite the abstract idea, a description of an ordering of a look up table based on the mathematical relationships as one might do on pen and paper. How this is implemented in additional elements beyond the general linking and “applying” is not specifically claimed.
Applicant further asserts the specific structural property of the data in memory provides technical improvements in memory compression, a unified arithmetic domain, and suitability for Edge AI (remarks p. 24-28).
Examiner respectfully disagrees. Any purported improvement flows as a direct result of the abstract idea, the description and ordering of the look up table, not from an improvement in the memory or the processor itself. Both exhibit A and figure 2 shown are representative of the mathematical relationships and describing of the lookup table exactly as one might do on pen and paper. No exhibit of an improvement in the memory itself or the processor is provided. Furthermore, a unified arithmetic domain is a mathematical concept, based on mathematical relationships, i.e., how to format mathematical data. Furthermore, any suitability for AI flows as a direct result of the mathematical relationships, not as a result of an improvement in technology itself.
Applicant asserts that the claims recite additional elements that integrate the abstract idea into a practical application, because the claims recite a specific memory configuration and a processor that utilizes this specific data structure to perform calculations . Furthermore the lookup table implementation using the kRNS approach provides a fundamentally different computational paradigm using a positional number system that incorporates modulus 2 with application in the negative domain , which allows efficient realization in hardware resources Remarks p. 28-29).
Examiner respectfully disagrees. What is specific is in the abstract idea, not the generically recited additional elements. Furthermore the positional number system is math, and any efficiency realization in hardware resources flows directly from the math. It is precisely the specific RNS data structure, the k-RNS where one modulus is 2, i.e., the math, which enables use of the generic hardware, a register and an XOR gate to perform the claimed function. “It is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology” (MPEP 2106.05(a)(II)). The “inventive concept cannot be furnished by the unpatentable law or nature (or natural phenomenon or abstract idea) itself”. MPEP 2106.05.I. See also MPEP 2106.05(a). "The judicial exception alone cannot provide the improvement".
Applicant further asserts that the claims provide a specific combination of memory storing a kRNS based lookup table with claimed row-index sharing, and a processor to utilize this lookup table that is not well understood, routine, or conventional, but rather an architecture innovation from the combination (Remarks p. 20).
Examiner respectfully disagrees. The combination of the memory and processor is a generic computer, which merely “applies” the abstract idea. What is arguably not well-understood, routine or conventional is the abstract idea.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 6-14, 16-20, and 22-28 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Regarding treatment of claims, apparatus claims 17-20, and 22-27 will be addressed first, followed by method claims 1-4, 6-14, 16, and 28.
Regarding claim 17, under the Alice Framework Step 1, claim 17 falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process, machine, manufacture, or a composition of matter.
Under the Alice Framework Step 2A prong 1, claim 17 recites mathematical concepts including mathematical relationships, mathematical calculations, and mental steps related to a residue number system. Specifically, the claim recites the following mathematical relationships and mathematical calculations:
a look-up table constructed based on a modular set composed of p coprime integers, wherein one of the p coprime integers is 2 and is designated as a modulus for column indices, the look-up table including:
row indices for all integers in the dynamic range defined by a produce of the p coprime integers; and
column indices for all integers in the dynamic range, wherein the look-up table is configured such that a set of the row indices maps to both a positive integer and a negative integer in the dynamic range, and the positive integer and the negative integer are distinguished by values of the corresponding column indices; and
utilize the look-up table based on the row indices of the look-up table and the column indices of the look-up table to perform calculations.
As disclosed in the specification, a residue number system defines the moduli set and transforms numbers to their integer remainders (also called residue) through modulo division [0003], and as claimed further described in the specification [0022]. Specification [0022] describes to represent an n-bit integer and its negative using a k-cluster residue number system (k-RNS), it first defines a modular set of p coprime integers as (m1,..., 2,..., mp) where a dynamic range is generated according to the product of the modular set (m1,..., 2,..., mp) . When a modular set of 3 coprime integers is chosen to be (2n/2-1, 2, 2n/2+1), the dynamic range is set to [- (2n-1), (2n-2) ] . The modular set is not limited to 3 coprime integers, the number of coprime integers in the modular set can be increased to increase the dynamic range and keep the moduli small. In this case, the k-RNS converts each integer in the dynamic range to its row indices and column index formed by remainders through modulo division such as Equation 1. Equation 1: ri=I mod mi
where:
ri is a row index or a column index; I is an integer in the dynamic range; and mi is a coprime integer of the modular set.
This is descriptive of mathematical relationships and mathematical calculations claimed, including generating a look-up table according to the row indices, the column indices and all integers in the dynamic range. The look-up table is reflective of the mathematical relationships of generating the indexes. Furthermore, generating a look-up table is also a mental step as one might do using pen and paper.
Using the look-up table to perform calculations is a mathematical calculation. See [0083-0091].
Under the Alice Framework Step 2A prong 2, claim 17 recites the following additional elements: a k-cluster residue number system of an edge artificial intelligence (AI) computing system, the k-cluster residue number system comprising: a memory and a processor of the k-cluster residue number system of the edge AI computing system. The additional elements merely generally link the abstract idea in a manner that merely recite “apply it” in a processor of the k-cluster residue number system. Furthermore performing the abstract idea for, and in an edge AI computing system merely generally links the abstract idea to a particular technological environment without reciting the steps being performed in a particular machine. Furthermore the storing of a look-up table comprises an insignificant extra-solution activity. For these reasons, claim 17 is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the claim contains no inventive concept being the abstract idea. As set for in the Step 2A prong 2 analysis the claims merely “apply” the abstract idea in a processor of the k-cluster residue number system generally, and merely generally link to a particular technological environment. Furthermore, the storing of a look-up table comprises well-understood, routine and conventional activity. See MPEP 2106.05(d).II.iv. storing and retrieving information in memory. For these reasons claim 1 does not amount to significantly more than the abstract idea.
Claims 18-20, and 22-27 are rejected for at least the reasons set forth with respect to claim 17.
Claims 18-20, and 22-26 further mathematically limits the apparatus as in claim 17. Claims 18-20, and 22-26 recite no further additional elements beyond those recited in the claim 17 analysis that would require further analysis under step 2A prong 2 and step 2B. For these reasons, claims 18-20 and 22-27 are neither integrated into a practical application, nor amounting to significantly more than the abstract idea.
Claim 27 further mathematically limits the apparatus as in claim 17. Under the step 2A prong 2 analysis, claim 27 recites the following further additional elements: retrieving, inputting a column index of the unknown integer to a first input of an XOR gate, and inputting the column index of the negative integer corresponding to the row indices of the unknown integer to a second input of the XOR gate to generate and output. The retrieving, inputting, outputting comprise an insignificant extra solution activity. As to the XOR gate, this limitation is recited at a high level of generality such that it merely generically links the additional elements to the math performed. The XOR gate merely implements the mathematical concept of an XOR function in Boolean logic such that the use of the XOR gate merely flows as a natural consequence of the math being performed. For these reasons, claim 27 is not integrated into a practical application. Under the step 2B analysis, the retrieving, inputting, outputting comprise well-understood, routine, and conventional activity. See MPEP 2106.05(d).II.iv. storing and retrieving information, i. receiving or transmitting data.. Furthermore, the XOR gate, this limitation is recited at a high level of generality such that it merely generically links the additional elements to the math performed. The XOR gate merely implements the mathematical concept of an XOR function in Boolean logic such that the use of the XOR gate merely flows as a natural consequence of the math being performed. For these reasons claim 27 does not amount to significantly more than the abstract idea.
Claim 1 is directed to a method that would be practiced by the apparatus as in claim 17 as configured. All steps recited in the method as in claim 1 are practiced by the apparatus as in claim 17 as configured. The claim 17 analysis applies equally to claim 1.
Claims 2-4, and 6-14, 16, and 28 are rejected for at least the reasons set forth with respect to claim 1. Claims 2-4, 6-14, and 16 merely further mathematically limit the abstract set forth in claim 1. Claims 2-4, 6-14, and 16 recite no further additional elements that would require further analysis under Step 2A prong 2 and Step 2B.
Claim 28 further mathematically limits the apparatus as in claim 3. Under the step 2A prong 2 analysis, claim 28 recites the following further additional elements: retrieving, inputting a column index of the unknown integer to a first input of an XOR gate, and inputting the column index of the negative integer corresponding to the row indices of the unknown integer to a second input of the XOR gate to generate and output. The retrieving, inputting, outputting comprise an insignificant extra solution activity. As to the XOR gate, this limitation is recited at a high level of generality such that it merely generically links the additional elements to the math performed. The XOR gate merely implements the mathematical concept of an XOR function in Boolean logic such that the use of the XOR gate merely flows as a natural consequence of the math being performed. For these reasons, claim 28 is not integrated into a practical application. Under the step 2B analysis, the retrieving, inputting, outputting comprise well-understood, routine, and conventional activity. See MPEP 2106.05(d).II.iv. storing and retrieving information, i. receiving or transmitting data.. Furthermore, the XOR gate, this limitation is recited at a high level of generality such that it merely generically links the additional elements to the math performed. The XOR gate merely implements the mathematical concept of an XOR function in Boolean logic such that the use of the XOR gate merely flows as a natural consequence of the math being performed. For these reasons claim 28 does not amount to significantly more than the abstract idea.
Allowable Subject Matter
For substantially the same reasons set forth in the office action dated 01/15/25, claims 1-4, 6-14, 16-20, and 22-28 would be allowable if rewritten to overcome the relevant rejections under 35 USC 101.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY E LAROCQUE whose telephone number is (469)295-9289. The examiner can normally be reached on 10:00am - 1200pm, 2:00pm - 8pm ET M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Andrew Caldwell can be reached on 571-272-3701. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
Prosecution Insights