DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 25 and 33 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 25 recites the limitation "the cache hit" in line 1. There is insufficient antecedent basis for this limitation in the claim because the first instance of ‘a cache hit’ was removed by the amendments to claim 21.
Claim 33 recites the limitation "the cache hit" in line 1. There is insufficient antecedent basis for this limitation in the claim because the first instance of ‘a cache hit’ was removed by the amendments to claim 29.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-22, 25-26, 28-30, and 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Hanebutte et al. (US Pub. No. 2008/0082743), hereinafter referred to as Hanebutte, in view of Segars et al. (US Patent No. 6021476), hereinafter referred to as Segars.
Referring to claims 21 and 29, Hanebutte discloses an apparatus comprising: a cache configured to store data (NV cache, [0021]); and circuitry (fig. 4) configured to maintain a plurality of entries (fig. 5) comprising cache-management metadata, each corresponding to a respective region of contiguous data stored in the cache (data with contiguous addresses may be merged into a block of data. A mapping table may be created and stored in the non-volatile cache which includes multiple entries, each for a block of data, [0014]; metadata includes the disk LBA of the actual data block, the size of the data block in sectors, and the cache LBA of the actual data block, [0032]); store, for each such region, an address in a cache address space (fig. 5, 510, Logical Block Address (LBA) on HDD) and a size defining a variable-length contiguous range of addresses in the cache (fig. 5, mapping table; block 1's disk LBA may be A; block 1 has X number of sectors…metadata includes the disk LBA of the actual data block, the size of the data block in sectors, [0031-0032]); and retrieve data from the cache responsive to a memory access request, based at least in part on identification of a region (read requests may be intercepted and the cached memory data may actually be read from the NV cache, [0022]; a read request…includes LBA-the logical start address of the data block on the HDD, and the sector count-size of the data block on the disk, [0030]) [0030]
While Hanebutte teaches storing a logical block address, the LBA does not does not appear to be explicitly disclosed as a starting address; and while Hanebutte teaches requests to the contiguous data and retrieving data from the cache, Hanebutte does not appear to check the cache by a starting address and size encompass the target address of the memory access.
However, Segars discloses a starting address (address ranges for the logical regions are specified by a base address identifying which memory location the region starts at, and a size attribute identifying the size of the logical region, col. 3, lines 5-15) and retrieving data whose stored starting address and size encompass the target address of the memory access, (compare the address on bus line 54 with the addresses in the cache to determine whether the data value corresponding to that address is stored within the cache. If so, the data value is output from the cache…Whenever a comparator determines that the address lies within the address range of a logical region, it outputs a hit signal, col. 6, lines 10-40).
Hanebutte and Segars are analogous art because they are from the field of endeavor, cache storage.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanebutte and Segars before him or her, to modify the storage system of Hanebutte to include the comparators of Segars because the comparators would provide granulized identification cached data.
The suggestion/motivation to do so would have been to improve the efficiency of the cache data retrieval (Segars: col. 2, line 60 to col. 3, line 10).
Therefore, it would have been obvious to combine Hanebutte and Segars to obtain the invention as specified in the instant claim.
As to claims 22 and 30, Hanebutte discloses for a given variable sized range of contiguous data stored in the cache, a corresponding entry identifies a size of the variable given sized range of contiguous data (fig. 5, 520 Number of Sectors; its corresponding block size in column 520...For example...block 1 has X number of sectors, [0031]).
As to claims 25 and 33, Hanebutte does not appear to explicitly disclose the cache hit is based on a comparison of a target address of the memory access to a range of addresses identified by the starting address and the size of the contiguous data stored in the cache.
However, Segars discloses the cache hit is based on a comparison of a target address of the memory access to a range of addresses identified by the starting address and the size of the contiguous data stored in the cache (address ranges for the logical regions are specified by a base address identifying which memory location the region starts at, and a size attribute identifying the size of the logical region, col. 3, lines 5-15; Each comparator is arranged to compare that address range with the particular address on bus line 54 to determine whether the address is contained within the corresponding logical region, col. 6, lines 30-40).
Hanebutte and Segars are analogous art because they are from the field of endeavor, cache storage.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanebutte and Segars before him or her, to modify the storage system of Hanebutte to include the comparators of Segars because the comparators would provide granulized identification cached data.
The suggestion/motivation to do so would have been to improve the efficiency of the cache data retrieval (Segars: col. 2, line 60 to col. 3, line 10).
Therefore, it would have been obvious to combine Hanebutte and Segars to obtain the invention as specified in the instant claim.
As to claims 26 and 34, Hanebutte discloses the circuitry is configured to detect overlap (fig. 6, step 605, check overlap and adjust mapping table) between a newly identified region of contiguous data and an existing region stored in the cache, and responsive to detecting the overlap, to modify the entry for the existing region to update the size of the region stored in the cache (fig. 6, step 640, modify current table entry; During the caching process, data with contiguous addresses may be merged into a block of data, [0014]; Column 520 includes number of sectors (or size of blocks with LBAs on HDD shown in column 510), [0031])
While Hanebutte anticipates modifying the LBA, Hanebutte does not appear to explicitly teach a starting address.
However, Segars discloses a starting address (address ranges for the logical regions are specified by a base address identifying which memory location the region starts at, and a size attribute identifying the size of the logical region, col. 3, lines 5-15).
The suggestion/motivation to combine remains as indicated above.
As to claim 28, Hanebutte discloses circuitry is configured to retrieve a plurality of data items stored contiguously in the cache as a region corresponding to an executing application (utilize the NV cache (such as flash memory) as a fast storage device for OS and applications combined with a slower storage device for data, [0027]). Furthermore, the claimed apparatus differs from Hanebutte in view of Segars in that while Hanebutte teaches the caching of data for an executing application and Segars teaches caching data and instructions, Hanebutte does not appear to explicitly disclose a correspondence of the cache data to the execution of a neural network, such that the data items correspond “to a set of inputs, weights, or parameters.” However the prior art performs the same function as it pertains to storing and managing contiguous data, which in the case of Hanebutte is disclosed as corresponding to “the operating system, all applications, open documents etc.” Therefore, the intended use of the apparatus for data corresponding to execution of a neural network would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, because the prior art of Hanebutte performs “the same function, albeit in a different environment.” (MPEP 2144.07).
Claims 23 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Hanebutte in view of Segars, as applied to claims 21-22, 25-26, 28-30, and 33-34 above, further in view of Lee et al. (US Pub. No. 2016/0054917), hereinafter referred to as Lee.
As to claims 23 and 31, while Hanebutte discloses the cache corresponds to a level of the processor’s memory hierarchy (fig. 4 memory 475, HDD 485, NV cache 490, system RAM, and HDD 190; Chipset 130 may include one or more integrated circuit packages or chips, [0016]), Hanebutte does not appear to explicitly disclose memory hierarchy architecture is on-chip or on-package memory hierarchy.
However, Lee teaches an on-chip memory hierarchy (fig. 3, on-chip memories 215 and 213, [0061-0063]).
Hanebutte, Segars, and Lee are analogous art because they are from the field of endeavor, block storage.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanebutte, Segars, and Lee before him or her, to modify the storage system of Hanebutte in view of Segars to implement the chip architecture of Lee, because the configuration would provide reduced size, power consumption, and transmission time.
The suggestion/motivation to do so would have been to reduce the resource requirements and consumption (Lee: [0059-60]).
Therefore, it would have been obvious to combine Hanebutte, Segars, and Lee to obtain the invention as specified in the instant claim.
Claims 24 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Hanebutte in view of Segars, as applied to claims 21-22, 25-26, 28-30, and 33-34 above, further in view of Suzuki et al. (US Pub. No. 2012/0072641), hereinafter referred to as Suzuki.
As to claims 24 and 32, the Hanebutte discloses each of the plurality of entries further stores region-specific metadata at a granularity smaller than the variable-length contiguous range (During the caching process, data with contiguous addresses may be merged into a block of data, [0014]; Column 520 includes number of sectors (or size of blocks with LBAs on HDD shown in column 510), [0031]; contiguous data blocks and creates one entry in the mapping table for these larger data blocks, [0032]).
The combination of Hanebutte in view of Segars does not appear to explicitly disclose the metadata comprising an offset for locating a target address within the region based on a difference between the target address and the starting address of the region.
However, Suzuki teaches an offset for locating a target address within the region based on a difference between the target address and the starting address of the region (calculates the PBA by finding an LBA relative address in the LBA group from the difference between the LBA and the start address of the corresponding LBA group, and then adding the start address of the PBA group to the LBA relative address; [0143]).
Hanebutte, Segars, and Suzuki are analogous art because they are from the field of endeavor, block storage.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanebutte, Segars, and Suzuki before him or her, to modify the storage system of Hanebutte in view of Segars to implement the logical unit configuration as taught by Suzuki, because the logical storage configuration would extend the storage areas to a plurality of host systems.
The suggestion/motivation to do so would have been to provide representation of the RAID storage areas to a plurality of hosts (Suzuki: [0048]).
Therefore, it would have been obvious to combine Hanebutte, Segars, and Suzuki to obtain the invention as specified in the instant claim.
Claims 27 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Hanebutte in view of Segars, as applied to claims 21-22, 25-26, 28-30, and 33-34 above, further in view in view of Verrilli et al. (US Pub. No. 2017/0286308), hereinafter referred to as Verrilli.
As to claims 27 and 35, while Hanebutte discloses modifying and removing mapping table entries instances such that an increase of the address of the region to correspond to a new beginning of the contiguous data in the cache (data block represented by the existing entry, that entry may be split into two or more entries with each having its new parameters (e.g., disk LBA, data size, and cache LBA), [0033]), and Segar discloses the starting address, the combination does not appear to explicitly disclose detecting a reduction in the size of the contiguous data stored in the cache and, responsive to the reduction updating the table entry.
However, Verrilli discloses (for each sub-line of the plurality of sub-lines of the eviction LLC line containing modified data, compressing data from the sub-line…storing the updated offset value and the updated length value in a master table entry for the sub-line in a master table, [0012])
Hanebutte, Segars, and Verrilli are analogous art because they are from the field of endeavor, cache storage.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanebutte, Segars, and Verrilli before him or her, to modify the storage system embodiment of Hanebutte in view of Segars to include eviction mechanism of Verrilli in order to update existing entries.
The suggestion/motivation to do so would have been to reduce access latency (Verrilli: [0030).
Therefore, it would have been obvious to combine Hanebutte, Segars, and Verrilli to obtain the invention as specified in the instant claim.
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Hanebutte in view of Segars, as applied to claims 21-22, 25-26, 28-30, and 33-34 above, further in view of Loh et al. (US Pub. No. 20130138892), hereinafter referred to as Loh.
As to claim 36, Hanebutte discloses the cache is included in a semiconductor chip (NV cache may be made of flash memory, [0027]).
While Hanebutte discloses the cache is configured to store a copy of data stored in an off-chip memory, the combination of Hanebutte in view of Segars does not appear to explicitly disclose the cache is a row-based three-dimensional (3D) dynamic random access memory (DRAM) and the off-chip memory as a die.
However, Loh discloses cache embodied as a row-based three-dimensional (3D) dynamic random access memory (DRAM) (see [0011-0012]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanebutte, Segars, and Loh before him or her, to substitute the anticipated cache architecture with the row-based three-dimensional (3D) dynamic random access memory (DRAM) taught by Loh because Loh demonstrates the specific cache architecture and function were known in the art and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable. The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP2143.I.B).
Furthermore, one of ordinary skill in the art would recognize there are a finite number of solutions to physical implementation of memory, the HDD of Hanebutte being one and the claimed die being another.
Accordingly, before the effective filing date of the claimed invention, it would have been “Obvious-to-Try” the claimed die as a solution to the off-chip storage, because “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense.” (see MPEP 2143.I.E).
Therefore, it would have been obvious to combine Hanebutte, Segars, and Loh to obtain the invention as specified in the instant claim.
Claims 37-38 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Hanebutte in view Segars, further in view of Lee, further in view of Atkisson et al. (US Pub. No. 2012/0221774), hereinafter referred to as Atkisson.
As to claim 37, Hanebutte discloses a system comprising: a first memory (fig. 1, HDD 190); and a second device (fig. 1, processor 110 and chipset 130) comprising: a cache (NV cache, [0021]) configured to store data; and circuitry configured to: maintain a plurality of entries comprising cache-management metadata, each corresponding to a respective region of contiguous data stored in the cache (data with contiguous addresses may be merged into a block of data. A mapping table may be created and stored in the non-volatile cache which includes multiple entries, each for a block of data, [0014]; metadata includes the disk LBA of the actual data block, the size of the data block in sectors, and the cache LBA of the actual data block, [0032]); store, for each such region, an address in a cache address space and a size defining a variable-length contiguous range of addresses in the cache (metadata includes the disk LBA of the actual data block, the size of the data block in sectors, and the cache LBA of the actual data block, [0032]); and
Hanebutte does not appear to explicitly disclose a first and second semiconductor chip configuration, a starting address, and update coherency data associated with the contiguous data during execution of an application.
However, Lee discloses a first and second semiconductor chip configuration (fig. 3, [0061]).
Furthermore, Segars discloses a starting address (address ranges for the logical regions are specified by a base address identifying which memory location the region starts at, and a size attribute identifying the size of the logical region, col. 3, lines 5-15).
Finally, Atkisson discloses update coherency data (the backing store interface module 722 manages cache coherency for the cache 102. For example, in various embodiments, the backing store interface module 722 may access a common directory with other users of the backing store 118 to maintain coherency…in a predefined coherency protocol, [0356]) associated with the contiguous data during execution of an application (user application 502 is a software application, [0212]).
Hanebutte, Lee, Segars, and Atkisson are analogous art because they are from the field of endeavor, cache storage.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanebutte, Lee, Segars, and Atkisson before him or her, to implement the storage system of Hanebutte according to the semiconductor chip architecture taught by Lee, the addressing of Segars, and the coherency protocol of Atkisson because semiconductor technology is an industry standard widely implement in the field of art before the effective filing date of the claimed invention, and providing advantages of mass production and circuitry footprint reduction, the comparators of Segars would provide granulized identification cached data, and the cache coherency of Atkisson would maintain cache coherence among a plurality of users and manage dirty cache data.
The suggestion/motivation to do so would have been to employ a circuitry architecture for electronics which benefit from a small size and advanced manufacturing (Lee: [0006-0007], [0129]), improve the efficiency of the cache data retrieval (Segars: col. 2, line 60 to col. 3, line 10)., and to maintain cache coherency (Atkisson: [0242], [0356]).
Therefore, it would have been obvious to combine Hanebutte, Lee, Segars, and Atkisson to obtain the invention as specified in the instant claim.
As to claim 38, the Hanebutte discloses in response to a change in size of the data, the circuitry is configured to change an indication of a size of the data stored in a corresponding entry of the plurality of entries (fig. 6, modify current table entry, [0035]).
As to claim 40, while Hanebutte discloses the cache corresponds to a level of the processor’s memory hierarchy (fig. 4 memory 475, HDD 485, NV cache 490, system RAM, and HDD 190; Chipset 130 may include one or more integrated circuit packages or chips, [0016]), Hanebutte does not appear to explicitly disclose memory hierarchy architecture is on-chip or on-package memory hierarchy.
However, Lee teaches an on-chip memory hierarchy (fig. 3, on-chip memories 215 and 213, [0061-0063]).
Hanebutte, Lee, Segars, and Atkisson are analogous art because they are from the field of endeavor, cache storage.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanebutte, lee, Segars, and Atkisson before him or her, to modify the storage system of Hanebutte to implement the chip architecture of Lee, because the configuration would provide reduced size, power consumption, and transmission time.
The suggestion/motivation to do so would have been to reduce the resource requirements and consumption (Lee: [0059-60]).
Therefore, it would have been obvious to combine Hanebutte, Lee, Segars, and Atkisson to obtain the invention as specified in the instant claim.
Claim 39 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hanebutte, Lee, Segars, and Atkisson, as applied to claims 37-38 and 40 above, further in view of Suzuki.
As to claim 39, Hanebutte discloses each of the plurality of entries further stores region-specific metadata at a granularity smaller than the variable-length contiguous range (During the caching process, data with contiguous addresses may be merged into a block of data, [0014]; Column 520 includes number of sectors (or size of blocks with LBAs on HDD shown in column 510), [0031]; contiguous data blocks and creates one entry in the mapping table for these larger data blocks, [0032]),
The combination of Hanebutte, Lee, Segars, and Atkisson does not appear to explicitly disclose the metadata comprising an offset for locating a target address within the region based on a difference between the target address and the starting address of the region..
However, Suzuki teaches an offset for locating a target address within the region based on a difference between the target address and the starting address of the region (calculates the PBA by finding an LBA relative address in the LBA group from the difference between the LBA and the start address of the corresponding LBA group, and then adding the start address of the PBA group to the LBA relative address; [0143]).
Hanebutte, Lee, Segars, Atkisson, and Suzuki are analogous art because they are from the field of endeavor, block storage.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hanebutte, Lee, Segars, Atkisson, and Suzuki before him or her, to modify the storage system of Hanebutte to implement the logical unit configuration as taught by Suzuki, because the logical storage configuration would extend the storage areas to a plurality of host systems.
The suggestion/motivation to do so would have been to provide representation of the RAID storage areas to a plurality of hosts (Suzuki: [0048]).
Therefore, it would have been obvious to combine Hanebutte, Lee, Segars, Atkisson, and Suzuki to obtain the invention as specified in the instant claim.
Response to Arguments
Applicant’s remarks filed 11/26/2025 have been fully considered, but are not persuasive.
With respect to independent claims 21, 27, and 37, regarding the teachings of Hanebutte, on pg. 9 of the response the Applicant asserts “the mapping table 500 of Hanebutte fails to disclose or suggest the recited "cache-management metadata, each corresponding to a respective region of contiguous data stored in the cache.”” The Examiner respectfully disagrees. Hanebutte teaches “data with contiguous addresses may be merged into a block of data. A mapping table may be created and stored in the non-volatile cache which includes multiple entries, each for a block of data” in paragraph [0014], and “metadata includes the disk LBA of the actual data block, the size of the data block in sectors, and the cache LBA of the actual data block” in paragraph [0032].
The Applicant’s remaining remarks on pg. 9-11 of the response with respect to the independent claims are directed to the prior art teachings of Atkisson, and are moot because the revised rejections of the independent claims, necessitated by the amendments, do not rely on the teachings of Atkisson.
The Applicant’s remarks on pg. 11-14 of the response, which are directed to the amended dependent claim 23, are moot in view of the new grounds of rejection.
The Applicant’s remarks on pg. 15-16 of the response with respect to the dependent claim 24 are directed to the prior art teachings of Atkisson, and are moot because the revised rejections of the claim, necessitated by the amendments, do not rely on the teachings of Atkisson.
With respect to dependent claim 26, regarding the teachings of Hanebutte, on pg. 9 of the response the Applicant asserts “the mapping table is not updated based on a detected overlap as recited” The Examiner respectfully disagrees; as referenced in the rejections above, Hanebutte considers the overlap, particularly see fig. 6 and paragraphs [0014], [0031-0036].
The Applicant’s remarks on pg. 17 of the response, which indicate they are to address the claimed subject matter of dependent claim 28, are moot because the remarks are directed to limitations regarding an “on-chip or on-package memory hierarchy” which are not limitations of dependent claim 28.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Pub. No. 2018/0336133 of Turner et al. is pertinent to cache modification and coherency.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC T OBERLY/ Primary Examiner, Art Unit 2184