DETAILED ACTION
The current Office Action is in response to the papers submitted 05/26/2026. Claims 1 – 7, 10 – 17, 20, and 23 - 26 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 – 7, 10 – 17, 20, and 23 - 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Leiseboer et al. (Pub. No.: US 2018/0307484) referred to as Leiseboer in view of Cardina et al. (Pub. No.: US 2012/0116902) referred to as Cardina in view of Murphrey et al. (Pub. No.: US 2002/0078396) referred to as Murphrey.
With regard to claim 1, Leiseboer teaches a method [6, Fig 6; Figs 10 – 12; The device 6 processing data according to the methods of figures 10 - 12] for processing data [Paragraphs 0051 – 0053; The reading and storing of data in the cache is processing data] stored in a memory [610, Fig 6], the method [Figs 10 – 12; The figures show the steps performs in the methods of the system] comprising:
activating a security mode [Figs 6 and 10 – 12; Paragraphs 0050 – 0053, 0061 – 0063, 0067 – 0072; A security mode is entered when a user sets parameters such as a time duration or the number of read-back operations. Setting such parameters is a function call or instruction that is executed before read-back operations are executed. The read-back operations are separate from the code setting the parameters]; and
in the activated security mode, automatically deleting, by a hardware component [620, Fig 6], the data stored in the memory [610, Fig 6; Paragraphs 0050 – 0053; The data in memory 610 is a result of read program code being executed], and otherwise, refraining from automatically deleting data [105 and 106, Fig 10; 115 and 116, Fig 11; 123, Fig 12; Paragraphs 0050 – 0053, 0061 – 0063, 0067 – 0072; The controller deletes data in the memory when the security mode is activated and data is not deleted when the security mode is not activated].
However, Leiseboer may not specifically disclose the limitation(s) of activating a security mode depending on a function call or instruction for program code designated for protection against side-channel attacks that exploit a physical implementation characteristics of a device and in the activated security mode, automatically deleting the data stored in the memory and associated with the execution of the designated program code.
Cardina discloses activating a security mode depending on a function call or instruction for program code designated for protection against attacks and in the activated security mode, automatically deleting the data stored in the memory and generated by the execution of the designated program code [Figs 2 – 3 and 5; Paragraphs 0041 – 0042, 0057, 0066; When program code that allows a user to use temporary account data is activated the system enters a security mode where time or uses of the temporary data is monitored and then the temporary data that was generated by program code is automatically erased to prevent attacks].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Cardina in Leiseboer, because it allows a system to enter a secure mode by allowing data to be accessed a threshold number of times or a threshold length of time thereby preventing attacks accessing the data after the threshold has been reached.
Murphrey discloses program code designated for protection against side-channel attacks that exploit physical implementation characteristics of a device [102, Fig 3; 116 and 118, Fig 4; A form of side-channel attack is data remanence, and the repeated overwriting erases the original data and prevents obtaining information related to the original data that was erased through the multiple overwrites. A memory device leaving a remanence of data that was previously deleted but not overwritten is a physical implementation characteristic of the memory device that can be exploited to obtain previously deleted data].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Murphrey, because the multiple overwrites in the erase operation ensures the original data remanence is not present at the end of the erase operation.
With regard to claim 2, Leiseboer teaches wherein the memory [610, Fig 6] comprises at least one register or a cache memory [610, Fig 6; Paragraphs 0051 – 0053; The memory is a volatile cache], and the data correspond to a value loadable into the memory [610, Fig 6; Paragraphs 0051 – 0053; The text stored in the cache is a value that is loaded from the VZ memory].
With regard to claim 3, Leiseboer teaches the data are deleted using of one constant, one random value, or one pseudorandom value [Paragraphs 0050, 0053, 0056, 0061, and 0063; The cache is erased using a secure erase operation which overwrites data with other data. The erase operation is also defined as including writing static ones or static zeros or random data. Data that is stored is also constant while it is stored].
With regard to claim 4, Leiseboer teaches previous data are deleted before the designated program performs an operation on the data stored in the memory [Figs 10 - 12; Two or more consecutive iterations of the processes will delete data from a previous iteration in the last step before operations in the current iteration are performed].
With regard to claim 5, Leiseboer teaches the memory [610, Fig 6] comprises a register, a memory not accessible or not visible from outside in relation to a processor, a memory accessible or visible from outside in relation to a processor, a RAM [Paragraph 0051; The cache being SRAM is a type of RAM], a non-volatile memory [610, Fig 6; Paragraph 0053; The cache is volatile], or a cache memory [610, Fig 6; The memory is cache].
With regard to claim 6, Leiseboer teaches the method [Figs 10 – 12; The figures show the steps performs in the methods of the system] is carried out on a processor [620, Fig 6; The controller acts as a processor since it executes the secure deletion of data in cache], a CPU, a controller [620, Fig 6; Paragraphs 0051 – 0053; The controller controls carries out the methods used to control data access], an arithmetic logic unit (ALU), a cache memory [610, Fig 6; Paragraphs 0051 – 0053; The methods are performed on the cache memory since the method involves read and writing data to and from the cache], a security module [6, Fig 6; The entire device is a security device since it is used to provide secure access to data], a crypto unit [406, Fig 5], or a coprocessor .
With regard to claim 7, Leiseboer teaches wherein the deletion is initiated and/or performed by a hardware component [620, Fig 6; Paragraphs 0051 – 0053; The controller controls the secure erase in cache].
With regard to claim 10, Leiseboer teaches the security mode is activatable or deactivatable depending on a switch, a register, a configuration register, a crypto unit, an input/output unit, a processor, a CPU, a controller [620, Fig 6; Paragraphs 0050 - 0053, 0061 - 0063, 0067 - 0072; The erasing is controlled and activated by the controller and a threshold], an arithmetic logic unit (ALU), a cache memory, a security module [620 or 630, Fig 6; Paragraphs 0050 - 0053, 0061 - 0063, 0067 - 0072; The event detector and/or controller is a security module since both are devices that are used in the process of securing data by erasing the data or synching the data in a cache], or a coprocessor.
With regard to claim 11, Leiseboer teaches the security mode has a plurality of deletion stages [Paragraphs 0050 – 0053; The erase including writing multiple zeros or ones shows multiple bits being written in the erase operation and each bit that is erased with a one or zero is considered a deletion stage].
With regard to claim 12, Leiseboer teaches the deletion is performed after each operation, provided that the security mode is activated [Paragraphs 0051 – 0053; Each time there is a read of cached data that surpasses the limited multiple read limit the data in the cache is deleted].
With regard to claim 13, Leiseboer teaches the deletion is performed after at least one cycle duration of a clock signal [Paragraph 0053; The deletion being based on a number of reads indicates there is a number of clock cycles that occur between the time the data was written and cycles required to perform the read and also detect that the read limit was reached since operations in a computer are regulated by clock cycles] and/or after a predefined time duration [Paragraph 0053; The deletion can be time based].
With regard to claim 14, Leiseboer teaches the data have previously been read from a further memory [4’, Fig 6] and loaded into the memory [610, Fig 6; Paragraphs 0051 – 0053; Data stored in VZ memory is read into the cache].
Claim 15 is a device corresponding to claim 1 and is thus rejected using the same prior art and similar reasoning. Leisboer teaches a device [Figs 1 and 6], Cardina discloses a device [Figs 5 – 7], and Murphrey discloses a device [Fig 1].
With regard to claim 16, Leiseboer teaches the device [6, Fig 6] comprises a processor [620, Fig 6; The controller acts as a processor since it executes the secure deletion of data in cache] or a microcontroller [620, Fig 6; The cache controller is also a microcontroller of the cache].
Claim 17 is a device corresponding to claim 5 and is thus rejected using the same prior art and similar reasoning.
Claim 20 is a device corresponding to claim 4 and is thus rejected using the same prior art and similar reasoning.
With regard to claim 23, Leiseboer discloses wherein the security-optimized mode is activatable or deactivatable depending on a jump to an exception routine, a return from an exception routine, a call of a function, a return from a function, a crypto unit that is used, an instruction or a set of instructions [Figs 10 – 12; Paragraphs 0050 - 0053, 0061 - 0063, 0067 – 0072; The security mode is activated or deactivated based on the read instruction and the instruction(s) defining the security process of erasing data based on time or number of reads], a position of a program pointer, or a position of a stack pointer.
Claim 24 is a device corresponding to claim 23 and is thus rejected using the same prior art and similar reasoning.
Regarding claim 25, Leiseboer teaches the data generated by the execution of the designated program code comprises intermediate values [122, Fig 12; Paragraphs 0067 and 0072; The unsecure or plain text data in the cache is intermediate values of data that are eventually changed to encrypted versions of the data], operands, or results [Figs 6, 8A – 8B, and 9; All the data stored in the cache is a result of an operation storing data into the cache], and wherein the memory [610, Fig 6] comprises at least one register or cache memory [610, Fig 6; The memory is cache which is also considered a register].
Regarding claim 26, Leiseboer teaches the data generated by the execution of the designated program code comprises intermediate values [122, Fig 12; Paragraphs 0067 and 0072; The unsecure or plain text data in the cache is intermediate values of data that are eventually changed to encrypted versions of the data], operands, or results [Figs 6, 8A – 8B, and 9; All the data stored in the cache is a result of an operation storing data into the cache], and wherein the memory [610, Fig 6] comprises at least one register or cache memory [610, Fig 6; The memory is cache which is also considered a register].
Response to Arguments
Applicant's arguments filed 05/26/2026 have been fully considered but they are not persuasive.
The applicant argues on page 7 that claim 1 is allowed since Leiseboer fails to teach a function call or instruction for program code designated for protection against side-channel attacks, the deleted data is not generated by execution of program code such as intermediate values, operands, or results, and there is no concept of a security mode protecting against side-channel attacks. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
Leiseboer is used to teach a general security mode that limits how long or how many times data can be read. Setting the limit and then limiting access to data, based on the limit, is a security mode. Leiseboer is not used to teach anything related to a side-channel attack as argued. Murphrey is used in the rejections to teach protection against side-channel attacks. There is no limitation in claim 1 that the generated data that is deleted in intermediate values, operands, or results as argued. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the deletions of generated data that is intermediate values, operands, or results.) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The applicant argues on page 7 that claim 1 is allowed since Cardina fails to teach a function call or instruction for program code designated for protection against side-channel attacks that exploit physical implementation characteristics of a device and deleting intermediate values, operands, or results from processor registers or cache memory. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
Cardinia is not used to teach anything related to a side-channel attacks. Murphrey is used in the rejections to teach protection against side-channel attacks. There is no limitation in claim 1 of deleting intermediate values, operands, or results from processor registers or cache memory as argued. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., deleting intermediate values, operands, or results from processor registers or cache memory) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The applicant argues on page 8 that claim 1 is allowed since the protection against data remanence taught by Murphey is not a side-channel attack that exploits physical implementation characteristic of the device such a exploiting physical characteristics during program execution based on paragraph 0002 of the specification. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
There are no bounds on what is considered a side-channel attack in the claims other then the attack exploits physical implementation characteristics of a device. There is no indication what physical implementation characteristics of the device are exploited in the side-channel attack. Paragraph 0002 of the specification provides a non-limiting list of examples of types of side-channel attacks. If a specific type of side-channel attack is meant in the claims, then the specific side-channel attack should be listed in the claim. The remanence of data in memory is a physical implementation characteristic of the memory. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., power consumption of a device can be proportional to the processed data or observing physical characteristics during program execution to infer secret data) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The applicant argues on page 8 that claims 25 and 26 introduce new limitation that are not taught by the prior art. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
The arguments fail to properly explain how the claim limitations are not taught by the prior art other than saying they do not. There are no specific examples or explanation detailing how the prior art is different from the current claim limitations. Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. The rejections contain citations and explanations detailing how the prior art teaches the current claim limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/ Primary Examiner, Art Unit 2138
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