Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed 04/14/2026 has been entered. Claims 1-23 remain pending in the application.
Claim Interpretation
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are: “an activation unit for performing activation operations on the first operation result” and “a pooling unit for performing pooling operations on the first operation result output from the fourth register region”. in claims 4-5.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. See PGPUB ¶35-36 where algorithms of the units are discussed (RELU and MAX-Pooling) tied to an accelerator.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-19 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Dally et al. (US 20180046900 A1 hereinafter Dally) in view of Baum et al. (US 20180285719 A1 hereinafter Baum)
As to independent claim 1, Dally teaches an AI operation accelerator adapted to perform operations on an input data in a memory unit, the memory unit including a first data storage region for storing the input data, a second data storage region for storing a descriptor which includes a weight data, and a third data storage region for storing an output data, the AI operation accelerator including: [SCNN accelerator with buffers (memory/registers) with input data, weights and outputs Fig. 2b-c 230, 235, 240 ¶51, ¶60 "dataflow relies on input buffers, weight buffer 230 and input activations buffer 235, for storing weights and input activations"]
a first register region for registering a part of the input data, wherein the first register region is configured a predetermined data length; [buffer for input data may be registers ¶87"input activations buffer 310 and buffer 320 may be a set of registers or SRAM that are configured to store the input activations and the positions associated with each input activation value"], [amount of input is compressed into a format with fixed number ¶113, 120]
a second register region for registering a first part of the descriptor; [compressed-sparse format (descriptor) and buffers ¶74, ¶120 "weights are encoded in a compressed-sparse format "]
a third register region for registering a first part of the weight data; [FIFO weight buffer 305 with a storage capacity ¶83-84 ]
a first operator for operating the first part of the input data and the first part of the weight data to generate a first operation result; [Fig. 3A 325 multipliers on input data and weight ¶72 "processing a vector of F non-zero filter weights a vector of I non-zero input activations in within the F×I multiplier array 325"]
a fourth register region for registering the first operation result; [Fig. 3A 340 array includes results and buffers ¶73 "accumulator array 340 may include one or more accumulation buffers and adders to store the products generated in the multiplier array 325 and sum the products into the partial sums"]
a fifth register region for registering a second part of the weight data; and [buffer with sequencer and pointers for selecting different weights ¶86 " weight buffer 305 is a FIFO buffer that includes a tail pointer, a channel pointer, and a head pointer. The layer sequencer 215 controls the “input” side of the weight buffer 305, pushing weight vectors into the weight buffer 305"]
a second operator for operating the first operation result and the second part of the weight data to generate a second operation result, [output (result) fed into next layer to generate another result ¶36, ¶83 " output activation volume of a neural network layer can serve as the input activation volume for the next neural network layer, then the output activations buffer 350 is logically swapped with the input activations buffer 310 between processing of the different neural network layers"]
Dally does not specifically teach wherein when a predetermined data amount is stored in the fourth register region, the second operator is triggered to operate the first operation result and the second part of the weight data.
However, Baum teaches wherein when a predetermined data amount is stored in the fourth register region, the second operator is triggered to operate the first operation result and the second part of the weight data. [One ANN layer completes and sends results to another (handover) and can be triggered by external signals when complete (amount stored) ¶216-217 " a trigger can be issued to trigger activity in an LCU in a different LC. This process is termed a ‘handover’. The handover mechanism can trigger activity from one LC to another, e.g., a trigger can be used when one ANN layer completes and sends results to another layer in the ANN"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the accelerator disclosed by Dally by incorporating the wherein when a predetermined data amount is stored in the fourth register region, the second operator is triggered to operate the first operation result and the second part of the weight data disclosed by Baum because both techniques address the same field of machine learning and by incorporating Baum into Dally meets needed capabilities, capacity resulting in more efficient neural networks [Baum ¶17].
As to dependent claim 2, the rejection of claim 1 is incorporated, Dally and Baum further teach wherein when the second operator is triggered to be in operation, the first operator continues in operating the input data. [Dally double buffering allows keep storing new results while another set is processed by PEs ¶82 " double-buffered so that one set of registers can store new partial sums while the second set of registers are drained out by the post-processing unit 345"]
As to dependent claim 3, the rejection of claim 1 is incorporated, Dally and Baum further teach wherein the predetermined data amount is configured based on a batch width and a filter parameter. [Dally batch length and filter weights ¶55 "batch of length N of groups of C channels of input activation planes can be applied to the same volume of filter weights."]
As to dependent claim 4, the rejection of claim 1 is incorporated, Dally and Baum further teach an activation unit for performing activation operations on the first operation result. [Dally activation operations are processed by a destination calculation unit ¶82]
As to dependent claim 5, the rejection of claim 1 is incorporated, Dally and Baum further teach a pooling unit for performing pooling operations on the first operation result output from the fourth register region. [Dally post processing unit for pooling ¶82]
As to dependent claim 6, the rejection of claim 1 is incorporated, Dally and Baum further teach wherein the first operator further includes a first operation element array having a plurality of first operation elements, and [Dally multiplier array Fig. 3A 325 ¶82]
each of the first operation elements is configured to: receive the input data and the first part of the weight data corresponding to multi-dimensional positions; and process the input data and the first part of the weight data to generate a plurality of operation results as the first operation result. [Dally array 325 computes products using weights and inputs ¶81-82]
As to dependent claim 7, the rejection of claim 6 is incorporated, Dally and Baum further teach wherein the second operator further includes a second operation element array having a plurality of second operation elements; and [Dally Each processing element (PE) includes a multiplier array fed from another PE Fig. 2A 210, Fig. 2C 240 ¶66]
each of the second operation elements is configured to: receive the first operation result and the second part of the weight data; and [Dally results get fed into next PE ¶83]
process the first operation result and the second part of the weight data to generate a plurality of operation results as the second operation result. [Dally output (result) fed into next layer to generate another result ¶36, ¶83 " output activation volume of a neural network layer can serve as the input activation volume for the next neural network layer, then the output activations buffer 350 is logically swapped with the input activations buffer 310 between processing of the different neural network layers"]
As to dependent claim 8, the rejection of claim 1 is incorporated, Dally and Baum further teach wherein the first operator has a first maximum operation capacity, the second operator has a second maximum operation capacity smaller than the first maximum operation capacity. [Dally 16 operations capacity and a 1 operation per cycle capacity ¶105 " a post-processing unit 345 performing one operation per cycle should keep pace with a F×I multiplier array 325 that performs 16 operations per cycle"]
As to dependent claim 10, the rejection of claim 7 is incorporated, Dally and Baum further teach wherein a number of the first operation elements is larger than a number of the second operation elements. [Dally 16 operations capacity vs a 1 operation per cycle capacity ¶105 " a post-processing unit 345 performing one operation per cycle should keep pace with a F×I multiplier array 325 that performs 16 operations per cycle"]
As to independent claim 11, Dally teaches a method of accelerating AI operation, comprising: [SCNN accelerator with buffers (memory/registers) with input data, weights and outputs Fig. 2b-c 230, 235, 240 ¶51, ¶60 "dataflow relies on input buffers, weight buffer 230 and input activations buffer 235, for storing weights and input activations"]
A. reading an input data and a descriptor from a memory unit, wherein the descriptor includes a weight data; [memory ¶45, compressed-sparse format (descriptor) and buffers ¶74, ¶120 "weights are encoded in a compressed-sparse format "]
B. performing a first part of the input data and a first part of the weight data by a first operator for generating a first operation result; [Fig. 3A 325 multipliers on input data and weight ¶72 "processing a vector of F non-zero filter weights a vector of I non-zero input activations in within the F×I multiplier array 325"]
C. registering the first operation result; [buffer with sequencer and pointers for selecting different weights ¶86 " weight buffer 305 is a FIFO buffer that includes a tail pointer, a channel pointer, and a head pointer. The layer sequencer 215 controls the “input” side of the weight buffer 305, pushing weight vectors into the weight buffer 305"]
E. writing the second operation result into the memory unit. [Writes output and activations ¶45-46 " write weight and/or activation data from the SCNN 200 to the memory"]
Dally does not specifically teach D. in response to the first operation result reaching a predetermined data amount, triggering a second operator to perform the first operation result and a second part of the weight data by the second operator for generating a second operation result.
However, Baum teaches D. in response to the first operation result reaching a predetermined data amount, triggering a second operator to perform the first operation result and a second part of the weight data by the second operator for generating a second operation result.
[One ANN layer completes and sends results to another (handover) and can be triggered by external signals when complete (amount stored) ¶216-217 " a trigger can be issued to trigger activity in an LCU in a different LC. This process is termed a ‘handover’. The handover mechanism can trigger activity from one LC to another, e.g., a trigger can be used when one ANN layer completes and sends results to another layer in the ANN"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the accelerator disclosed by Dally by incorporating the D. in response to the first operation result reaching a predetermined data amount, triggering a second operator to perform the first operation result and a second part of the weight data by the second operator for generating a second operation result disclosed by Baum because both techniques address the same field of machine learning and by incorporating Baum into Dally meets needed capabilities, capacity resulting in more efficient neural networks [Baum ¶17].
As to dependent claim 12, the rejection of claim 11 is incorporated, Dally and Baum further teach wherein in the step D, when the second operator performs the second operation, the first operator and the second operator are in parallel processing state. [Dally parallel processing PEs ¶44]
As to dependent claim 13, the rejection of claim 11 is incorporated, Dally and Baum further teach A01. reading the first part of the input data from the memory unit into a first register region; [Dally buffer for input data may be registers ¶87"input activations buffer 310 and buffer 320 may be a set of registers or SRAM that are configured to store the input activations and the positions associated with each input activation value"], [amount of input is compressed into a format with fixed number ¶113, 120]
A03. reading a first part of the descriptor from the memory unit into a second register region; and [Dally compressed-sparse format (descriptor) and buffers ¶74, ¶120 "weights are encoded in a compressed-sparse format "]
A05. reading the first part of the weight data from the memory unit into a third register region. [Dally read weights from memory ¶45 into multiple Pes with buffers Fig. 2A 204-210, Fig. 2C 230 ¶60]
As to dependent claim 14, the rejection of claim 13 is incorporated, Dally and Baum further teach wherein the step C further includes storing the first operation result of the first operator into a fourth register region. [Dally Fig. 3A 340 array includes results and buffers ¶73 "accumulator array 340 may include one or more accumulation buffers and adders to store the products generated in the multiplier array 325 and sum the products into the partial sums"]
As to dependent claim 15, the rejection of claim 14 is incorporated, Dally and Baum further teach A07. reading a second part of the weight data from the memory unit into a fifth register region. [Dally read weights from memory ¶45 into multiple Pes with buffers Fig. 2A 204-210, Fig. 2C 230 ¶60]
As to dependent claim 16, the rejection of claim 15 is incorporated, Dally and Baum further teach F. determining whether all the input data in the first register memory are read out and operated, when the step F is no, loading a next batch of the input data from the first register region, and when the step F is yes, the method proceeds to step G; [Dally batch processing and channels ¶55 sequencing ¶79]
G. determining whether all data in the fourth register region is processed, when the step G is no, a data address parameter is updated, and when the step G is yes, the method proceeds to step H; and [Dally outputs of operations are a updated address (linear address) ¶96]
H. determining whether any input data in the first register region is not read out yet, when the step H is no, the method ends, [Dally counts outputs to test if data is in register ¶188]
wherein the predetermined data amount is configured based on a batch width and a filter parameter. [Dally batch length and filter weights ¶55 "batch of length N of groups of C channels of input activation planes can be applied to the same volume of filter weights."]
As to dependent claim 17, the rejection of claim 11 is incorporated, Dally and Baum further teach I. determining whether all data in the fourth register region are operated by the second operation, when the step I is no, data in the fourth register region is read out for performing the second operation, and when the step I is yes, a data address is updated and the method ends. [Dally counters and end conditions (all data operated) with pointers ¶87-88]
As to dependent claim 18, the rejection of claim 17 is incorporated, Dally and Baum further teach performing activation operations on the first operation result. [Dally activations like relu ¶82]
As to dependent claim 19, the rejection of claim 17 is incorporated, Dally and Baum further teach performing pooling operations on the first operation result. [Dally pooling ¶82]
As to independent claim 21, Dally teaches A computing system including:
a memory unit [sram ¶87] including a first data storage region for storing an input data, a second data storage region for storing a descriptor which includes a weight data, and a third data storage region for storing an output data; [compressed-sparse format (descriptor) and buffers ¶74, ¶120 "weights are encoded in a compressed-sparse format "]
a memory read-write controller coupled to the memory unit, for controlling read and write of the memory unit; and [read/write interface ¶45-46 " memory interface 205 reads weight and activation data from a memory coupled to the SCNN"]
an AI operation accelerator coupled to the memory read-write controller, the AI operation accelerator including: [SCNN accelerator with buffers (memory/registers) with input data, weights and outputs Fig. 2b-c 230, 235, 240 ¶51, ¶60 "dataflow relies on input buffers, weight buffer 230 and input activations buffer 235, for storing weights and input activations"]
a first register region for registering a part of the input data, wherein the first register region is configured a predetermined data length; [buffer for input data may be registers ¶87"input activations buffer 310 and buffer 320 may be a set of registers or SRAM that are configured to store the input activations and the positions associated with each input activation value"], [amount of input is compressed into a format with fixed number ¶113, 120]
a second register region for registering a first part of the descriptor; [compressed-sparse format (descriptor) and buffers ¶74, ¶120 "weights are encoded in a compressed-sparse format "]
a third register region for registering a first part of the weight data; [FIFO weight buffer 305 with a storage capacity ¶83-84 ]
a first operator for operating the first part of the input data and the first part of the weight data to generate a first operation result; [Fig. 3A 325 multipliers on input data and weight ¶72 "processing a vector of F non-zero filter weights a vector of I non-zero input activations in within the F×I multiplier array 325"]
a fourth register region for registering the first operation result; [Fig. 3A 340 array includes results and buffers ¶73 "accumulator array 340 may include one or more accumulation buffers and adders to store the products generated in the multiplier array 325 and sum the products into the partial sums"]
a fifth register region for registering a second part of the weight data; and [buffer with sequencer and pointers for selecting different weights ¶86 " weight buffer 305 is a FIFO buffer that includes a tail pointer, a channel pointer, and a head pointer. The layer sequencer 215 controls the “input” side of the weight buffer 305, pushing weight vectors into the weight buffer 305"]
a second operator for operating the first operation result and the second part of the weight data to generate a second operation result, [output (result) fed into next layer to generate another result ¶36, ¶83 " output activation volume of a neural network layer can serve as the input activation volume for the next neural network layer, then the output activations buffer 350 is logically swapped with the input activations buffer 310 between processing of the different neural network layers"]
Dally does not specifically teach wherein when a predetermined data amount is stored in the fourth register region, the second operator is triggered to operate the first operation result and the second part of the weight data.
However, Baum teaches wherein when a predetermined data amount is stored in the fourth register region, the second operator is triggered to operate the first operation result and the second part of the weight data. [One ANN layer completes and sends results to another (handover) and can be triggered by external signals when complete (amount stored) ¶216-217 " a trigger can be issued to trigger activity in an LCU in a different LC. This process is termed a ‘handover’. The handover mechanism can trigger activity from one LC to another, e.g., a trigger can be used when one ANN layer completes and sends results to another layer in the ANN"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the accelerator disclosed by Dally by incorporating the wherein when a predetermined data amount is stored in the fourth register region, the second operator is triggered to operate the first operation result and the second part of the weight data disclosed by Baum because both techniques address the same field of machine learning and by incorporating Baum into Dally meets needed capabilities, capacity resulting in more efficient neural networks [Baum ¶17].
As to dependent claim 22, the rejection of claim 21 is incorporated, Dally and Baum further teach wherein when the second operator is triggered to be in operation, the first operator continues in operating the input data. [Dally double buffering allows keep storing new results while another set is processed by PEs ¶82 " double-buffered so that one set of registers can store new partial sums while the second set of registers are drained out by the post-processing unit 345"]
As to independent claim 23, Dally teaches a non-transitory computer readable media storing a program code readable and executable by a computer, when the program code is executed by the computer, the computer performing steps of: [computer programs and computer readable media ¶212-213]
A. reading an input data and a descriptor from a memory unit, wherein the descriptor includes a weight data; [memory ¶45, compressed-sparse format (descriptor) and buffers ¶74, ¶120 "weights are encoded in a compressed-sparse format "]
B. performing a first part of the input data and a first part of the weight data by a first operator for generating a first operation result; [Fig. 3A 325 multipliers on input data and weight ¶72 "processing a vector of F non-zero filter weights a vector of I non-zero input activations in within the F×I multiplier array 325"]
C. registering the first operation result; [buffer with sequencer and pointers for selecting different weights ¶86 " weight buffer 305 is a FIFO buffer that includes a tail pointer, a channel pointer, and a head pointer. The layer sequencer 215 controls the “input” side of the weight buffer 305, pushing weight vectors into the weight buffer 305"]
E. writing the second operation result into the memory unit. [Writes output and activations ¶45-46 " write weight and/or activation data from the SCNN 200 to the memory"]
Dally does not specifically teach wherein when a predetermined data amount is stored in the fourth register region, the second operator is triggered to operate the first operation result and the second part of the weight data.
However, Baum teaches wherein when a predetermined data amount is stored in the fourth register region, the second operator is triggered to operate the first operation result and the second part of the weight data. [One ANN layer completes and sends results to another (handover) and can be triggered by external signals when complete (amount stored) ¶216-217 " a trigger can be issued to trigger activity in an LCU in a different LC. This process is termed a ‘handover’. The handover mechanism can trigger activity from one LC to another, e.g., a trigger can be used when one ANN layer completes and sends results to another layer in the ANN"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the accelerator disclosed by Dally by incorporating the wherein when a predetermined data amount is stored in the fourth register region, the second operator is triggered to operate the first operation result and the second part of the weight data disclosed by Baum because both techniques address the same field of machine learning and by incorporating Baum into Dally meets needed capabilities, capacity resulting in more efficient neural networks [Baum ¶17].
Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Dally and Baum as applied in the rejection of claim 1 and 13 above, and further in view of Du et al. (US 10162799 B2 hereinafter Du)
As to dependent claim 9, Dally and Baum teach the method of claim 1 above that is incorporated,
Dally and Baum do not specifically teach wherein a capacity of the fourth register region is configured at least triple times of the predetermined data length of the first register region.
However, Du teaches wherein a capacity of the fourth register region is configured at least triple times of the predetermined data length of the first register region. [buffer is 3 items wide for remap (triple) Col. 2 ln. 26-36 "each stride between the convolution operations is 1, and each set of the remap data includes 3 remap data. The convolution operation is a 3×3 convolution operation, and the input buffer unit is configured to buffer the latest 2 inputted data and output the latest 2 inputted data in the later clock"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the memories described by Dally and Baum by incorporating the wherein a capacity of the fourth register region is configured at least triple times of the predetermined data length of the first register region disclosed by Du because all techniques address the same field of system design and by incorporating Du into Dally and Baum provide better buffer devices that can improve the performance of the convolution operation and capable of processing data streams [Du Col. 1 ln. 47-57]
As to dependent claim 20, Dally and Baum teach the method of claim 1 above that is incorporated,
Dally and Baum do not specifically teach wherein the first register region is configured a predetermined data length, and a capacity of the fourth register region is configured at least triple times of the predetermined data length.
However, Du teaches wherein the first register region is configured a predetermined data length, and a capacity of the fourth register region is configured at least triple times of the predetermined data length. [buffer is 3 items wide for remap (triple) Col. 2 ln. 26-36 "each stride between the convolution operations is 1, and each set of the remap data includes 3 remap data. The convolution operation is a 3×3 convolution operation, and the input buffer unit is configured to buffer the latest 2 inputted data and output the latest 2 inputted data in the later clock"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the memories described by Dally and Baum by incorporating the wherein the first register region is configured a predetermined data length, and a capacity of the fourth register region is configured at least triple times of the predetermined data length disclosed by Du because all techniques address the same field of system design and by incorporating Du into Dally and Baum provide better buffer devices that can improve the performance of the convolution operation and capable of processing data streams [Du Col. 1 ln. 47-57]
Response to Arguments
Applicant's arguments filed 04/14/2026, with respect to 101 and Ramirez, those rejections have been withdrawn.
Applicant's arguments filed 04/14/2026, with respect to Dally, Dally's architecture (as shown in the pseudocode of Table 4) is based on loop (for-loops) sequential or tiling processing. In Dally, normally the next step is performed only after completing an entire tile or an entire layer. Such modification would not be a simple substitution, but would fundamentally alter the operation principle of Dally, thereby teaching away from the proposed combination. Accordingly, after analysis: Dally's design is based on fixed data-block processing, and does not suggest or teach that the second operator can be dynamically triggered by "monitoring the fill level of intermediate results." If Ramirez's threshold-triggering mechanism were forcibly added to Dally, it would destroy Dally's original layer-switching logic.
As to point (1) applicant’s arguments with respect to claim 1 have been considered but are moot in view of a new ground of rejection made under rejected under 35 U.S.C. 103 as being unpatentable over Dally view of Baum as set forth above. Further to point (1), Dally already has double buffering and output buffers and needs not create the “data hazard” applicant alleges (see ¶78, ¶82, ¶95). Baum uses “complete” but also see reference below about predetermined data amount as three rows.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
(US 20190080231 A1) teaches three input rows buffered before a layer begins processing (see ¶60)
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Beau Spratt whose telephone number is 571 272 9919. The examiner can normally be reached 8:30am to 5:00pm (PST).
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/BEAU D SPRATT/Primary Examiner, Art Unit 2143
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