DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responsive to amendment filed on 01/16/2026. Claims 1-20 are pending. The amendment have overcome the claims objection, rejection under 35 U.S.C. 101 and some of rejections under 35 U.S.C. 102 and 103 as set forth in previous office action.
Response to Amendment
Applicant’s arguments, see Remarks page 8, filed on 01/16/2026, with respect to claim 1 have been fully considered and are persuasive since claim 1 recites additional elements that integrate the judicial exception into a practical application under step 2A prong two, as claim 1 recites a neural engine circuit including a plurality of operations circuits operating in parallel, an accumulator circuit coupled to the plurality of operation circuits, a key mask register, a masking circuit coupled to the accumulator circuit, and the first record is stored into a record store of the accumulator circuit and provided to the comparator circuit as feedback information to be compared with the second record by the comparator, which implement a judicial exception using a particular machine. Furthermore claims 10 and 19 recites similar limitations, where each of a plurality of operation circuits includes a comparator circuit and the first cord is stored into the record store and provided to the comparator circuit as feedback information to be compared ith the second record, such additional elements integrate the judicial exception into a practical application under step 2A prong two because it provides an improvement in the functioning of a computer or an improvement to other technology by having a feedback loop to reuse the same comparator circuit to perform the comparation, rather than having a plurality of comparator circuits cascaded to perform the operation. Accordingly, rejection under 35 U.S.C. 101 are withdrawn.
In response to applicant’s argument regarding rejection under 35 U.S.C. 103, “During the Interview, the Examiner agreed that the above amended features are not taught by Mohapatra. In addition, Gao, Cohen, and Dally do not cure the deficiencies of Mohapatra. Accordingly, amended claim 1 is allowable over the combination of Mohapatra, Gao, Cohen, and Dally. In addition, independent claims 10 and 19 recite similar features as claim 1 and are allowable for at least the same reasons as for claim 1. Further, dependent claims 2-9, 11-18, and 20 are allowable for being dependent from an allowable base claim in addition to their own allowable features. Applicant respectfully requests that the rejections under 35 U.S.C. § 102 and 35 U.S.C. § 103 of claims 1-20 be reconsidered and withdrawn, and that these claims be passed to allowance.”
Examiner respectfully disagrees because while Examiner agreed during the interview on 11/04/2025 that the limitations reciting mask register storing key mask or having a mask circuit to mask non-key field would overcome the 102 rejection as recited in claim 1. However, claims 10 and 19 do not recite such limitations. Accordingly, claims 10 and 19 are still rejected.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 line 13 recites “the records”. It is unclear whether the records is referring to the first and second seconds or the plurality of records as antecedently recited. For examination purposes, Examiner interprets such limitations as the plurality of records.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10 and 15-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mohapatra - US 20200134417.
Regarding claim 10, Mohapatra teaches a method operating a neural engine circuit (Mohapatra figure 1 illustrates an array of processing elements 105 for implementing neural network [i.e., a neural engine circuit]), comprising:
comparing, by a comparator circuit of each of a plurality of operation circuits operating in parallel, a field of a first record of a plurality of records and a corresponding field of a second record of the plurality of records to generate a comparison result on values in the field and the corresponding field (Mohapatra figure 1 illustrates a plurality of processing elements 105 operating in parallel [i.e., a plurality of operation circuits]. Figure 6 [0056] illustrates implementation of each processing element, wherein based on the mode of operation, such as maxpool operation [0058-0059], which configured to compare data from IFMAP 145a having at least 8 bit precision, thus each bit of IFMAP corresponds to a corresponding field of a second record and data from a pooler register 165 having at least 8 bit, thus each bit of data from pooler register corresponds to a field of a first record, the comparator circuit 620 to generate a maximum value [i.e., a comparison result], thus the data used in comparison operation across the processing elements correspond to a plurality of records), wherein the first record or the second record comprises a plurality of fields including the field as a key field for comparison (Mohapatra [0059] describes IF data 145a [i.e., the second record] is 8 bit wide corresponds to a plurality of field including the field as a key field for comparison as comparison is performed on the bits, which are also considered as key field);
storing, at a record store of an accumulator circuit coupled to the plurality of operation circuits, the plurality of records including the first record, wherein the first record is stored into the record store and provided to the comparator circuit as feedback information to be compared with the second record (Mohapatra figure 6 illustrates each PE includes register file storage 145a-145c and pooler register 165. Thus, the registers in the PEs correspond to [i.e., an accumulator circuit], which coupled to the PEs. Therefore, data IFMAP and data from pooler register of the PEs [i.e., the plurality of record] are stored in IFMAP 145a and pool register 165 [i.e., a record store], including data in pooler register [i.e., the first record] that is provided to the comparator 620 as a feedback information (see figure 6 illustrates output of comparator is sent to pooler register and is feedback to the comparator) to be compared with the IFMAP [i.e., the second record]); and
storing, at a sideband register of the accumulator circuit, a plurality of comparison results generated by the plurality of operation circuits (Mohapatra figure 6 illustrates register OFMAP 145c [i.e., a sideband register] to store result performed by the comparator 620. Thus, the register 145c of the PEs store a plurality of comparison results generated by the PEs).
Regarding claim 15, Mohapatra teaches the method of claim 10, wherein the field and the corresponding field have a same index in the first record and the second record (Mohapatra figure 6 illustrates comparator performs comparison of data from register 145a and pooler register 165 to determine current max value, and [0059] describes each data is at least 8 bit precision. Thus, each data include a data field having the same index value to perform the comparing correctly).
Regarding claim 16, Mohapatra teaches the method of claim 10, wherein the comparison result is a lexicographical comparison result (Mohapatra [0068] describes the input tensor data are 8-bit precision; thus, the comparator is performed comparing of at least two 8-bit data to determine the maximum value, and multi-bit comparison is performed by comparing each element or bit until a different is found between the two data to determine the max or larger data. Thus, such comparison result between two 8 bit is lexicographical because the 8-bit data are being compared with each other and first differing bit decides if the data is larger or not).
Regarding claim 17, Mohapatra further teaches the method of claim 10, wherein the first record is received during a first operation cycle and the second record is received during a second operation cycle subsequent to the first operation cycle (Mohapatra [0070] figure 6 describes the comparator performs maxpooling operation that compares data from the IF register 145a and the current maximum value in pooler register 165. Thus, initially, comparator 620 receives a first data from register 145a [i.e., the first record during a first operation cycle], which is stored in pooler register 165 as current max value, then a second data is received in second cycle subsequent to the first cycle, which is compared with the data stored in pooler register 165).
Regarding claim 18, Mohapatra further teaches the method of claim 10, wherein each of the plurality of operation circuits comprises a multiplier circuit, an adder circuit, and the comparator circuit, wherein the comparator circuit is configured to determine the comparison result, and wherein the comparator circuit is coupled to the accumulator circuit (Mohapatra figure 6 illustrates each of the plurality of PEs incudes multiplier 610, adder 615, and comparator 620, wherein the comparator 620 determine the comparison result, and the comparator 620 coupled to the register file 145a-c and pooler register 165)
Claim 19 recites apparatus claim having similar limitation as method claim 10. Thus, it is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Mohapatra in view of Gao - US 20220230069 and Cohen - US 20190004997.
Regarding claim 11, Mohapatra teaches the method of claim 10, but does not teach storing, at a key mask register of the accumulator circuit, indices indicating a plurality of key fields and a plurality of non-key fields for generating a masked plurality of comparison results. Gao discloses a masking matrix having indices indicating a plurality of key fields and a plurality of non-key fields (Gao figure 8 [0070] discloses a masking matrix 802 having a plurality of 1 values [i.e., key fields] and a plurality of 0 values [i.e., non-key fields] at different location or indices configured to mask the values of the input feature 801)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the method of Mohapatra to include a process of masking input feature map data as illustrated in Gao. This modification would have been obvious because both Mohapatra and Gao discloses processing data, such as input feature map in neural network. Furthermore, masking input feature map to turn the data into 0 according to masking values would reduce computations of the neural network since zero value can be avoided in computation.
The combined system of Mohapatra in view of Gao does not teach a key mask register storing the mask values. However, Cohen discloses a key mask register for storing mask values (Cohen figure 3 [0080] describes at least one masking register 315 to store mask values, wherein an element of the destination is set to 0 when the corresponding mask bit has a 0 value).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the register file including registers 145a-145c and pooler register 165 of the PEs as disclosed in combined system of Mohapatra in view of Gao to include masking register to store the mask values to mask out the input feature map IFMAP before performing pooling operation. This modification would have been obvious because the combined system of Mohapatra in view of Gao includes mask values to mask the input feature map and Cohen discloses a register to store masking values. Furthermore, having a register to store mask value allow the system to access the mask data faster to mask IFMAP and increase computation speed by skipping the masked values.
As modified, the combined system of Mohapatra in view of Gao and Cohen teaches storing, at a key mask register of the accumulator circuit, indices indicating a plurality of key fields and a plurality of non-key fields for generating a masked plurality of comparison results in max pooling mode.
Allowable Subject Matter
Claims 1-9 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b), set forth in this Office action.
Claims 12-14, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
See OA 09/16/2025 for reasons for allowable subject matter.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUY DUONG whose telephone number is (571)272-2764. The examiner can normally be reached Mon-Friday 7:30-5:30.
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764.
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182