DETAILED ACTION
The Office Action is sent in response to Applicant’s Communication received on 09/16/2025 for application number 17/582,560. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant’s Remarks, and Amendments for Specification, Drawings, and Claims.
Examiner Notes the following: Claims 1-4, 11, 13, and 19-20 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite in that it fails to point out what is included or excluded by the claim language. Claim 1 has the limitation as recited “an output of a multiplexer having a first input connected to… a second input of the multiplexer is connect to…”. However, it is unclear if the structural element of “multiplexer” is part of the machine, as it would normally be recited in a more formal structure with the machine (like for example, the processing element comprising: a multiplexer…). As such, it is unclear if the “multiplexer” is a positively recited element in the claim language and is rejected under 35 U.S.C. 112(b).
Claims 2-7 effectively depends on claim 1 and are rejected for the reason given above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, claims 1-7 recites a modular polynomial multiplier and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 1 recites
A modular polynomial multiplier comprising:
a plurality of processing elements, each processing element comprising:
a multiplication unit with a first input, a second input and an output, wherein with each of a series of clock cycles, the output of the multiplication unit carries the product of a value provided on the first input and a value provided on the second input;
an addition unit having a first input, a second input and an output, wherein the first input is connected to the output of the multiplication unit,; and
a delay unit that has an input connected to the output of the addition unit and an output, wherein the input carries an input value and the output provides the input value delayed by one clock cycle;
wherein the first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial; and
wherein the second input of the multiplication unit of each processing element is connected to an output of a multiplexer having a first input connected to an input line carrying a sequence of coefficients of a second polynomial having n coefficients and a second input of the multiplexer is connected to a delay line carrying the sequence of coefficients of the second polynomial delayed by n clock cycles and negated.
The above underlined limitations are related to multiplication of two polynomial coefficients which amount to mathematical calculations which falls under the “mathematical concepts” of abstract ideas (see Spec. paragraphs 17-23, 27-37, 42-52, and 64-76). Accordingly, the claim is directed to an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 1 recites the following additional elements: “A plurality of processing elements”, “a multiplication unit with a first input, a second input and an output”, “a series of clock cycles”, “an addition unit having a first input, a second input and an output”, “a delay unit that has an input… and an output”, “wherein the first input is connected to the output of the multiplication unit”, “a input connected to the output of the addition unit”, “the input carries an input value”, “the first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial” and “the second input of the multiplication unit of each processing element is connected to an output of a multiplexer having a first input connected to an input line … and a second input of the multiplexer is connected to a delay line…”. However, the additional elements of “A plurality of processing elements”, “a multiplication unit with a first input, a second input and an output”, “a series of clock cycles”, “an addition unit having a first input, a second input and an output”, and “a delay unit that has an input… and an output” are recited at a high-level of generality (i.e., as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for pipelining data; as a generic computer component for adding data; and as a generic computer component for delaying data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “wherein the first input is connected to the output of the multiplication unit”, “a input connected to the output of the addition unit”, “the input carries an input value”, “the first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial” and “the second input of the multiplication unit of each processing element is connected to an output of a multiplexer having a first input connected to an input line … and a second input of the multiplexer is connected to a delay line…” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 1 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “A plurality of processing elements”, “a multiplication unit with a first input, a second input and an output”, “a series of clock cycles”, “an addition unit having a first input, a second input and an output”, and “a delay unit that has an input… and an output” are recited at a high-level of generality (i.e., as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for pipelining data; as a generic computer component for adding data; and as a generic computer component for delaying data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “wherein the first input is connected to the output of the multiplication unit”, “a input connected to the output of the addition unit”, “the input carries an input value”, “the first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial” and “the second input of the multiplication unit of each processing element is connected to an output of a multiplexer having a first input connected to an input line … and a second input of the multiplexer is connected to a delay line…” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 2-7 recite further steps and details to multiplication of sets of two polynomial coefficients for modular polynomial multiplication and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas. Claim 2 is directed to sending partial multiplication data from one delay unit to a addition unit of another processing element in a pipelined process. Claim 3 recites additional processing element to compute the initial partial multiplication. Claim 4 recites additional processing element to compute the final multiplication. Claim 5 recites the input sequence which is a consequence of using a pipeline structure to compute the math. Claim 6 recites outputting the end result of the math. Claim 7 recites the how the math started with the most significant coefficient. In particular, claim 7 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims are directed to an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 2 recites the following additional element: “outputs of delay units.. are connected to second inputs of addition units…”. Claim 3 recites the following additional elements: “a multiplication unit with a first input, a second input, and an output”, “a delay unit that has an input… and an output”, “wherein the first input… carries a coefficient…the second input is connected to the input line”, “an input connected to the output of the multiplication unit”, and “an output connected to a second input…”. Claim 4 recites the following additional elements: “a multiplication unit with a first input, a second input, and an output”, “An addition unit having a first input…, a second input… and an output”, “wherein the first input… carries a coefficient…the second input is connected to one of the input line and the delay line”, “a first input connected to the output of the multiplication unit” and “a second input connected to the output of [the] delay unit”. Claim 5 recites the following additional elements: “the second input of the multiplication unit… is connected to the input line… and is connected to the delay line”, “respective first number of clock cycles” and “respective second number of clock cycles”. Claim 6 recites the following additional element: “a set of contiguous clock cycles”. However, the additional elements of “a multiplication unit with a first input, a second input, and an output”, “a delay unit that has an input… and an output” (from claim 3), “a multiplication unit with a first input, a second input, and an output”, “An addition unit having a first input…, a second input… and an output” (from claim 4), “respective first number of clock cycles” and “respective second number of clock cycles”, and “a set of contiguous clock cycles” are recited at a high-level of generality (i.e., as a generic computer component for multiplying data; as a generic computer component for delaying data; as a generic computer component for adding data; and as a generic computer component for pipelining data;) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “outputs of delay units.. are connected to second inputs of addition units…” (from claim 2), “wherein the first input… carries a coefficient…the second input is connected to the input line”, “an input connected to the output of the multiplication unit”, “an output connected to a second input…” (from claim 3), “wherein the first input… carries a coefficient…the second input is connected to one of the input line and the delay line”, “a first input connected to the output of the multiplication unit” “a second input connected to the output of [the] delay unit” (from claim 4), and “the second input of the multiplication unit… is connected to the input line… and is connected to the delay line” (from claim 5) are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claims 2-7 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a multiplication unit with a first input, a second input, and an output”, “a delay unit that has an input… and an output” (from claim 3), “a multiplication unit with a first input, a second input, and an output”, “An addition unit having a first input…, a second input… and an output” (from claim 4), “respective first number of clock cycles” and “respective second number of clock cycles”, and “a set of contiguous clock cycles” are recited at a high-level of generality (i.e., as a generic computer component for multiplying data; as a generic computer component for delaying data; as a generic computer component for adding data; and as a generic computer component for pipelining data;) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “outputs of delay units.. are connected to second inputs of addition units…” (from claim 2), “wherein the first input… carries a coefficient…the second input is connected to the input line”, “an input connected to the output of the multiplication unit”, “an output connected to a second input…” (from claim 3), “wherein the first input… carries a coefficient…the second input is connected to one of the input line and the delay line”, “a first input connected to the output of the multiplication unit” “a second input connected to the output of [the] delay unit” (from claim 4), and “the second input of the multiplication unit… is connected to the input line… and is connected to the delay line” (from claim 5) are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claims 8-15 recites a modular polynomial multiplier and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 8 recites
A modular polynomial multiplier comprising:
a first modular polynomial multiplier configured to produce a first modular product of a first portion of a first polynomial and a first portion of a second polynomial, the first modular product produced as a first series of coefficients with a separate coefficient at each of a set of clock cycles;
a second modular polynomial multiplier configured to produce a second modular product of a second portion of the first polynomial and a second portion of the second polynomial, the second modular product produced as a second series of coefficients with a separate coefficient at each of the set of clock cycles;
a first delay circuit configured to delay the first series of coefficients by one clock cycle to form a delayed series of coefficients;
a second delay circuit configured to delay a first coefficient in the second series of coefficients by a number of clock cycles equal to the number of coefficients in the second series of coefficients to form a modified series of coefficients; and
an addition unit configured to add coefficients in the delayed series of coefficients to coefficients in the modified series of coefficients.
The above underlined limitations are related to multiplication of sets of two polynomial coefficients for modular polynomial multiplication which amount to mathematical calculations which falls under the “mathematical concepts” grouping of abstract ideas (see paragraphs 17-23, 27-37, 42-52, and 64-76). Accordingly, the claim is directed to an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 1 recites the following additional elements: “a first modular polynomial multiplier”, “a second modular polynomial multiplier”, “a first delay circuit”, “a second delay circuit” and “an addition unit”. However, the additional elements of “a first modular polynomial multiplier”, “a second modular polynomial multiplier”, “a first delay circuit”, “a second delay circuit” and “an addition unit” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication; as a generic computer component for delaying data; and as a generic computer component for addition) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 8 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first modular polynomial multiplier”, “a second modular polynomial multiplier”, “a first delay circuit”, “a second delay circuit” and “an addition unit” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication; as a generic computer component for delaying data; and as a generic computer component for addition) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 9-15 recite further steps and details to multiplication of sets of two polynomial coefficients for modular polynomial multiplication and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas. Claim 9, directed to the structure of the delay circuit to apply the delay to a specific element in order to complete the mathematical operation that requires an input at a specific time. Claim 10, directed to negating the first coefficient to complete the mathematical operation. Claims 11 and 13, recites plurality of processing elements that does multiplication, addition, and delays wherein the inputs are a requirement of the mathematical operation and the clock cycles is a consequence of the math that is applied in pipelined hardware. Claim 12, directed to repeating the similar limitations and reasons to why claim 8 is directed to an abstract idea. Claims 14 and 15, is directed to applying the math similarly to the other multiplier in claims 8 and 12 respectively, wherein the structure is identical to the other multiplier which is applying the modular polynomial multiplication. Accordingly, the claims are directed to an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 9 recites the following additional elements: “a delay unit”, “a first switch”, and “a second switch”. Claim 10 recites the following additional element: “a negation unit”. Claim 11 recites the following additional elements: “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles”, “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…”. Claim 12 recites the following additional elements: “a third modular polynomial multiplier”, “a fourth modular polynomial multiplier”, “a third delay circuit”, “a fourth delay circuit” and “a second addition unit”. Claim 13 recites the following additional elements which are similar to claim 11: “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles”, “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…”. Claim 14 recites the following additional element: “the first modular polynomial multiplier is structurally identical to the second modular polynomial multiplier”. Claim 15 recites the following additional element: “the third modular polynomial multiplier is structurally identical to the fourth modular polynomial multiplier”. However, the additional elements of “a delay unit”, “a first switch”, “a second switch” (from claim 9), “a negation unit” (from claim 10), “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles” (from claim 11), “a third modular polynomial multiplier”, “a fourth modular polynomial multiplier”, “a third delay circuit”, “a fourth delay circuit”, “a second addition unit” (from claim 12), “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles” (from claim 13), “the first modular polynomial multiplier is structurally identical to the second modular polynomial multiplier” (from claim 14), and “the third modular polynomial multiplier is structurally identical to the fourth modular polynomial multiplier” (from claim 15) are recited at a high-level of generality (i.e., as a generic computer component for delaying; as a generic computer component for switching/routing data; as a generic computer component for negating data; as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for adding data; as a generic computer component for pipelining data; and as a generic computer component that is identical to another generic computer component for multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” (from claim 11), “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” (from claim 13) are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claims 9-15 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a delay unit”, “a first switch”, “a second switch” (from claim 9), “a negation unit” (from claim 10), “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles” (from claim 11), “a third modular polynomial multiplier”, “a fourth modular polynomial multiplier”, “a third delay circuit”, “a fourth delay circuit”, “a second addition unit” (from claim 12), “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles” (from claim 13), “the first modular polynomial multiplier is structurally identical to the second modular polynomial multiplier” (from claim 14), and “the third modular polynomial multiplier is structurally identical to the fourth modular polynomial multiplier” (from claim 15) are recited at a high-level of generality (i.e., as a generic computer component for delaying; as a generic computer component for switching/routing data; as a generic computer component for negating data; as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for adding data; as a generic computer component for pipelining data; and as a generic computer component that is identical to another generic computer component for multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” (from claim 11), “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” (from claim 13) are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claims 16-20 recites a modular polynomial multiplier and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 16 recites
A modular polynomial multiplier comprising:
a first circuit receiving a first sub-polynomial of a first polynomial and a first sub- polynomial of a second polynomial and producing a modular product of the first sub-polynomial of the first polynomial and the first sub-polynomial of the second polynomial; and
a second circuit receiving a second sub-polynomial of the first polynomial and a second sub-polynomial of the second polynomial and producing a modular product of the second sub-polynomial of the first polynomial and the second sub-polynomial of the second polynomial; wherein the first circuit and the second circuit are identical to each other.
The above underlined limitations are related to multiplication of sets of two polynomial coefficients for modular polynomial multiplication which amount to mathematical calculations which falls under the “mathematical concepts” grouping of abstract ideas (see paragraphs 17-23, 27-37, 42-52, and 64-76). Accordingly, the claim is directed to an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 1 recites the following additional elements: “a first circuit”, “a second circuit”, “receiving a first sub-polynomial of a first polynomial and a first sub- polynomial of a second polynomial”, “receiving a second sub-polynomial of the first polynomial and a second sub-polynomial of the second polynomial” and “wherein the first circuit and the second circuit are identical to each other”. However, the additional elements of “a first circuit”, “a second circuit” and “wherein the first circuit and the second circuit are identical to each other” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receiving a first sub-polynomial of a first polynomial and a first sub- polynomial of a second polynomial” and “receiving a second sub-polynomial of the first polynomial and a second sub-polynomial of the second polynomial” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 8 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first circuit”, “a second circuit” and “wherein the first circuit and the second circuit are identical to each other” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receiving a first sub-polynomial of a first polynomial and a first sub- polynomial of a second polynomial” and “receiving a second sub-polynomial of the first polynomial and a second sub-polynomial of the second polynomial” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 16-20 recite further steps and details to multiplication of sets of two polynomial coefficients for modular polynomial multiplication and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas. Claim 17, directed to repeating the similar limitations and reasons to why claim 16 is directed to an abstract idea. Claim 18, directed to delaying the coefficients to the correct time in order to complete the modular polynomial multiplication. Claim 19, directed to delaying the coefficients to the correct time in order to complete the modular polynomial multiplication. Claim 20, recites plurality of processing elements that does multiplication, addition, and delays wherein the inputs are a requirement of the mathematical operation and the clock cycles is a consequence of the math that is applied in pipelined hardware. Accordingly, the claims are directed to an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 17 recites the following additional elements: “a first sub-circuit”, “a second sub-circuit”, and “wherein the first sub-circuit is identical to the second sub-circuit”. Claim 18 recites the following additional elements: “a first delay circuit”, “a second delay circuit” and “an addition circuit”. Claim 19 recites the following additional elements: “a third delay circuit”, “a fourth delay circuit” and “an [second] addition circuit”. Claim 20 recites the following additional elements: “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles”, “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…”. However, the additional elements of “a first sub-circuit”, “a second sub-circuit”, “wherein the first sub-circuit is identical to the second sub-circuit”, “a first delay circuit”, “a second delay circuit”, “an addition circuit”, “a third delay circuit”, “a fourth delay circuit”, “an [second] addition circuit”, “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, and “a delay unit that has an input … and an output”, and “a series of clock cycles” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication; as a generic computer component for delaying; as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for adding data; as a generic computer component for pipelining data; and as a generic computer component that is identical to another generic computer component for multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claims 17-20 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first sub-circuit”, “a second sub-circuit”, “wherein the first sub-circuit is identical to the second sub-circuit”, “a first delay circuit”, “a second delay circuit”, “an addition circuit”, “a third delay circuit”, “a fourth delay circuit”, “an [second] addition circuit”, “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, and “a delay unit that has an input … and an output”, and “a series of clock cycles” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication; as a generic computer component for delaying; as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for adding data; as a generic computer component for pipelining data; and as a generic computer component that is identical to another generic computer component for multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Paksoy et al. (NPL: “New TMVP-based Algorithms for Polynomial Quotient Rings and Application to Saber on ARM Cortex-M4”), hereinafter Paksoy, and in view of Parker et al. (NPL: “Low-Area/Power Parallel FIR Digital Filter Implementations” from IDS filed 05/31/2022), hereinafter Parker.
Regarding claims 16 and 17, see prior Office Action mailed 06/16/2025 and response to arguments below.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Paksoy, Parker, and further in view of Illinois Urbana-Champaign (NPL: “Pipeline Motivation: Single-cycle datapath”), hereinafter Illinois, and further in view of Tuan (US 9,355,690 B1).
Regarding claims 18 and 19, see prior Office Action mailed 06/16/2025 and response to arguments below.
Claim 20 are rejected under 35 U.S.C. 103 as being unpatentable over Paksoy, Parker, and further in view of Wezelenburg, and further in view of Ghosh.
Response to Arguments
Applicant’s arguments, see p.12, filed 09/16/2025, with respect to Drawings, Specification and Claim Objections have been fully considered and are persuasive. The Drawings, Specification and Claim Objections of the Office Action mailed 06/16/2025 has been withdrawn.
Applicant's arguments, see pages 12-22, filed 09/16/2025, with respect to Rejections under 35 U.S.C. 101 have been fully considered but they are not persuasive.
Regarding claim 1 (and 2-7), the applicant argues [on p.13-14] that the in the Office Action the parts of claim 1 that were asserted to recite “mathematical concepts” does not recite mathematical concepts. However, the applicant in considering the parts of claim 1 as NOT “mathematical concepts” would then be considered additional elements under Step 2A Prong 1 and Prong 2 and Step 2B. The Examiner notes that the parts of claim 1 in question are directed to mathematical output of multiplication and pipelining/delaying the output to ensure the mathematical formula is computed properly as disclosed in specification paragraphs 23-38. In the case that the parts of claim 1 does not belong to mathematical concepts, it would then be directed to Insignificant Extra-Solution Activity. However, the applicant has not argued these additional elements under Step 2A Prong 1 and Prong 2 and Step 2B.
The Applicant also argues [on p.14-15] that claim 1 does not refer to generic elements but instead provides specific processing elements with specific components that are connected together in specific ways. However, the “specific” components (i.e. multiplication unit and addition unit) are just merely performing the basic functions of multiplication and addition. A processor consisting of generic components, performing basic functions of multiplication and addition, is merely a generic component for “applying” the abstract idea. Additionally processing elements are just merely implementing the mathematical formulas as shown in paragraph 23 (and 17, and 21-22). Furthermore, the Applicant states that claim 1 has been amended to include a multiplexer, but has not positively recited such multiplexer. See rejection under 35 U.S.C. 112(b) above.
The Applicant also argues [on p.15] that the machine implements the steps of the method and the machine do more than simply perform an extra solution activity. However, the Applicant has not shown how the processing elements amount to significantly more than a judicial exception or how the extra-solution activity imposes meaningful limits on the claim. See previous 2 paragraphs and rejection under 35 U.S.C. 101.
The Applicant also argues [on p.15-17] that the claim reflects the improvement as described in the specification. However, the Applicant points to a paragraph talking about a 4-parallel architecture and states that the structure in claim 8 is part of such architecture, but does not talk about the structure itself. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Additionally, the improvement cannot come from the abstract idea itself, i.e. the improvement is a consequence of the mathematical concept. See specification paragraphs 21-23, 42-45, 49, 51-52, 61-63, and 67-73 and arguments above. The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reasons given above.
Regarding claim 8 (and 9-15), the applicant argues [on p.17-18] that the in the Office Action the parts of claim 8 to deal with coefficients at each clock cycle and delaying such coefficients are not directed to abstract ideas but timing and control concepts. However, the applicant in considering the parts of claim 8 as NOT “mathematical concepts” would then be considered additional elements under Step 2A Prong 1 and Prong 2 and Step 2B. The Examiner notes that the parts of claim 8 in question are directed to mathematical output of the multiplication of the formulas disclosed in in specification paragraphs 23-38 and pipelining/delaying the output to ensure the mathematical formula is computed properly as disclosed in specification paragraph 42 (and 43-59, see at least par. 52, eq.21 which shows the delay required for the formula). In the case that the parts of claim 8 does not belong to mathematical concepts, it would then be directed to Insignificant Extra-Solution Activity. However, the applicant has not argued these additional elements under Step 2A Prong 1 and Prong 2 and Step 2B.
The Applicant also argues [on p.19] that claim 8 does not refer to generic elements but instead provides specific processing elements with specific components that are connected together in specific ways. However, as argued above for the modular polynomial multiplier a processor consisting of generic components is merely a generic component for “applying” the abstract idea, similarly for the delay unit for applying the formula. Although the claims are interpreted in light of the specification and as the claim limitations is not interpreted under 112(f), the limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, The delay circuit is merely a generic circuit for delaying an element to implement the mathematical formula (i.e. eq.21).
The Applicant also argues [on p.19-20] that the machine implements the steps of the method and the machine do more than simply perform an extra solution activity. However, the Applicant has not shown how the processing elements amount to significantly more than a judicial exception or how the extra-solution activity imposes meaningful limits on the claim. See previous 2 paragraphs and rejection under 35 U.S.C. 101.
The Applicant also argues [on p.20-21] that the claim reflects the improvement as described in the specification. However, the Applicant points to a paragraph talking about a 4-parallel architecture and states that the structure in claim 8 is part of such architecture, but does not talk about the structure itself. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Additionally, the improvement cannot come from the abstract idea itself, i.e. the improvement is a consequence of the mathematical concept. See specification paragraphs 21-23, 42-45, 49, 51-52, 61-63, and 67-73 and arguments above. The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reasons given above.
Regarding claim 16 (and 17-20), the Applicant also argues [on p.21-22] that the claim reflects the improvement as described in the specification. However, the Applicant points to a paragraph talking about a 4-parallel architecture and states that the structure in claim 8 is part of such architecture (and a 2-parallel architecture), but does not talk about the structure itself. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Additionally, the improvement cannot come from the abstract idea itself, i.e. the improvement is a consequence of the mathematical concept. See specification paragraphs 21-23, 42-45, 49, 51-52, 61-63, and 67-73 and arguments above. The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reasons given above.
Applicant's arguments, see page 22, filed 09/16/2025, with respect to Rejections under 35 U.S.C. 103 have been fully considered but they are not persuasive. Regarding claim 1 (and 2-7), the applicant argues that the prior art does not show or suggest a multiplexer with two inputs: a sequence of coefficients and a negated delayed sequence of the coefficients. However, the argument is directed to a non-positively recited multiplexer. See rejection under 35 U.S.C. 112(b) above. The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reasons given above.
Applicant's arguments, see page 25, filed 09/16/2025, with respect to Rejections under 35 U.S.C. 103 have been fully considered but they are not persuasive. Regarding claim 16 (and 17-20), the applicant argues the modification of Parker to use modular products would destroy the functionality of Parker. However, the argument does not address the rejection made, wherein Paksoy is modified by Parker. See Office Action mailed 06/06/2025, p.50-51. The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reasons given above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 9:00 am to 2:00 pm on Monday, 8:00 am to 5:00 pm on Tuesday to Thursday, and 8:00 am to 4:00pm on Friday ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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