DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/30/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, claims 1-7 recites a modular polynomial multiplier and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 1 recites
A modular polynomial multiplier comprising:
a plurality of processing elements, each processing element comprising:
a multiplication unit with a first input, a second input and an output, wherein with each of a series of clock cycles, the output of the multiplication unit carries the product of a value provided on the first input and a value provided on the second input;
an addition unit having a first input, a second input and an output, wherein the first input is connected to the output of the multiplication unit,; and
a delay unit that has an input connected to the output of the addition unit and an output, wherein the input carries an input value and the output provides the input value delayed by one clock cycle;
A plurality of multiplexers;
wherein the first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial; and
wherein the second input of the multiplication unit of each processing element is connected to an output of a respective multiplexer of the plurality of multiplexers, the respective multiplexer having a first input connected to an input line carrying a sequence of coefficients of a second polynomial having n coefficients and a second input of the respective multiplexer is connected to a delay line carrying the sequence of coefficients of the second polynomial delayed by n clock cycles and negated.
The above underlined limitations are related to multiplication of two polynomial coefficients which amount to mathematical calculations which falls under the “mathematical concepts” of abstract ideas (see Spec. paragraphs 17-23, 27-37, 42-52, and 64-76). Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 1 recites the following additional elements: “A plurality of processing elements”, “a multiplication unit with a first input, a second input and an output”, “a series of clock cycles”, “an addition unit having a first input, a second input and an output”, “a delay unit that has an input… and an output”, “wherein the first input is connected to the output of the multiplication unit”, “a input connected to the output of the addition unit”, “the input carries an input value”, “a plurality of multiplexers”, “the first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial” and “the second input of the multiplication unit of each processing element is connected to an output of a respective multiplexer… having a first input connected to an input line … and a second input of the respective multiplexer is connected to a delay line…”. However, the additional elements of “A plurality of processing elements”, “a multiplication unit with a first input, a second input and an output”, “a series of clock cycles”, “an addition unit having a first input, a second input and an output”, “a delay unit that has an input… and an output”, and “plurality of multiplexers” are recited at a high-level of generality (i.e., as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for pipelining data; as a generic computer component for adding data; as a generic computer component for delaying data; and as a generic computer component for routing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “wherein the first input is connected to the output of the multiplication unit”, “a input connected to the output of the addition unit”, “the input carries an input value”, “the first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial” and “the second input of the multiplication unit of each processing element is connected to an output of a respective multiplexer… having a first input connected to an input line … and a second input of the respective multiplexer is connected to a delay line…” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 1 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “A plurality of processing elements”, “a multiplication unit with a first input, a second input and an output”, “a series of clock cycles”, “an addition unit having a first input, a second input and an output”, “a delay unit that has an input… and an output”, and “plurality of multiplexers” are recited at a high-level of generality (i.e., as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for pipelining data; as a generic computer component for adding data; as a generic computer component for delaying data; and as a generic computer component for routing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “wherein the first input is connected to the output of the multiplication unit”, “a input connected to the output of the addition unit”, “the input carries an input value”, “the first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial” and “the second input of the multiplication unit of each processing element is connected to an output of a respective multiplexer… having a first input connected to an input line … and a second input of the respective multiplexer is connected to a delay line…” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 2-7 recite further steps and details to multiplication of sets of two polynomial coefficients for modular polynomial multiplication and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas.
Claim 2 is directed to sending partial multiplication data from one delay unit to an addition unit of another processing element in a pipelined process. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional element: “outputs of delay units.. are connected to second inputs of addition units…”. The additional element of “outputs of delay units.. are connected to second inputs of addition units…” is merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “outputs of delay units.. are connected to second inputs of addition units…” is merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 3 recites additional processing element to compute the initial partial multiplication. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional element: “a multiplication unit with a first input, a second input, and an output”, “a delay unit that has an input… and an output”, “wherein the first input… carries a coefficient…the second input is connected to the input line”, “an input connected to the output of the multiplication unit”, and “an output connected to a second input…”. However, the additional elements of “a multiplication unit with a first input, a second input, and an output”, “a delay unit that has an input… and an output” are recited at a high-level of generality (i.e., as a generic computer component for multiplying data; and as a generic computer component for delaying data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “wherein the first input… carries a coefficient…the second input is connected to the input line”, “an input connected to the output of the multiplication unit”, “an output connected to a second input…” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a multiplication unit with a first input, a second input, and an output”, “a delay unit that has an input… and an output” are recited at a high-level of generality (i.e., as a generic computer component for multiplying data; and as a generic computer component for delaying data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “wherein the first input… carries a coefficient…the second input is connected to the input line”, “an input connected to the output of the multiplication unit”, “an output connected to a second input…” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 4 recites additional processing element to compute the final multiplication. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “a multiplication unit with a first input, a second input, and an output”, “An addition unit having a first input…, a second input… and an output”, “wherein the first input… carries a coefficient…the second input is connected to one of the input line and the delay line”, “a first input connected to the output of the multiplication unit” and “a second input connected to the output of [the] delay unit”. However, the additional elements of “a multiplication unit with a first input, a second input, and an output”, and “An addition unit having a first input…, a second input… and an output” are recited at a high-level of generality (i.e., as a generic computer component for multiplying data; and as a generic computer component for adding data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “wherein the first input… carries a coefficient…the second input is connected to one of the input line and the delay line”, “a first input connected to the output of the multiplication unit” and “a second input connected to the output of the delay unit” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a multiplication unit with a first input, a second input, and an output”, and “An addition unit having a first input…, a second input… and an output” are recited at a high-level of generality (i.e., as a generic computer component for multiplying data; and as a generic computer component for adding data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “wherein the first input… carries a coefficient…the second input is connected to one of the input line and the delay line”, “a first input connected to the output of the multiplication unit” and “a second input connected to the output of the delay unit” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 5 recites the input sequence which is a consequence of using a pipeline structure to compute the math. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “the second input of the multiplication unit… is connected to the input line… and is connected to the delay line”, “respective first number of clock cycles” and “respective second number of clock cycles”. However, the additional elements of “respective first number of clock cycles” and “respective second number of clock cycles” are recited at a high-level of generality (i.e., as a generic computer component for pipelining data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “the second input of the multiplication unit… is connected to the input line… and is connected to the delay line” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “respective first number of clock cycles” and “respective second number of clock cycles” are recited at a high-level of generality (i.e., as a generic computer component for pipelining data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “the second input of the multiplication unit… is connected to the input line… and is connected to the delay line” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 6 recites outputting the end result of the math. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “a set of contiguous clock cycles”. However, the additional elements of “a set of contiguous clock cycles” is recited at a high-level of generality (i.e., as a generic computer component for pipelining data;) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a set of contiguous clock cycles” is recited at a high-level of generality (i.e., as a generic computer component for pipelining data;) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 7 recites the how the math starts with the most significant coefficient. In particular, claim 7 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claim recites an abstract idea.
Claims 8-15 recites a modular polynomial multiplier and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 8 recites
A modular polynomial multiplier circuit comprising:
a first modular polynomial multiplier circuit configured to produce a first modular product of a first portion of a first polynomial and a first portion of a second polynomial, the first modular product produced as a first series of coefficients with a separate coefficient at each of a set of clock cycles;
a second modular polynomial multiplier circuit configured to produce a second modular product of a second portion of the first polynomial and a second portion of the second polynomial, the second modular product produced as a second series of coefficients with a separate coefficient at each of the set of clock cycles;
a first delay circuit configured to delay the first series of coefficients by one clock cycle to form a delayed series of coefficients;
a second delay circuit configured to delay a first coefficient in the second series of coefficients by a number of clock cycles equal to the number of coefficients in the second series of coefficients to form a modified series of coefficients; and
an addition unit configured to add coefficients in the delayed series of coefficients to coefficients in the modified series of coefficients.
The above underlined limitations are related to multiplication of sets of two polynomial coefficients for modular polynomial multiplication which amount to mathematical calculations which falls under the “mathematical concepts” grouping of abstract ideas (see paragraphs 17-23, 27-37, 42-52, and 64-76). Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 1 recites the following additional elements: “a first modular polynomial multiplier circuit”, “a second modular polynomial multiplier circuit”, “a first delay circuit”, “a second delay circuit” and “an addition unit”. However, the additional elements of “a first modular polynomial multiplier circuit”, “a second modular polynomial multiplier circuit”, “a first delay circuit”, “a second delay circuit” and “an addition unit” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication; as a generic computer component for delaying data; and as a generic computer component for addition) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 8 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first modular polynomial multiplier circuit”, “a second modular polynomial multiplier circuit”, “a first delay circuit”, “a second delay circuit” and “an addition unit” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication; as a generic computer component for delaying data; and as a generic computer component for addition) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 9-15 recite further steps and details to multiplication of sets of two polynomial coefficients for modular polynomial multiplication and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas.
Claim 9, directed to the structure of the delay circuit to apply the delay to a specific element in order to complete the mathematical operation that requires an input at a specific time. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 9 recites the following additional elements: “a delay unit”, “a first switch”, and “a second switch”. However, the additional elements of “a delay unit”, “a first switch”, and “a second switch” are recited at a high-level of generality (i.e., as a generic computer component for delaying; and as a generic computer component for switching/routing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a delay unit”, “a first switch”, and “a second switch” are recited at a high-level of generality (i.e., as a generic computer component for delaying; and as a generic computer component for switching/routing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 10, directed to negating the first coefficient to complete the mathematical operation. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, Claim 10 recites the following additional element: “a negation unit”. However, the additional element of “a negation unit” is recited at a high-level of generality (i.e., as a generic computer component for negating data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a negation unit” is recited at a high-level of generality (i.e., as a generic computer component for negating data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claims 11 and 13, recites plurality of processing elements that does multiplication, addition, and delays wherein the inputs are a requirement of the mathematical operation and the clock cycles is a consequence of the math that is applied in pipelined hardware. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, Claim 11 recites the following additional elements: “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles”, “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…”. Claim 13 recites the following additional elements which are similar to claim 11: “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles”, “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…”. However, the additional elements of “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles” (from claim 11), “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, and “a series of clock cycles” (from claim 13) are recited at a high-level of generality (i.e., as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for adding data; and as a generic computer component for pipelining data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” (from claim 11), “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” (from claim 13) are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles” (from claim 11), “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, and “a series of clock cycles” (from claim 13) are recited at a high-level of generality (i.e., as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for adding data; and as a generic computer component for pipelining data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” (from claim 11), “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” (from claim 13) are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 12, directed to repeating the similar limitations and reasons to why claim 8 is directed to an abstract idea. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, Claim 12 recites the following additional elements: “a third modular polynomial multiplier”, “a fourth modular polynomial multiplier”, “a third delay circuit”, “a fourth delay circuit” and “a second addition unit”. However, the additional elements of “a third modular polynomial multiplier”, “a fourth modular polynomial multiplier”, “a third delay circuit”, “a fourth delay circuit”, and “a second addition unit” are recited at a high-level of generality (i.e., as a generic computer component for delaying; as a generic computer component for switching/routing data; as a generic computer component for negating data; as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for adding data; and as a generic computer component for pipelining data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a third modular polynomial multiplier”, “a fourth modular polynomial multiplier”, “a third delay circuit”, “a fourth delay circuit”, and “a second addition unit” are recited at a high-level of generality (i.e., as a generic computer component for delaying; as a generic computer component for switching/routing data; as a generic computer component for negating data; as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for adding data; and as a generic computer component for pipelining data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claims 14 and 15, is directed to applying the math similarly to the other multiplier in claims 8 and 12 respectively, wherein the structure is identical to the other multiplier which is applying the modular polynomial multiplication. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, Claim 14 recites the following additional element: “the first modular polynomial multiplier is structurally identical to the second modular polynomial multiplier”. Claim 15 recites the following additional element: “the third modular polynomial multiplier is structurally identical to the fourth modular polynomial multiplier”. However, the additional elements of “the first modular polynomial multiplier is structurally identical to the second modular polynomial multiplier” (from claim 14), and “the third modular polynomial multiplier is structurally identical to the fourth modular polynomial multiplier” (from claim 15) are recited at a high-level of generality (i.e., as a generic computer component that is identical to another generic computer component for multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “the first modular polynomial multiplier is structurally identical to the second modular polynomial multiplier” (from claim 14), and “the third modular polynomial multiplier is structurally identical to the fourth modular polynomial multiplier” (from claim 15) are recited at a high-level of generality (i.e., as a generic computer component that is identical to another generic computer component for multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claims 16-20 recites a modular polynomial multiplier and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 16 recites
A modular polynomial multiplier comprising:
a first circuit receiving a first sub-polynomial of a first polynomial and a first sub- polynomial of a second polynomial and producing a modular product of the first sub-polynomial of the first polynomial and the first sub-polynomial of the second polynomial; and
a second circuit receiving a second sub-polynomial of the first polynomial and a second sub-polynomial of the second polynomial and producing a modular product of the second sub-polynomial of the first polynomial and the second sub-polynomial of the second polynomial; wherein the first circuit and the second circuit are identical to each other.
The above underlined limitations are related to multiplication of sets of two polynomial coefficients for modular polynomial multiplication which amount to mathematical calculations which falls under the “mathematical concepts” grouping of abstract ideas (see paragraphs 17-23, 27-37, 42-52, and 64-76). Accordingly, the claim is directed to an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 1 recites the following additional elements: “a first circuit”, “a second circuit”, “receiving a first sub-polynomial of a first polynomial and a first sub- polynomial of a second polynomial”, “receiving a second sub-polynomial of the first polynomial and a second sub-polynomial of the second polynomial” and “wherein the first circuit and the second circuit are identical to each other”. However, the additional elements of “a first circuit”, “a second circuit” and “wherein the first circuit and the second circuit are identical to each other” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receiving a first sub-polynomial of a first polynomial and a first sub- polynomial of a second polynomial” and “receiving a second sub-polynomial of the first polynomial and a second sub-polynomial of the second polynomial” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 8 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first circuit”, “a second circuit” and “wherein the first circuit and the second circuit are identical to each other” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receiving a first sub-polynomial of a first polynomial and a first sub- polynomial of a second polynomial” and “receiving a second sub-polynomial of the first polynomial and a second sub-polynomial of the second polynomial” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 17-20 recite further steps and details to multiplication of sets of two polynomial coefficients for modular polynomial multiplication and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas.
Claim 17, directed to repeating the similar limitations and reasons to why claim 16 is directed to an abstract idea. Accordingly, the claims recites to an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 17 recites the following additional elements: “a first sub-circuit”, “a second sub-circuit”, and “wherein the first sub-circuit is identical to the second sub-circuit”. However, the additional elements of “a first sub-circuit”, “a second sub-circuit”, and “wherein the first sub-circuit is identical to the second sub-circuit” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first sub-circuit”, “a second sub-circuit”, and “wherein the first sub-circuit is identical to the second sub-circuit” are recited at a high-level of generality (i.e., as a generic computer component for modular polynomial multiplication) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 18, directed to delaying the coefficients to the correct time in order to complete the modular polynomial multiplication. Accordingly, the claims recites to an abstract idea.
Under the Alice Framework Step 2A prong 2, Claim 18 recites the following additional elements: “a first delay circuit”, “a second delay circuit” and “an addition circuit”. However, the additional elements of “a first delay circuit”, “a second delay circuit”, and “an addition circuit” are recited at a high-level of generality (i.e., as a generic computer component for delaying; and as a generic computer component for adding) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first delay circuit”, “a second delay circuit”, and “an addition circuit” are recited at a high-level of generality (i.e., as a generic computer component for delaying; and as a generic computer component for adding) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 19, directed to delaying the coefficients to the correct time in order to complete the modular polynomial multiplication. Accordingly, the claims recites to an abstract idea.
Under the Alice Framework Step 2A prong 2, Claim 19 recites the following additional elements: “a third delay circuit”, “a fourth delay circuit” and “an second addition circuit”. However, the additional elements “a third delay circuit”, “a fourth delay circuit”, and “an second addition circuit” are recited at a high-level of generality (i.e., as a generic computer component for delaying; and as a generic computer component for adding) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements “a third delay circuit”, “a fourth delay circuit”, and “an second addition circuit” are recited at a high-level of generality (i.e., as a generic computer component for delaying; and as a generic computer component for adding) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 20, recites plurality of processing elements that does multiplication, addition, and delays wherein the inputs are a requirement of the mathematical operation and the clock cycles is a consequence of the math that is applied in pipelined hardware. Accordingly, the claims recites to an abstract idea.
Under the Alice Framework Step 2A prong 2, Claim 20 recites the following additional elements: “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, “a delay unit that has an input … and an output”, “a series of clock cycles”, “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…”. However, the additional elements of “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, and “a delay unit that has an input … and an output”, and “a series of clock cycles” are recited at a high-level of generality (i.e., as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for adding data; and as a generic computer component for pipelining data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a plurality of processing elements”, “a multiplication unit with a first… an output”, “an addition unit having a first… an output”, and “a delay unit that has an input … and an output”, and “a series of clock cycles” are recited at a high-level of generality (i.e., as a generic computer component for processing data; as a generic computer component for multiplying data; as a generic computer component for adding data; and as a generic computer component for pipelining data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “wherein the first input is connected to the output of the multiplication unit”, “an input connected to the output of the addition unit”, “wherein the input carries an input value”, “the first input of the multiplication unit… coefficient of a first polynomial”, and “the second input of the multiplication unit… a sequence of coefficients… and the sequence of coefficients… negated and delayed by a number of clock cycles…” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Paksoy et al. (NPL: “New TMVP-based Algorithms for Polynomial Quotient Rings and Application to Saber on ARM Cortex-M4”), hereinafter Paksoy, and in view of Parker et al. (NPL: “Low-Area/Power Parallel FIR Digital Filter Implementations” from IDS filed 05/31/2022), hereinafter Parker.
Regarding claim 16, Paksoy discloses:
split formulas and decompositions can be derived from any polynomial multiplication algorithms [“different split formulas for TMVPs can be derived from any given polynomial multiplication algorithm” Sec.2.1]
a processor for computing modulo polynomial multiplication using arithmetic operations with modulo [“We implement this algorithm on the ARM Cortex-M4” 3.5 Implementation Results; “The product c(x)…of the polynomials a(x) and b(x) in R can be calculated by reducing c′(x) modulo xn ± 1… arithmetic operations include reduction modulo q” 2.2 Polynomial Multiplication Modulo xn ± 1 via TMVP]
However, Paksoy does not explicitly disclose:
a first circuit receiving a first sub-polynomial of a first polynomial and a first sub- polynomial of a second polynomial and producing a modular product of the first sub-polynomial of the first polynomial and the first sub-polynomial of the second polynomial; and a second circuit receiving a second sub-polynomial of the first polynomial and a second sub-polynomial of the second polynomial and producing a modular product of the second sub-polynomial of the first polynomial and the second sub-polynomial of the second polynomial; wherein the first circuit and the second circuit are identical to each other.
In the analogous art of Polynomial Multiplication implementations, Parker teaches a first circuit receiving a first sub-polynomial of a first polynomial and a first sub- polynomial of a second polynomial and producing a modular product of the first sub-polynomial of the first polynomial and the first sub-polynomial of the second polynomial; and a second circuit receiving a second sub-polynomial of the first polynomial and a second sub-polynomial of the second polynomial and producing a modular product of the second sub-polynomial of the first polynomial and the second sub-polynomial of the second polynomial; wherein the first circuit and the second circuit are identical to each other [Figure 5, item H0’ and H’; “the product terms in the polynomial formulation of the parallel FIR filter are equivalent to filtering operations” 3.1 An Introduction of Fast FIR algorithms; "If a L-parallel filter is operated at the same clock rate as the original filter, L output samples are generated every clock cycle…" 2. Parallel Processing for High-Speed or Low-Power; “The 4-parallel structure shown in Fig. 5 can be thought of as 3 separate (2-by-2) FFAs each producing 2 outputs which are combined to produce the 4 filter outputs.” 3.4. Cascading Fast FIR Algorithms].
It would have been obvious to one of ordinary skill in the art, having the teachings of Paksoy and Parker before him before the effective filing date of the claimed invention to modify the processor for modulo polynomial multiplication as disclosed by Paksoy to use the polynomial multiplication decomposition with the FIR parallel structure as taught by Parker, in order to, implement a structure and technique to increase throughput or decrease the power consumption for polynomial multiplication [Parker: 3.1. An Introduction to Fast FIR Algorithms]. The combination of Paksoy and Parker discloses the limitations in claim 16.
Regarding claim 17, Paksoy and Parker disclose the invention substantially as claimed. See the discussion of claim 16 above.
Paksoy discloses producing a modular product of polynomials [Sec.2.2].
In the analogous art of Polynomial Multiplication implementations, Parker teaches a first sub-circuit producing a product of a first sub-sub-polynomial of the first sub-polynomial of the first polynomial and a first sub-sub-polynomial of the first sub-polynomial of the second polynomial; and a second sub-circuit producing a product of a second sub-sub-polynomial of the first sub-polynomial of the first polynomial and a second sub-sub-polynomial of the first sub-polynomial of the second polynomial; wherein the first sub-circuit is identical to the second sub-circuit [Figure 5, item H0’ (sub-polynomial) and H0 and H1 (sub-sub-polynomials)].
It would have been obvious to one of ordinary skill in the art, having the teachings of Paksoy and Parker before him before the effective filing date of the claimed invention to modify the processor for modulo polynomial multiplication as disclosed by Paksoy to use the polynomial multiplication decomposition with the FIR parallel structure as taught by Parker, in order to, implement a structure and technique to increase throughput or decrease the power consumption for polynomial multiplication [Parker: 3.1. An Introduction to Fast FIR Algorithms]. Wherein the combination of Paksoy and Parker discloses the additional limitations of claim 17
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Paksoy, Parker, and further in view of Illinois Urbana-Champaign (NPL: “Pipeline Motivation: Single-cycle datapath”), hereinafter Illinois, and further in view of Tuan (US 9,355,690 B1).
Regarding claim 18, Paksoy and Parker disclose the invention substantially as claimed. See the discussion of claim 17 above.
Paksoy discloses a processor for computing modulo polynomial multiplication [“We implement this algorithm on the ARM Cortex-M4” 3.5 Implementation Results; “The product c(x)…of the polynomials a(x) and b(x) in R can be calculated by reducing c′(x) modulo xn ± 1” 2.2 Polynomial Multiplication Modulo xn ± 1 via TMVP]
However, Paksoy does not explicitly disclose:
a first delay circuit configured to delay the first series of coefficients by one clock cycle to form a delayed series of coefficients;
a second delay circuit configured to delay a first coefficient in the second series of coefficients by a number of clock cycles equal to the number of coefficients in the second series of coefficients to form a modified series of coefficients; and
an addition unit configured to add coefficients in the delayed series of coefficients to coefficients in the modified series of coefficients.
In the analogous art of Polynomial Multiplication implementations, Parker teaches a first polynomial multiplier configured to produce a first product of a first portion of a first polynomial and a first portion of a second polynomial, the first product produced as a first series of coefficients with a separate coefficient at each of a set of clock cycles; and a second polynomial multiplier configured to produce a second product of a second portion of the first polynomial and a second portion of the second polynomial, the second product produced as a second series of coefficients with a separate coefficient at each of the set of clock cycles [Figure 5, items H0’ and H1’ respectively; “the product terms in the polynomial formulation of the parallel FIR filter are equivalent to filtering operations” 3.1 An Introduction of Fast FIR algorithms; "If a L-parallel filter is operated at the same clock rate as the original filter, L output samples are generated every clock cycle…" 2. Parallel Processing for High-Speed or Low-Power; “The 4-parallel structure shown in Fig. 5 can be thought of as 3 separate (2-by-2) FFAs each producing 2 outputs which are combined to produce the 4 filter outputs.” 3.4. Cascading Fast FIR Algorithms];
a second delay circuit configured to delay the second series of coefficients to form a modified series of coefficients[Figure 5, shows an delay for H1’ for the output y(4k)].; and
an addition unit configured to add coefficients in the delayed series of coefficients to coefficients in the modified series of coefficients[Figure 5, shows an addition unit for H0’ and H1’].
It would have been obvious to one of ordinary skill in the art, having the teachings of Paksoy and Parker before him before the effective filing date of the claimed invention to modify the processor for modulo polynomial multiplication as disclosed by Paksoy to use the polynomial multiplication decomposition with the FIR parallel structure as taught by Parker, in order to, implement a structure and technique to increase throughput or decrease the power consumption for polynomial multiplication [Parker: 3.1. An Introduction to Fast FIR Algorithms].
However, Paksoy and Parker does not explicitly disclose a first delay circuit configured to delay the first series of coefficients by one clock cycle to form a delayed series of coefficients; and a second delay circuit configured to delay a first coefficient in the second series of coefficients by a number of clock cycles equal to the number of coefficients in the second series of coefficients to form a modified series of coefficients;
In the analogous art of data staging and pipelining, Illinois teaches adding intermediate pipeline registers to data paths [“We’ll add intermediate registers to out pipelined datapath” slide 9; "Any data values required in later stages must be propagated through the pipeline registers" slide 11, teaches using pipeline registers which would be a delay].
It would have been obvious to one of ordinary skill in the art, having the teachings of Paksoy, Parker and Illinois before him before the effective filing date of the claimed invention to incorporate the pipelining architecture taught by Illinois into the modulo Polynomial Multiplication FIR parallel structure disclosed by the combination of Paksoy and Parker, to allow for increased utilization of all hardware units, improve throughput, and propagate data to the stage required. The combination of Paksoy, Parker, and Illinois discloses a first delay circuit configured to delay the first series of coefficients by one clock cycle to form a delayed series of coefficients.
However, Paksoy, Parker, and Illinois does not explicitly disclose a second delay circuit configured to delay a first coefficient in the second series of coefficients by a number of clock cycles equal to the number of coefficients in the second series of coefficients to form a modified series of coefficients;
In the analogous art of asynchronous pipelining architecture, Tuan teaches delaying data until it reaches a clock cycle wherein it is used ["by having at least one internal pipeline asynchronous register or buffer, a second operation on a set of data may begin before a first operation on another set of data finishes… After waiting for an initial stage of data to be moved to a next stage, a subsequent set of data may take the place of the initial stage of data, and so on." Col 8, lines 45-57, teaches delaying data until its needed]
It would have been obvious to one of ordinary skill in the art, having the teachings of Paksoy, Parker, Illinois and Tuan before him before the effective filing date of the claimed invention to modify the delays/pipeline registers of the combination of Paksoy, Parker, and Illinois to include asynchronous pipeline registers to ensure using the data at the correct clock cycle, in order to, increase throughput by utilizing the hardware for subsequent data while waiting for the correct clock cycle for the data to be used [Tuan: Col. 8, lines 41-63]. The combination of Paksoy, Parker, Illinois and Tuan discloses a second delay circuit configured to delay a first coefficient in the second series of coefficients by a number of clock cycles equal to the number of coefficients in the second series of coefficients to form a modified series of coefficients;
Regarding claim 19, Paksoy, Parker, Illinois, and Tuan disclose the invention substantially as claimed. See the discussion of claim 18 above.
Paksoy discloses a processor for computing modulo polynomial multiplication [“We implement this algorithm on the ARM Cortex-M4” 3.5 Implementation Results; “The product c(x)…of the polynomials a(x) and b(x) in R can be calculated by reducing c′(x) modulo xn ± 1” 2.2 Polynomial Multiplication Modulo xn ± 1 via TMVP]
However, Paksoy does not explicitly disclose:
a third delay circuit configured to delay the third series of coefficients by one clock signal to form a second delayed series of coefficients; a fourth delay circuit configured to delay a first coefficient in the fourth series of coefficients by a number of clock cycles equal to the number of coefficients in the fourth series of coefficients to form a second modified series of coefficients; and a second addition unit for adding coefficients in the second delayed series of coefficients to coefficients in the second modified series of coefficients.
In the analogous art of Polynomial Multiplication implementations, Parker further teaches:
a third polynomial multiplier configured to produce a third product of a first sub-polynomial of the first portion of the first polynomial and a first sub- polynomial of the first portion of the second polynomial, the third product produced as a third series of coefficients with a separate coefficient at each of a set of clock cycles; and a fourth polynomial multiplier configured to produce a fourth modular product of a second sub-polynomial of the first portion of the first polynomial and a second sub-polynomial of the first portion of the second polynomial, the fourth product produced as a fourth series of coefficients with a separate coefficient at each of the set of clock cycles; [Figure 5, item H0’ which is broken into H0 and H1 respectively; “the product terms in the polynomial formulation of the parallel FIR filter are equivalent to filtering operations” 3.1 An Introduction of Fast FIR algorithms; "If a L-parallel filter is operated at the same clock rate as the original filter, L output samples are generated every clock cycle…" 2. Parallel Processing for High-Speed or Low-Power; “The 4-parallel structure shown in Fig. 5 can be thought of as 3 separate (2-by-2) FFAs each producing 2 outputs which are combined to produce the 4 filter outputs.” 3.4. Cascading Fast FIR Algorithms];
a fourth delay circuit configured to delay the fourth series of coefficients to form a second modified series of coefficients [Figure 5, shows an delay for H0’ for H1].; and
a second addition unit configured to the second delayed series of coefficients to coefficients in the second modified series of coefficients [Figure 5, shows an addition unit for H0’ for H0 and H1].
It would have been obvious to one of ordinary skill in the art, having the teachings of Paksoy and Parker before him before the effective filing date of the claimed invention to modify the processor for modulo polynomial multiplication as disclosed by Paksoy to use the polynomial multiplication decomposition with the FIR parallel structure as taught by Parker, in order to, implement a structure and technique to increase throughput or decrease the power consumption for polynomial multiplication [Parker: 3.1. An Introduction to Fast FIR Algorithms].
However, Paksoy and Parker does not explicitly disclose a third delay circuit configured to delay the third series of coefficients by one clock signal to form a second delayed series of coefficients; and a fourth delay circuit configured to delay a first coefficient in the fourth series of coefficients by a number of clock cycles equal to the number of coefficients in the fourth series of coefficients to form a second modified series of coefficients;
In the analogous art of data staging and pipelining, Illinois teaches adding intermediate pipeline registers to data paths [“We’ll add intermediate registers to out pipelined datapath” slide 9; "Any data values required in later stages must be propagated through the pipeline registers" slide 11, teaches using pipeline registers which would be a delay].
It would have been obvious to one of ordinary skill in the art, having the teachings of Paksoy, Parker and Illinois before him before the effective filing date of the claimed invention to incorporate the pipelining architecture taught by Illinois into the modulo Polynomial Multiplication FIR parallel structure disclosed by the combination of Paksoy and Parker, to allow for increased utilization of all hardware units, improve throughput, and propagate data to the stage required. The combination of Paksoy, Parker, and Illinois discloses a third delay circuit configured to delay the third series of coefficients by one clock signal to form a second delayed series of coefficients;
However, Paksoy, Parker, and Illinois does not explicitly disclose a fourth delay circuit configured to delay a first coefficient in the fourth series of coefficients by a number of clock cycles equal to the number of coefficients in the fourth series of coefficients to form a second modified series of coefficients;
In the analogous art of asynchronous pipelining architecture, Tuan teaches delaying data until it reaches a clock cycle wherein it is used ["by having at least one internal pipeline asynchronous register or buffer, a second operation on a set of data may begin before a first operation on another set of data finishes… After waiting for an initial stage of data to be moved to a next stage, a subsequent set of data may take the place of the initial stage of data, and so on." Col 8, lines 45-57, teaches delaying data until its needed].
It would have been obvious to one of ordinary skill in the art, having the teachings of Paksoy, Parker, Illinois and Tuan before him before the effective filing date of the claimed invention to modify the delays/pipeline registers of the combination of Paksoy, Parker, and Illinois to include asynchronous pipeline registers to ensure using the data at the correct clock cycle, in order to, increase throughput by utilizing the hardware for subsequent data while waiting for the correct clock cycle for the data to be used [Tuan: Col. 8, lines 41-63]. The combination of Paksoy, Parker, Illinois and Tuan discloses a fourth delay circuit configured to delay a first coefficient in the fourth series of coefficients by a number of clock cycles equal to the number of coefficients in the fourth series of coefficients to form a second modified series of coefficients.
Claim 20 are rejected under 35 U.S.C. 103 as being unpatentable over Paksoy, Parker, and further in view of Wezelenburg (US 2007/0028076 A1), and further in view of Ghosh et al. (US 2023/0091951 A1), hereinafter Ghosh.
Regarding claim 20, Paksoy and Parker disclose the invention substantially as claimed. See the discussion of claim 17 above.
Paksoy discloses:
split formulas and decompositions can be derived from any polynomial multiplication algorithms [“different split formulas for TMVPs can be derived from any given polynomial multiplication algorithm” Sec.2.1]
a processor for computing modulo polynomial multiplication using arithmetic operations with modulo [“We implement this algorithm on the ARM Cortex-M4” 3.5 Implementation Results; “The product c(x)…of the polynomials a(x) and b(x) in R can be calculated by reducing c′(x) modulo xn ± 1… arithmetic operations include reduction modulo q” 2.2 Polynomial Multiplication Modulo xn ± 1 via TMVP]
However, Paksoy does not explicitly disclose:
Wherein the first sub-circuit comprises:
a plurality of processing elements, each processing element comprising:
a multiplication unit with a first input, a second input and an output, wherein with each of a series of clock cycles, the output of the multiplication unit carries the product of a value provided on the first input and a value provided on the second input;
an addition unit having a first input, a second input and an output wherein the first input is connected to the output of the multiplication unit,; and
a delay unit that has an input connected to the output of the addition unit and an output, wherein the input carries an input value and the output provides the input value delayed by one clock cycle;
wherein the first input of the multiplication unit of each processing element carries a respective coefficient of the first sub-sub-polynomial of the first sub-polynomial of the first polynomial; and
wherein the second input of the multiplication unit of each processing element is connected to one of an input line carrying a sequence of coefficients of the first sub-sub-polynomial of the first sub-polynomial of the second polynomial and a delay line carrying the sequence of coefficients of the first sub-sub-polynomial of the first sub-polynomial of the second polynomial negated and delayed by a number of clock cycles equal to a number of coefficients in the first sub-sub-polynomial of the first sub-polynomial of the second polynomial..
In the analogous art of Polynomial Multiplication implementations, Parker teaches:
a plurality of processing elements, each processing element comprising [Figure 7, pp 86, wherein they show that it consists of a repeating set of a multiplier, adder, and a respective pipeline delay]:
a multiplication unit with a first input, a second input and an output, wherein with each of a series of clock cycles, the output of the multiplication unit carries the product of a value provided on the first input and a value provided on the second input [Figure 7, wherein they show multipliers taking as input x(n) and CN-k wherein k = 1…N];
an addition unit having a first input, a second input and an output wherein the first input is connected to the output of the multiplication unit [Figure 7, wherein they show adders with an input connected to the respective multiplier]; and
a delay unit that has an input connected to the output of the addition unit and an output, wherein the input carries an input value and the output provides the input value delayed by one clock cycle [Figure 7, wherein they show a delay that takes in an input from the adder];
wherein the first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial; and wherein the second input of the multiplication unit of each processing element is connected to one of an input line carrying a sequence of coefficients of a second polynomial having n coefficients [Figure 7, wherein they show a multiplier takes x(n) and CN-k; "two polynomials of degree L-1 can be multiplied using only (2L-1) product terms... The product terms in polynomial formulation of the parallel FIR filter are equivalent to filtering operations, this implies that the parallel FIR filter can be realized using approximately (2L-1) FIR filters of length-N/L" 3.1. An Introduction to Fast FIR algorithms; "the FIR filter sections that are found in the parallel filtering structure... the FIR filter sections must be implemented using a transposed direct-form Structure" 5.3. Sub-Structure Sharing, shows that Figure 7 is the H0/H1 elements in Figure 5 which implements the polynomial multiplication of H0’].
It would have been obvious to one of ordinary skill in the art, having the teachings of Paksoy and Parker before him before the effective filing date of the claimed invention to modify the processor for modulo polynomial multiplication as disclosed by Paksoy to use the polynomial multiplication decomposition with the FIR parallel structure as taught by Parker, in order to, implement a structure and technique to increase throughput or decrease the power consumption for polynomial multiplication [Parker: 3.1. An Introduction to Fast FIR Algorithms].
However, Paksoy and Parker does not explicitly disclose a delay line carrying the sequence of coefficients of the second polynomial delayed by n clock cycles and negated.
In the analogous art of modulo polynomial multiplication implementations, Wezelenburg teaches the input to the multiplier is connected to one of an input line and a negate line [Figure 10, Shows the input a1 going into the mux 1052 (input line) and the negate 1030. The negate 1030 is also connected to mux 1052 (negate line) prior the multiplier 1012. Effectively providing the modulo value by using the negate 1030]
It would have been obvious to one of ordinary skill in the art, to look for a preprocessing step for the input to implement the polynomial multiplication modulo xn ± 1 as disclosed by Paksoy, wherein the modulo effect is negating the input values [Paksoy: Section 2.2]. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Paksoy, Parker and Wezelenburg before him before the effective filing date of the claimed invention to modify the input stage prior to the multipliers of the combination of Paksoy and Parker to incorporate the input negation for Nega-cyclic Toeplitz matrices taught by Wezelenburg, to allow for processing the correct inputs with improved efficiency and overhead for polynomial product modulo ZN+1 for Toeplitz matrix implementations [Wezelenburg: Paragraphs 16-21, 29-32, and 127].
However, Paksoy, Parker, and Wezelenburg does not explicitly disclose a delay line carrying the sequence of coefficients of the second polynomial delayed by n clock cycles.
In the analogous art of modulo polynomial multiplication implementations, Ghosh teaches the sequence of coefficients of the second polynomial delayed by n clock cycles [Figure 3, teaches broadcasting inputs bi and then delaying them by pushing it to the end of the queue to be reused].
Given the need to reuse the same value twice as disclosed by Paksoy it would have been obvious to one of ordinary skill in the art, to seek an implementation to cycle through each value twice [Paksoy: Section 2.2]. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Paksoy, Parker, Wezelenburg and Ghosh before him before the effective filing date of the claimed invention to implement the input method and design into the processor, as disclosed by the combination of Paksoy, Parker and Wezelenburg, by incorporating the input method for the modulo polynomial multiplier design as taught by Ghosh, to allow for an iteratively provided input design that reduces the number of multiplications and providing multiplication and modulus reduction in a single clock cycle [Ghosh: Paragraphs 21, 25, and 29]. The combination of Paksoy, Parker, Wezelenburg and Ghosh discloses a delay line carrying the sequence of coefficients of the second polynomial delayed by n clock cycles and negated.
Response to Arguments
Applicant’s arguments, see page 11, filed 02/26/2026, with respect to Claim rejection under 35 U.S.C. 112(b) have been fully considered and are persuasive. The rejection under 35 U.S.C. 112(b) of the Office Action mailed 12/29/2025 has been withdrawn.
Applicant's arguments, see page 11-20, filed 02/26/2026, with respect to Rejections under 35 U.S.C. 101 have been fully considered but they are not persuasive.
On p.11-12 based on Final Office Action (hereinafter FOA), Section 29, First Paragraph: Applicant argues the claims does not recite a mathematical concept, although both of the identified elements involve the multiplication of two polynomial coefficients, neither element recites multiplying two polynomial coefficients. However the applicant has not fully argued the two considerations for Mathematical Calculations. See MPEP 2106.04(a)(2)(1)(c) i.e. "a step of "determining" a variable or number using mathematical methods or "performing" a mathematical operation may also be considered mathematical calculations when the broadest reasonable interpretation of the claim in light of the specification encompasses a mathematical calculation".
On p.12, FOA, Sec.29, 2nd par.: Applicant argues the arrangement of the units form a particular machine, however, the arrangement has been considered and the interconnection of the elements are a consequence of the applying the mathematical concept as shown in specification paragraphs 17 and 21-23 and as shown in figure 1. See Office Action (hereinafter OA) mailed 12/29/2025, p.5, "the additional elements do not, individually or in combination, integrate the exception into a practical application".
On p.12-13, FOA, Sec.29, 3rd par.: Applicant argues the claim is directed to a particular machine for perform steps that are part of determining the modular polynomial multiplication, however this is directed to an improvement in the mathematics, wherein the improvement in technology cannot come from the math. See MPEP 2106.05(a) "the judicial exception alone cannot provide the improvement".
On p.13-14, FOA, Sec.29, 4th par.: Applicant argues the claim reflects the improvement as described in the specification, however, the arguments are directed to features not claimed (i.e. the 4-parallel architecture in view of the examples given by the applicant), and the use of the mathematical concept in terms of steps. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Performing mathematical operations in steps (i.e. clock cycles) is merely math broken into a time sequence of mathematical steps to compute the mathematical operation which falls under mathematical concepts, such as mathematical relationships and/or calculations. As such, the improvement is a consequence of the mathematical concept. See MPEP 2106.04(a)(2)(I) and 2106.05(a).
On p.14-17, FOA, Sec.30, 1st par.: Applicant argues timing of the coefficients is a control concept which are not abstract ideas. However, the use of the mathematical concept in terms of steps to compute the mathematical concept, is merely performing mathematical operations in steps (i.e. clock cycles). The math is broken into a time sequence of mathematical steps to compute the mathematical operation which falls under mathematical concepts, such as mathematical relationships and/or calculations. As such, the improvement is a consequence of the mathematical concept. See MPEP 2106.04(a)(2)(I) and 2106.05(a).
On p.17, FOA, Sec.30, 2nd par.: Applicant argues none of the math formulas require a delay unit, However, the use of the mathematical concept in terms of steps to compute the mathematical concept, is merely performing mathematical operations in steps (i.e. clock cycles), and see at least specification eq. 21 and fig. 4, and see MPEP 2106.04(a)(2)(I) and 2106.05(a).
On p.17-19, FOA, Sec.30, 3rd & 4th par.: Applicant argues particular timing controls and particular machine. See responses above towards the use of delay units and steps (i.e. clock cycles) and particular machine.
On p.19-20, FOA, Sec.31, 1st par.: Applicant arguments are directed to the layout of the architecture provides the improvement, However, it is merely generic circuit applying the mathematical concepts for decomposing the polynomial multiplication and computing it. wherein the claim merely recites 2 circuit used for producing modular polynomial multiplications. As such, the improvement is a consequence of the mathematical concept. See MPEP 2106.05(a). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant's arguments, see page 20-22, filed 02/26/2026, with respect to Rejections under 35 U.S.C. 103 have been fully considered but they are not persuasive.
On p.21, 1st argument: Applicant argues the two references are mutually exclusive techniques for performing polynomial multiplication, wherein Paksoy teaches a 2-way decomposition and Parker teaches a 3/4-way decomposition, However, Paksoy merely discloses an example of a 2-way decomposition (sec.2.1), and also states "different split formulas for TMVPs can be derived from any given polynomial multiplication algorithm" [p.6, Sec.2.1, last par.]. Parker further discloses a various decompositions i.e. a 3-way decomposition [i.e. figure 5, 3]. It would be obvious to one of ordinary skill in the art, to modify Paksoy to use the 3/4-way decomposition by Parker, to reduce multiplications required and implement the structure for the 3/4-way decomposition by parker [sec.3.1].
On p.21, 2nd argument: Applicant argues parker would destroy the modular nature of Paksoy, however the modification of Paksoy with Parker does not teach away the use of modular arithmetic of Paksoy. As argued above for the 3-way decomposition and with Paksoy's arithmetic operations that include reduction modulo, it would not teach away the modular multiplication provided by Paksoy. See Paksoy Sec.2.2 and see MPEP 2145(X)(D)(1), "the prior art's mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed".
On p.21, 3rd argument: Applicant argues Parker nor Paksoy teaches modular polynomial multiplication of sub-polynomials of two polynomials. However, the applicant is not arguing the rejection as made and is arguing the references individually not in combination. See rejection under 35 U.S.C. 103 above.
Conclusion
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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