Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
This Office Action is responsive to Applicants' Amendment filed on July 22, 2026, in which claims 1, 5, 8, 11, and 15 are currently amended. Claim 21 is newly added. Claims 1, 4, 5, 8-11, and 14-21 are currently pending.
Response to Arguments
The previous rejections to claims 1, 5, 11, and 15 under 35 U.S.C. § 112(b) are hereby withdrawn, as necessitated by applicant's amendments and remarks made to the rejections.
Applicant’s arguments with respect to rejection of claims 1, 4, 5, 8-11, and 14-21 under 35 U.S.C. 103 based on amendment have been considered and are persuasive. The argument is moot in view of a new ground of rejection set forth below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 21, "two second-order subgraphs that are obtained by tiling the depth subgraph by separately using an output of each of the at least one reference vertex as a tiling point" is grammatically indefinite. The "by" modifiers in the sentence are ambiguous such that it's unclear whether (a) each reference vertex is used as a tiling point to produce two second-order subgraphs for that reference vertex, after which their depth difference is calculated, or (b) the two second-order subgraphs are produced using outputs of different reference vertices. Since these interpretations are contradictory one of ordinary skill in the art could not reasonably determine the scope of the claim. In the interest of further examination the claim is interpreted as "the two second-order subgraphs are produced using outputs of different reference vertices."
Regarding claim 21, "the output of the intermediate vertex that is in the at least one reference vertex" is indefinite. The claim suggests that an intermediate vertex is somehow inside a reference vertex. It's unclear if the claim is meant to say that the intermediate vertex is one of the reference vertices or that it corresponds/is based on a reference vertex. In the interest of further examination the claim is interpreted as the intermediate vertex is based on at least one reference vertex.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 5, 8-11, and 14-21 are rejected under U.S.C. §103 as being unpatentable over the combination of Ma (“NeuGraph: Parallel Deep Neural Network Computation on Large Graphs”, 2019) as reinforced by Nvidia (“CUDA C BEST PRACTICES GUIDE”, 2018).
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Regarding claim 1, Ma teaches A neural network tiling method by a processor to reduce or eliminate access to external memory while performing processing operations, comprising: ([p. 446] "NeuGraph consists of: […] 2) a streaming scheduler that minimizes data movement across the host and GPU memory and maximizes its overlap with computation")
generating, by the processor, a neural network graph, wherein the neural network graph represents a neural network deployed in the processor,([p. 446] "translates GNN expressed by the SAGA-NN model into a dataflow graph […] to enable GNN computation over large graphs in GPUs" GNN dataflow graph interpreted as a neural network graph)
the neural network graph comprises a plurality of vertices, and each vertex represents a calculation unit in the neural network; and([p. 4] "Let hu denote the feature vector of a vertex u at layer , and W,WH, and WC be the weight parameters to learn. G-GCN recursively defines the feature of a vertex u")
tiling, by the processor, the neural network graph to obtain a depth subgraph, wherein the depth subgraph represents a depth subnetwork, ([p. 444] "The graph-aware dataflow engine in NeuGraph judiciously partitions the graph data (vertex and edge data) into chunks (subgraphs)" [p. 447] "NeuGraph translates a dataflow subgraph for each destination vertex interval" Chunk interpreted as depth subgraph)
wherein a plurality of vertices comprised in the processor exchange data with each other by reading and writing an on-chip buffer,([p. 444] "each vertex collects its neighbor vertices’ feature vectors along edges" [p. 445] "At each layer, the vertex or edge features are transformed and propagated along edges, and then aggregated at the target vertices to produce new features for the next layer" [p. 450] "Scatter-ApplyEdge-Gather (SAG) stage fusion as another kernel optimization on execution of the propagation procedures [...] we can optimize SAG stages by allowing the vertex/edge data to be directly updated with element-wise operations in GPU registers and then written back to their destination vertices in a single pass [...] using the compressed sparse row (CSR) format for back propagation computation" Propagation/back-propagation interpreted as exchanging data between vertices. GPU register interpreted as on-chip buffer)
the processor is configured to cause the depth subgraph to successively process at least two groups of data obtained by tiling first input data, to obtain first output data, the first input data is input data of the depth subnetwork,([p. 447] "NeuGraph can process edge chunks one by one, with only the source and destination vertex chunks needed for the edge chunk being processed […] NeuGraph therefore adopts a column-oriented approach as illustrated in Figure 5, where it continuously executes operators in the Scatter-ApplyEdge-Gather (SAG) stages for V0 and V1 to produce A0, which is subsequentially consumed by operators in the ApplyVertex stage" A0 interpreted as first output data)
and the first input data comprises one or more signals that can be processed by a computer, ([p. 444] "each vertex in the graph has a feature vector" [p. 445] "each vertex or edge in the graph can be associated with a set of tensor data (normally a vector) as its feature or embedding.")
wherein when a quantity of vertices comprised in the depth subgraph is not less than a first threshold, ([p. 447] "determining the number of vertex chunks P […] NeuGraph selects P as the minimum integer to fit each chunk in GPU memory" P interpreted as first threshold. Ma's vertex chunks are equal sized and P controls how many vertices occupy each chunk.)
tiling the depth subgraph to obtain a first second-order subgraph and a second second- order subgraph, wherein the first second-order subgraph is used to represent a first second-order subnetwork, the second second-order subgraph is used to represent a second second-order subnetwork, both the first second-order subnetwork and the second second-order subnetwork are comprised in the depth subnetwork, ([p. 448] "we apply the second-level partitioning over the edge grid to improve streaming efficiency without increasing the total I/O amount. Specifically, we horizontally partition an edge chunk and its associated source vertex chunk into k (k ≥ 2) fine-grained sub-chunks, which enables parallel streaming processing of k sub-chunks" Horizontally partitioned edge chunks interpreted as first and second second order subgraphs)
and vertices comprised in the first second-order subnetwork are all different from vertices comprised in the second second-order subnetwork, ([p. 446] "it slices vertex data into P equally-sized disjoint vertex chunks")
wherein output data of the first second-order subnetwork is stored into a middle buffer, ([p. 447] "The destination vertex chunk and the corresponding accumulated vertex data chunk (e.g., A0 in the figure) can be reused in GPU memory" [p. 450] "in GPU registers and then written back to their destination vertices in a single pass, without any extra cost of creating intermediate edge data in the GPU global memory" GPU global memory interpreted as middle buffer)
and the second second-order subnetwork reads the output data from the middle buffer, ([p. 447] "it continuously executes operators in the Scatter-ApplyEdge-Gather (SAG) stages for V0 and V1 to produce A0, which is subsequentially consumed by operators in the ApplyVertex stage" This supplies an explicit producer consumer relationship across a subgraph boundary where earlier layer computations produce A0, A0 resides/is reused in GPU memory, and subsequent ApplyVertex computation consumes it)
wherein the tiling the depth subgraph to obtain the first second-order subgraph and the second second-order subgraph comprises: determining at least one reference vertex that is in the plurality of vertices comprised in the depth subgraph ([p. 7] "NeuGraph applies a filter in CPU to select the useful vertices from E’s source vertex chunk, and only transfers the selected vertex data into GPU.")
and whose output data needs to occupy storage space smaller than available storage space of the middle buffer; ([p. 447] "NeuGraph generates a dataflow graph with operators on data chunks, each of which fits in GPU memory, as illustrated in Figure 5" [p. 448] "If this requirement is beyond GPU’s capacity, NeuGraph shrinks the chunk size by increasing P." See also FIG. 6 which shows multiple chunks in GPU memory. Neugraph explicitly refuses to retain a chunk size that exceeds that memory, and if the working set does not fit it shrinks the chunk. Ma simultaneously maintains multiple positive-sized objects in GPU memory, the destination chunk, the accumulation data, operators/parameters, etc. Consequently, the output associated with any one selected vertex must necessarily occupy less than the entire available GPU memory capacity)
and tiling the depth subgraph by using an output of an intermediate vertex in the at least one reference vertex as a tiling point to obtain the first second-order subgraph and the second second-order subgraph, wherein the intermediate vertex is any reference vertex in the at least one reference vertex, ([p. 445] "SAGA NN splits the feed-forward computation into four stages: Scatter, ApplyEdge, Gather, and ApplyVertex, as illustrated in Figure 2." FIG. 5 places A0 between SAG and ApplyVertex with A0 subsequently consumed by the latter. Ma therefore has explicit internal computational boundaries defined by intermediate outputs. Gather produces the accumulated intermediate A0, ApplyVertex is downstream of that intermediate. That is a natural dataflow tiling/cut point)
and output data of the intermediate vertex is output data of the first second-order subgraph and is input data of the second second-order subgraph([p. 447] "it continuously executes operators in the Scatter-ApplyEdge-Gather (SAG) stages for V0 and V1 to produce A0, which is subsequentially consumed by operators in the ApplyVertex stage" [p. 445] "At each layer, the vertex or edge features are transformed and propagated along edges, and then aggregated at the target vertices to produce new features for the next layer").
While Ma explicitly discloses a multi-GPU system with both local and global memory, Ma does not explicitly teach wherein the middle buffer is an off-chip buffer whose reading and writing speed is lower than that of the on-chip buffer, and the reading and writing speed of the middle buffer is faster than that of an external memory;.
Nvidia, in the same field of endeavor, teaches wherein the middle buffer is an off-chip buffer whose reading and writing speed is lower than that of the on-chip buffer, and the reading and writing speed of the middle buffer is faster than that of an external memory; and ([p. 43] "Because it is on-chip, shared memory has much higher bandwidth and lower latency than local and global memory").
Ma as well as Nvidia are directed towards GPU processing. Therefore, Ma as well as Nvidia are reasonably pertinent analogous art. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Ma with the teachings of Nvidia by using the described CUDA setup as Ma’s local and global memory. Ma already establishes an integrated distributed GPU system having GPU registers and global GPU memory in which intermediate accumulation data is reused. Nvidia provides the ordinary physical and performance characteristics of those same exact GPU memory levels. Nvidia provides as additional motivation for combination ([p. 43] "Because it is on-chip, shared memory has much higher bandwidth and lower latency than local and global memory"). This motivation for combination also applies to the remaining claims which depend on this combination.
Regarding claim 4, the combination of Ma, and Nvidia teaches The neural network tiling method according to claim 1, wherein after the tiling the neural network graph to obtain a depth subgraph, the method further comprises: generating, by the processor, a target instruction corresponding to the depth subgraph, wherein the target instruction is used to execute a target subtask,(Ma [p. 447] "it continuously executes operators in the Scatter-ApplyEdge-Gather (SAG) stages for V0 and V1 to produce A0, which is subsequentially consumed by operators in the ApplyVertex stage" [p. 445] "At each layer, the vertex or edge features are transformed and propagated along edges, and then aggregated at the target vertices to produce new features for the next layer" ApplyVertex interpreted as target subtask)
the neural network is configured to execute a target task, and the target subtask is a part of the target task.(Ma [p. 447] "For the forward computation, data flows from the source vertex to the destination vertex. […] it continuously executes operators in the Scatter-ApplyEdge-Gather (SAG) stages for V0 and V1 to produce A0, which is subsequentially consumed by operators in the ApplyVertex stage" Forward computation/propagation interpreted as target task).
Regarding claim 5, Ma teaches A neural network-based prediction method by a processor, comprising: obtaining, by the processor, original input data, wherein the original input data comprises one or more signals that can be processed by the processor;([p. 444] "Each successive layer uses the output from the previous layer as input" [p. 450] "It first loads the inputs of Scatter; i.e., source vertices and edge data […] input and output tensors")
tiling, by the processor a neural network graph that represents a neural network to generate depth subgraphs;([p. 444] "The graph-aware dataflow engine in NeuGraph judiciously partitions the graph data (vertex and edge data) into chunks (subgraphs)" [p. 447] "NeuGraph translates a dataflow subgraph for each destination vertex interval" Chunk interpreted as depth subgraph)
inputting, by the processor, the original input data to a neural network deployed in the processor for prediction processing by the depth subgraphs tiling the input data to obtain a prediction result, ([p. 444] "each vertex collects its neighbor vertices’ feature vectors along edges" [p. 445] "At each layer, the vertex or edge features are transformed and propagated along edges, and then aggregated at the target vertices to produce new features for the next layer" [p. 450] "Scatter-ApplyEdge-Gather (SAG) stage fusion as another kernel optimization on execution of the propagation procedures [...] we can optimize SAG stages by allowing the vertex/edge data to be directly updated with element-wise operations in GPU registers and then written back to their destination vertices in a single pass [...] using the compressed sparse row (CSR) format for back propagation computation" Propagation/back-propagation interpreted as exchanging data between vertices. GPU register interpreted as on-chip buffer)
wherein the prediction processing comprises: successively inputting, to a depth subnetwork for processing, at least two groups of data obtained by tiling first input data, to obtain first output data, the first input data is input data of the depth subnetwork, ([p. 447] "NeuGraph can process edge chunks one by one, with only the source and destination vertex chunks needed for the edge chunk being processed […] NeuGraph therefore adopts a column-oriented approach as illustrated in Figure 5, where it continuously executes operators in the Scatter-ApplyEdge-Gather (SAG) stages for V0 and V1 to produce A0, which is subsequentially consumed by operators in the ApplyVertex stage" A0 interpreted as first output data)
and the first input data comprises one or more signals that can be processed by a computer, ([p. 444] "each vertex in the graph has a feature vector" [p. 445] "each vertex or edge in the graph can be associated with a set of tensor data (normally a vector) as its feature or embedding.")
wherein when a quantity of vertices comprised in a depth subgraph of the depth subgraphs is not less than a first threshold, ([p. 447] "determining the number of vertex chunks P […] NeuGraph selects P as the minimum integer to fit each chunk in GPU memory" P interpreted as first threshold. Ma's vertex chunks are equal sized and P controls how many vertices occupy each chunk.)
tiling the depth subgraph to obtain a first second-order subgraph and a second second-order subgraph, wherein the first second-order subgraph is used to represent a first second-order subnetwork, the second second-order subgraph is used to represent a second second-order subnetwork, both the first second-order subnetwork and the second second-order subnetwork are comprised in the depth subnetwork,([p. 448] "we apply the second-level partitioning over the edge grid to improve streaming efficiency without increasing the total I/O amount. Specifically, we horizontally partition an edge chunk and its associated source vertex chunk into k (k ≥ 2) fine-grained sub-chunks, which enables parallel streaming processing of k sub-chunks" Horizontally partitioned edge chunks interpreted as first and second second order subgraphs)
and vertices comprised in the first second-order subnetwork are all different from vertices comprised in the second second-order subnetwork, ([p. 446] "it slices vertex data into P equally-sized disjoint vertex chunks")
wherein output data of the first second-order subnetwork is stored into a middle buffer, ([p. 447] "The destination vertex chunk and the corresponding accumulated vertex data chunk (e.g., A0 in the figure) can be reused in GPU memory" [p. 450] "in GPU registers and then written back to their destination vertices in a single pass, without any extra cost of creating intermediate edge data in the GPU global memory" GPU global memory interpreted as middle buffer)
and the second second-order subnetwork reads the output data from the middle buffer,([p. 447] "it continuously executes operators in the Scatter-ApplyEdge-Gather (SAG) stages for V0 and V1 to produce A0, which is subsequentially consumed by operators in the ApplyVertex stage" This supplies an explicit producer consumer relationship across a subgraph boundary where earlier layer computations produce A0, A0 resides/is reused in GPU memory, and subsequent ApplyVertex computation consumes it)
wherein the tiling the depth subgraph to obtain the first second-order subgraph and the second second-order subgraph comprises: determining at least one reference vertex that is in the plurality of vertices comprised in the depth subgraph ([p. 7] "NeuGraph applies a filter in CPU to select the useful vertices from E’s source vertex chunk, and only transfers the selected vertex data into GPU.")
and whose output data needs to occupy storage space smaller than available storage space of the middle buffer; ([p. 447] "NeuGraph generates a dataflow graph with operators on data chunks, each of which fits in GPU memory, as illustrated in Figure 5" [p. 448] "If this requirement is beyond GPU’s capacity, NeuGraph shrinks the chunk size by increasing P." See also FIG. 6 which shows multiple chunks in GPU memory. Neugraph explicitly refuses to retain a chunk size that exceeds that memory, and if the working set does not fit it shrinks the chunk. Ma simultaneously maintains multiple positive-sized objects in GPU memory, the destination chunk, the accumulation data, operators/parameters, etc. Consequently, the output associated with any one selected vertex must necessarily occupy less than the entire available GPU memory capacity)
and tiling the depth subgraph by using an output of an intermediate vertex in the at least one reference vertex as a tiling point to obtain the first second-order subgraph and the second second-order subgraph, ([p. 445] "SAGA NN splits the feed-forward computation into four stages: Scatter, ApplyEdge, Gather, and ApplyVertex, as illustrated in Figure 2." FIG. 5 places A0 between SAG and ApplyVertex with A0 subsequently consumed by the latter. Ma therefore has explicit internal computational boundaries defined by intermediate outputs. Gather produces the accumulated intermediate A0, ApplyVertex is downstream of that intermediate. That is a natural dataflow tiling/cut point)
wherein the intermediate vertex is any reference vertex in the at least one reference vertex, and output data of the intermediate vertex is output data of the first second-order subgraph and is input data of the second second-order subgraph.([p. 447] "it continuously executes operators in the Scatter-ApplyEdge-Gather (SAG) stages for V0 and V1 to produce A0, which is subsequentially consumed by operators in the ApplyVertex stage" [p. 445] "At each layer, the vertex or edge features are transformed and propagated along edges, and then aggregated at the target vertices to produce new features for the next layer").
However, Ma does not explicitly teach wherein the middle buffer is an off-chip buffer whose reading and writing speed is lower than that of the on-chip buffer, and the reading and writing speed of the middle buffer is faster than that of an external memory.
Nvidia, in the same field of endeavor, teaches wherein the middle buffer is an off-chip buffer whose reading and writing speed is lower than that of the on-chip buffer, and the reading and writing speed of the middle buffer is faster than that of an external memory.([p. 43] "Because it is on-chip, shared memory has much higher bandwidth and lower latency than local and global memory").
Ma as well as Nvidia are directed towards GPU processing. Therefore, Ma as well as Nvidia are reasonably pertinent analogous art. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Ma with the teachings of Nvidia by using the described CUDA setup as Ma’s local and global memory. Ma already establishes an integrated distributed GPU system having GPU registers and global GPU memory in which intermediate accumulation data is reused. Nvidia provides the ordinary physical and performance characteristics of those same exact GPU memory levels. Nvidia provides as additional motivation for combination ([p. 43] "Because it is on-chip, shared memory has much higher bandwidth and lower latency than local and global memory"). This motivation for combination also applies to the remaining claims which depend on this combination.
Regarding claim 8, the combination of Ma, and Nvidia teaches The method according to claim 5, wherein the prediction processing further comprises: processing, by the processor using a direct subnetwork, second input data as a whole, wherein the direct subnetwork is comprised in the neural network and comprises some vertices in the neural network, and the second input data is obtained in the process of inputting the original input data to the neural network for prediction processing, (Ma [p. 444] "Deep learning, in the form of deep neural networks, is a class of machine learning algorithms that use a cascade of multiple layers of nonlinear processing units for feature extraction and transformation. Each successive layer uses the output from the previous layer as input" [p. 450] "It first loads the inputs of Scatter; i.e., source vertices and edge data […] input and output tensors")
and wherein at least one vertex in the direct subnetwork performs one processing operation in a process of processing the second input data(Ma [p. 447] "it continuously executes operators in the Scatter-ApplyEdge-Gather (SAG) stages for V0 and V1 to produce A0, which is subsequentially consumed by operators in the ApplyVertex stage" [p. 445] "At each layer, the vertex or edge features are transformed and propagated along edges, and then aggregated at the target vertices to produce new features for the next layer" ApplyVertex interpreted as target subtask).
Regarding claim 9, the combination of Ma, and Nvidia teaches The method according to claim 5, wherein storage space required by the first input data is larger than the available storage space of the on-chip buffer, (Ma [p. 7] "If this requirement is beyond GPU’s capacity, NeuGraph shrinks the chunk size by increasing P.")
and storage space required by each of the at least two groups of data is not larger than the available storage space of the on-chip buffer.(Ma [p. 7] "If this requirement is beyond GPU’s capacity, NeuGraph shrinks the chunk size by increasing P.").
Regarding claim 10, the combination of Ma, and Nvidia teaches The method according to claim 5, wherein the prediction processing further comprises: processing, by the processor using a third second-order subnetwork, fourth input data to obtain second intermediate data; (Ma [p. 444] "Deep learning, in the form of deep neural networks, is a class of machine learning algorithms that use a cascade of multiple layers" [p. 446] "it slices vertex data into P equally-sized disjoint vertex chunks" [p. 454] "the training is iterative on batches of samples" [p. 445] "A GNN can consist of multiple layers, with an iterative propagation procedure conducted layer-by layer over the same graph" See FIG. 2 and 4-6. Ma chunks GNN layer by layer, such that second layer chunks are interpreted as third and fourth second-order subnetworks utilizing fourth input data to obtain second intermediate data)
and storing the second intermediate data into a middle buffer, wherein the middle buffer is not the on-chip buffer;(Ma [p. 447] "The destination vertex chunk and the corresponding accumulated vertex data chunk (e.g., A0 in the figure) can be reused in GPU memory" [p. 450] "in GPU registers and then written back to their destination vertices in a single pass, without any extra cost of creating intermediate edge data in the GPU global memory" GPU global memory interpreted as middle buffer)
and processing, by a fourth second-order subnetwork, the second intermediate data obtained from the middle buffer to obtain fourth output data, (Ma [p. 447] "NeuGraph can process edge chunks one by one, with only the source and destination vertex chunks needed for the edge chunk being processed […] NeuGraph therefore adopts a column-oriented approach as illustrated in Figure 5, where it continuously executes operators in the Scatter-ApplyEdge-Gather (SAG) stages for V0 and V1 to produce A0, which is subsequentially consumed by operators in the ApplyVertex stage" A0 interpreted as first output data)
wherein both the third second-order subnetwork and the fourth second-order subnetwork are comprised in the neural network, (Ma [p. 444] "Deep learning, in the form of deep neural networks, is a class of machine learning algorithms that use a cascade of multiple layers")
vertices comprised in the third second-order subnetwork are all different from vertices comprised in the fourth second-order subnetwork, (Ma [p. 446] "it slices vertex data into P equally-sized disjoint vertex chunks")
and the fourth input data is obtained in the process of inputting the original input data to the neural network for prediction processing.(Ma [p. 444] "Deep learning, in the form of deep neural networks, is a class of machine learning algorithms that use a cascade of multiple layers of nonlinear processing units for feature extraction and transformation. Each successive layer uses the output from the previous layer as input" [p. 450] "It first loads the inputs of Scatter; i.e., source vertices and edge data […] input and output tensors").
Regarding claim 11, claim 11 is directed towards an apparatus for performing the method of claim 1. Therefore, the rejection applied to claim 1 also applies to claim 11. Claim 11 recites additional elements A neural network graph tiling apparatus, comprising a memory and a processor, wherein the memory is configured to store code, and the processor is configured to perform the following operations by reading the code stored in the memory: (Ma [p. 444] “NeuGraph can still achieve a up to 5× speedup over the state-of-art implementation on TensorFlow and a up to 19× speedup over DGL [1]. Moreover, NeuGraph achieves nearly linear scalability over multiple GPUs”).
Similarly, regarding claims 14 and 15, claims 14 and 15 are directed towards an apparatus for performing the methods of claims 4 and 5, respectively. Therefore, the rejections applied to claims 4 and 5 also apply to claims 14 and 15.
Regarding claim 16, the combination of Ma, and Nvidia teaches The apparatus according to claim 15, wherein the prediction processing further comprises: processing, by using a direct subnetwork, second input data as a whole, wherein the direct subnetwork is comprised in the neural network and comprises a part of vertices in the neural network, and the second input data is obtained in the process of inputting the original input data to the neural network for prediction processing.(Ma [p. 444] "Deep learning, in the form of deep neural networks, is a class of machine learning algorithms that use a cascade of multiple layers of nonlinear processing units for feature extraction and transformation. Each successive layer uses the output from the previous layer as input" [p. 450] "It first loads the inputs of Scatter; i.e., source vertices and edge data […] input and output tensors").
Regarding claim 17, the combination of Ma, and Nvidia teaches The apparatus according to claim 16, wherein storage space required by the second input data is not larger than available storage space of the on-chip buffer.(Ma [p. 7] "If this requirement is beyond GPU’s capacity, NeuGraph shrinks the chunk size by increasing P.").
Regarding claims 18-20, claims 18-20 are directed towards an apparatus to perform the method of claims 8-10, respectively. Therefore, the rejections applied to claims 8-10 also apply to claims 18-20.
Regarding claim 21, the combination of Ma, and Nvidia teaches The method according to claim 1, wherein before the tiling the depth subgraph by using the output of the intermediate vertex in the at least one reference vertex as the tiling point,(Ma [p. 448] "For each layer, NeuGraph can scale GNN computation be yond the GPU core by processing the dataflow subgraph for a column of edge chunks (illustrated in Figure 5) […] we apply the second-level partitioning over the edge grid")
the method further comprises: obtaining a depth difference between two second-order subgraphs (Ma [p. 448] "different edge sub-chunks could have distinct data transfer and computation cost due to different sparsity levels […] As illustrated in Figure 6, by examining the overlapping result in this simulation, the system finds a sub-chunk whose data transfer time is much shorter than the computation time, and within the same chunk, another sub-chunk is an opposite case")
that are obtained by tiling the depth subgraph by separately using an output of each of the at least one reference vertex as a tiling point, to obtain at least one depth difference, (Ma [p. 448] "we apply the second-level partitioning over the edge grid to improve streaming efficiency without increasing the total I/O amount. Specifically, we horizontally partition an edge chunk and its associated source vertex chunk into k (k ≥ 2) fine-grained sub-chunks, which enables parallel streaming processing of k sub-chunks")
wherein the at least one reference vertex is in a one-to-one correspondence with the at least one depth difference; (Ma [p. 448] "NeuGraph exploits the cyclic pattern inherent in GNNs: Both the computation time and data transfer time of each sub-chunk can be profiled in the first several iterations and used in refining the scheduling plan for processing in the following iterations" Ma's profiling information including the depth difference is individualized to each candidate fine-grained portion)
and determining that the output of the intermediate vertex that is in the at least one reference vertex and that corresponds to a depth difference less than a depth difference threshold is used as the tiling point to tile the depth subgraph.(Ma [p. 448] "For a vertex chunk, if θ < Tcopy Tcopy+Ttrans , NeuGraph chooses to apply filtering as it benefits the overall data transfer efficiency [...] Given a column of edge sub-chunks, the system first generates the initial schedule plan by assigning a random order for processing. Next, it repeatedly swaps the order of a pair sub-chunks such that a better schedule plan with less time can be obtained. This process stops when it converges or reaches maximum iterations. [...] By swapping the order of these two heterogeneous edge sub-chunks, the system enables a better balance between the computation and data transfer." Ma's current/best schedule provides a comparison threshold: the candidate is accepted when its resulting time/difference is less than the existing value).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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