Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Non-Final office is a response to the papers filed on 01/09/2026.
Claims 8-14 are pending, claims 1-7 are cancelled..
Remark
In the Office Action, claims 1-14 were restricted under 35 U.S.C. 121 by a genus- species type restriction. The restriction indicated that Species I and Species II claims respectively fall into the following two groups:
Groups:
I. Group I drawn to claims 1-7 which disclose a synapse array having unit synapse devices formed in regions where a plurality of word line pairs and a plurality of bit lines intersect each other.
II. Group II drawn to claims 8-14 which disclose a cumulative stack portion formed on a substrate; and a through-hole portion formed through the cumulative stack portion.
Applicant’s election without traverse of Group II (claims 8-14) in the reply filed on 01/09/2025 is acknowledged.
Claims 1-7 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/09/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over YUSUKE et AL. (JP 2021106262 A) in view of TOSHIAKI (JP 2004273480 A).
Regarding claim 8, Yusuke discloses:
A unit synapse device (see Fig. 1, 65-67, page 11, paragraph 11, when the memristor 10 is used as a synapse….) comprising:
a cumulative stack portion formed on a substrate (see Fig. 65-67, substrate 1 or 21, stack portion layers 21, 24, and 27 formed on substrate 21); and
a through-hole portion formed through the cumulative stack portion (see Fig. 65-67, through-hole portion 28-1, see page 34, paragraph 4-5, oxide semiconductor layer 27 via the through hole 28-1…..), wherein the through-hole portion has a via oxide layer in contact with the cumulative stack portion (see page 34, paragraph 4-5, oxide semiconductor layer 27 via the through hole 28-1…..), and a learning operation or an inference operation is performed (see pages 11, paragraph 11 to page 12 paragraph 1-3, the synaptic coupling increases (decreases) with respect to the input signal, and learning is completed…., see page 17-18, see page 32, paragraph 11, the function of associative learning can be realized by using the memristor 20….).
Note Yusuke discloses a semiconductor element is used as a synapse and comprising the through hole has a via oxide layer in contact with the cumulative stack portion. However, Yosuke fails to disclose:
a common electrode configured to fill the inside of the via oxide layer.
Toshiaki discloses a semiconductor device using the wiring board which is relate to the semiconductor element.
Thus, Toshiaki discloses:
a common electrode configured to fill the inside of the via oxide layer (see par [0018-0019], the through holes 12 formed in the substrate made of the porous metal oxide film 11, the inside of the through hole 12 where the electrode is formed is filled with the conductive material 13, and the other inside of the through hole 12 is formed….).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified a semiconductor element of Yosuke to include a common electrode configured to fill the inside of the via oxide layer in order for the surface and the back surface of the element can be conducted only in the minimum necessary area where the electrodes are formed (see Toshiaki par [0019]).
Allowable Subject Matter
Claims 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest the limitation as in claim 9.
Conclusion
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/BRIAN NGO/ Primary Examiner, Art Unit 2851