Office Action Predictor
Application No. 17/585,197

BINARY MACHINE LEARNING NETWORK WITH OPERATIONS QUANTIZED TO ONE BIT

Non-Final OA §102
Filed
Jan 26, 2022
Examiner
WONG, LUT
Art Unit
2127
Tech Center
2100 — Computer Architecture & Software
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
3y 6m
To Grant
90%
With Interview

Examiner Intelligence

77%
Career Allow Rate
463 granted / 598 resolved
Without
With
+12.1%
Interview Lift
avg trend
3y 6m
Avg Prosecution
23 pending
621
Total Applications
career history

Statute-Specific Performance

§101
18.7%
-21.3% vs TC avg
§103
32.6%
-7.4% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
11.3%
-28.7% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 8-20 in the reply filed on 9-29-2025 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 8 and 15 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Redfern et al (BCNN: A Binary CNN With All Matrix Ops Quantized To 1 Bit Precision” 1 Oct 2020. Retrieve from https://arxiv.org/pdf/2010.00704v1) 8. A non-transitory program storage device comprising instructions stored thereon to cause one or more processors to (See section 4.1 on imageNet system. Examiner Note: computing system inherently has storage device and processor): receive a machine learning model, the machine learning (ML) model including a set of building blocks wherein layers of the ML model may include one or more building blocks (See section 2.3); PNG media_image1.png 200 400 media_image1.png Greyscale receive a set of input data (See Fig. 2-3); replicate the set of input data (See Fig. 2-3 on replicate Rx and concat); PNG media_image2.png 200 400 media_image2.png Greyscale concatenate the replicated set of input data to the set of input data (See Fig. 2-3 on concat Intensity channel); PNG media_image3.png 200 400 media_image3.png Greyscale normalize the set of input data to generate a set of non-binary input feature values (See Fig. 3 on Batch norm; see section 4.2.2 on non integer value); PNG media_image4.png 200 400 media_image4.png Greyscale input the set of non-binary input feature values to a building block of the one or more building blocks, wherein each building block is configured to: perform a first binary convolution operation based on the set of non-binary input feature values (See Fig. 3 1x1 binary conv on top right); perform a non-binary convolution operation on results of the first binary convolution operation (See Fig. 3 1x1 3x3/S real grp conv); perform a second binary convolution operation on results of the non-binary convolution operation (See Fig. 3 1x1 second binary conv on bottom right); and output a set of non-binary output features based on results of the second binary convolution operation (See Fig. 3 on output). PNG media_image5.png 200 400 media_image5.png Greyscale Claim 15 is drawn to claim 8 and is rejected for the same rationale. Note for An electronic device, comprising: a system on a chip including: one or more processors; and an internal memory; and an external memory, wherein the system on a chip is coupled to the external memory, and wherein instructions stored in the external memory configure the one or more processors to (See Fig.7). Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. del Mundo et al (US 20200410318 A1) disclose binary convolutional neural network optimization and intermediate tensor. See abstract and Fig. 1A-1B. Qin et al (“BIPOINTNET: BINARY NEURAL NETWORK FOR POINT CLOUDS” 2021) disclose binary neural network with intermediate features. See abstract, and A4. Martinez et al (“TRAINING BINARY NEURAL NETWORKS WITH REALTO-BINARY CONVOLUTIONS” 2020) disclose binary neural network with real to binary convolutions. See abstract. Zhao et al (“A Review of Recent Advances of Binary Neural Networks for Edge Computing” 2020) disclose a review of Binary Neural Networks. See abstract. Shi et al (“SURVEY ON BINARY NEURAL NETWORKS” 2019) disclose a survey on binary neural networks. See abstract. Allowable Subject Matter Claims 9-14, 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: While Redfern et al disclose binarization, Redfern fails to disclose all the steps as required in claim 9 and 16. Furthermore, Redfern et al explicitly teach away using intermediate feature map (See section 5.3); thus make it non-obvious to modify the BCNN of Redfern et al to incorporate intermediate feature values as required in claim 9 and 16. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUT WONG whose telephone number is (571)270-1123. The examiner can normally be reached M-F 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Abdullah Al Kawsar can be reached at 5712703169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LUT WONG/Primary Examiner, Art Unit 2127
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Prosecution Timeline

Jan 26, 2022
Application Filed
Oct 21, 2025
Non-Final Rejection — §102
Mar 23, 2026
Response Filed

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
90%
With Interview (+12.1%)
3y 6m
Median Time to Grant
Low
PTA Risk
Based on 598 resolved cases by this examiner