DETAILED ACTION
This communication is in response to the application filed 01/28/22 in which claims 1-20 were presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/28/22 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
Claims 5-7, 12-14, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-11, and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by On (US 2022/0164253 A1; published May 26, 2022).
Regarding claim 1, On [a] method, comprising:
determining, by a quantum computing device, to migrate a quantum process currently executing using a first one or more qubits on the quantum computing device into a first quantum isolation zone (QIZ), wherein the first QIZ limits qubit visibility of any quantum process associated with the first QIZ to a plurality of qubits associated with the first QIZ; and (On ¶ 19 (“In an embodiment, the management device includes a memory that stores a program code for the physical qubit layer, the abstraction qubit layer, the logical qubit layer, and the application qubit layer, a central processing unit that executes the program code stored in the memory, and an interface device that provides communication between the first quantum chip and the second quantum chip.”); On ¶ 21 (“In an embodiment, the operating method further includes receiving a qubit request from a quantum application program, allocating logical qubits, which correspond to the qubit request, from among the plurality of logical qubits based on the logical qubit mapping, allocating abstraction qubits, which correspond to the allocated logical qubits, from among the plurality of abstraction qubits based on the abstraction qubit mapping, allocating physical qubits, which correspond to the allocated abstraction qubits, from among the plurality of physical qubits based on the physical qubit mapping, and performing a calculation corresponding to the qubit request by using the allocated physical qubits.”); On ¶ 67 (“In an embodiment, the abstraction channel between abstraction qubits may be implemented or determined based on the features of quantum chips or physical qubits. For example, in the calculation of physical qubits, the calculation execution time and the coherence time may be different depending on the type of the quantum chip or the physical qubit. In a quantum computing system, the relative calculation time of a physical qubit relative to the coherence time is more important than the absolute calculation time of a physical qubit. Accordingly, the abstraction qubit layer 112 may implement or determine abstraction channels between abstraction qubits based on a ratio of the calculation time of a physical qubit to the coherence time of the physical qubit according to types of quantum chips.”))
responsive to determining to migrate the quantum process: transferring the first one or more qubits to the first QIZ; (On ¶ 91 (“In operation S240, the management device 110 may allocate a physical qubit group corresponding to the allocated abstraction qubit group based on the physical qubit mapping. For example, the abstraction qubit layer 112 of the management device 110 may allocate the physical qubit group corresponding to the allocated abstraction qubit group based on the physical qubit mapping.”))
associating the quantum process with the first QIZ; and (On ¶ 93 (“As described above, according to an embodiment of the present disclosure, the management device 110 may perform a conversion operation through various layers such that the quantum application program recognizes or identifies that quantum chips implemented in different types have the same type. Accordingly, resource utilization of physical qubits may be improved.”))
continuing execution of the quantum process within the first QIZ (On ¶ 92 (“In operation S250, the management device 110 may perform calculations by using physical qubits corresponding to the allocated physical qubit group. For example, the physical qubit layer 111 of the management device 110 may control the plurality of controllers CT1 to CTm such that the calculations are performed based on the physical qubit corresponding to the assigned physical qubit group.”)).
Claim 8 is an apparatus claim corresponding to method claim 1 and, therefore, is similarly rejected. On further discloses [a] quantum computing device comprising: a system memory; and a processor device communicatively coupled to the system memory (On ¶ 19 (“In an embodiment, the management device includes a memory that stores a program code for the physical qubit layer, the abstraction qubit layer, the logical qubit layer, and the application qubit layer, a central processing unit that executes the program code stored in the memory, and an interface device that provides communication between the first quantum chip and the second quantum chip.”)).Claim 15 is a CRM claim corresponding to claim 1 and, therefore, is similarly rejected. On further discloses [a] non-transitory computer-readable medium having stored thereon computer-executable instructions that, when executed, causes one or more processor devices to (On ¶ 19 (“In an embodiment, the management device includes a memory that stores a program code for the physical qubit layer, the abstraction qubit layer, the logical qubit layer, and the application qubit layer, a central processing unit that executes the program code stored in the memory, and an interface device that provides communication between the first quantum chip and the second quantum chip.”)).
Regarding claim 2, On discloses the invention of claim 1 as discussed above. On further discloses wherein:
determining to migrate the quantum process into the first QIZ comprises determining that an attribute of the quantum process has exceeded a migration threshold; and (On ¶ 71 (“In an embodiment, the abstraction qubit layer 112 may be configured to manage physical qubit resources. For example, the abstraction qubit layer 112 may measure the fidelity of the physical qubit periodically or randomly, and then may exclude a physical qubit having fidelity of the reference value or less. In an embodiment, the excluded physical qubit may not be used as an abstraction qubit or may not correspond to an abstraction qubit. Alternatively, the abstraction qubit layer 112 may correspond or map physical qubits having fidelity of a reference value or more to abstraction qubits.”))
the attribute comprises a response time of the quantum process, an execution time of the quantum process, a noise tolerance of the quantum process, or a contention tolerance of the quantum process (On ¶ 81 (“For example, in a conventional quantum computing system, when types of quantum chips are different from one another, different quantum application programs are required due to different physical features. In addition, physical qubits may not be efficiently allocated due to the limitation of the physical connection between physical qubits. In an embodiment, the physical features of quantum chips or physical qubits may include at least one of a coherence time, an error rate, a gate calculation time, connectivity between qubits, and a quantum information communication execution time between qubits.”)).
Claim 9 is an apparatus claim corresponding to claim 2 and, therefore, is similarly rejected.
Regarding claim 3, On discloses the invention of claim 1 as discussed above. On further discloses wherein transferring the first one or more qubits to the first QIZ comprises associating the first one or more qubits with the first QIZ (On ¶ 90 (“In operation S230, the management device 110 may allocate an abstraction qubit group corresponding to the allocated logical qubit group based on the abstraction qubit mapping. For example, the logical qubit layer 113 of the management device 110 may allocate the abstraction qubit group corresponding to the allocated logical qubit group based on the abstraction qubit mapping.”)).
Claim 10 is an apparatus claim corresponding to claim 3 and, therefore, is similarly rejected. Claim 16 is a CRM claim corresponding to claim 3 and, therefore, is similarly rejected.
Regarding claim 4, On discloses the invention of claim 3 as discussed above. On further discloses wherein associating the first one or more qubits with the first QIZ comprises modifying qubit metadata for the first one or more qubits to indicate that each qubit of the first one or more qubits is associated with the first QIZ (On ¶ 63 (“The abstraction qubit mapping may include information about abstraction qubits and abstraction channels between the abstraction qubits.”); On ¶ 64 (“The plurality of abstraction qubits AQ1a to AQ1t and AQ2a to AQ2t may have a mapping relationship with the plurality of physical qubits PQ1a to PQ1t and PQ2a to PQ2t in various manners such as one-to-one mapping, many-to-one mapping, and many-to-many mapping, based on physical features of the quantum chips QC11 and QC21, physical features of physical qubits, and the like.”)).
Claim 11 is an apparatus claim corresponding to claim 4 and, therefore, is similarly rejected. Claim 17 is a CRM claim corresponding to claim 4 and, therefore, is similarly rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zeng et al. (US 10,325,218 B1) Constructing Quantum Process for Quantum Processors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHID KHAN whose telephone number is (571)270-0419. The examiner can normally be reached M-F, 9-5 est.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571)270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAHID K KHAN/ Primary Examiner, Art Unit 2146