Prosecution Insights
Last updated: July 17, 2026
Application No. 17/588,729

DISPLAY PANEL AND DISPLAY DEVICE

Non-Final OA §102§103§112
Filed
Jan 31, 2022
Priority
Feb 26, 2020 — CN 202010121624.4 +1 more
Examiner
NGUYEN, SOPHIA T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kunshan Go-visionox Opto-electronics Co., Ltd.
OA Round
4 (Non-Final)
45%
Grant Probability
Moderate
4-5
OA Rounds
0m
Est. Remaining
58%
With Interview

Examiner Intelligence

Grants 45% of resolved cases
45%
Career Allowance Rate
233 granted / 519 resolved
-23.1% vs TC avg
Moderate +14% lift
Without
With
+13.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
58 currently pending
Career history
606
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
89.9%
+49.9% vs TC avg
§102
3.2%
-36.8% vs TC avg
§112
6.1%
-33.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 519 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s amendment dated 10/02/2025, in which claims 1, 15, 22, 24, 28 were amended, claims 3, 8, 11-14, 17-20, 26 were cancelled, claims 21, 25, 27, 30 were withdrawn, claim 31 was added, has been entered. Specification The amendment filed 10/02/2025 has been entered. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application CN202010121624.4 filed on 02/26/2020. The foreign application is not in English. The certified copy of the foreign priority application CN202010121624.4 has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority Date Applicant has not yet complied with one or more conditions to actually be entitled to benefit of an earlier filing date under 35 U.S.C. 119(a)-(d). To be entitled to the filing date of the foreign priority application CN202010121624.4 that is not in English, an English translation of the non-English language foreign application CN202010121624.4 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 22 and 28-29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 22, claim 22 recites “the first driving circuit comprises: an active layer, a gate dielectric layer, a gate electrode layer located on the gate dielectric layer, a first capacitor conductive layer located on the gate dielectric layer, a gate structure.” It is unclear which element is “a gate structure”. It is unclear if “a gate structure” is the same or different from a gate structure formed of a gate dielectric layer, a gate electrode layer. It is unclear whether Applicant attempt to claim an invention having two gate structures which is distinct from the elected invention shown in Fig. 4 which has only one gate structure. For the purpose of this Action the above limitation of claim 22 will be interpreted and examined as --the first driving circuit comprises: an active layer, a gate structure comprising a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, a first capacitor conductive layer located on the gate dielectric layer.— Regarding claim 28, claim 28 recites “the first driving circuit comprises: an active layer, a gate dielectric layer, a gate electrode layer located on the gate dielectric layer, a first capacitor conductive layer located on the gate dielectric layer, a gate structure.” It is unclear which element is “a gate structure”. It is unclear if “a gate structure” is the same or different from a gate structure formed of a gate dielectric layer, a gate electrode layer. It is unclear whether Applicant attempt to claim an invention having two gate structures which is distinct from the elected invention shown in Fig. 4 which has only one gate structure. Claim 28 further recites “a first region having a plurality of first light-emitting units” and “a plurality of first light-emitting units in the first region.” It is unclear whether “a plurality of first light-emitting units in the first region” is the same or different from previously recited “a plurality of first light-emitting units”. For the purpose of this Action, the limitation “the first driving circuit comprises: an active layer, a gate dielectric layer, a gate electrode layer located on the gate dielectric layer, a first capacitor conductive layer located on the gate dielectric layer, a gate structure” will be interpreted and examined as --the first driving circuit comprises: an active layer, a gate structure comprising a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, a first capacitor conductive layer located on the gate dielectric layer--; and the limitation “a plurality of first light-emitting units in the first region” will be interpreted and examined as redundant limitation and will be omitted. Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 28 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Fujioka (US Pub. 20180293936). Regarding claim 28, Fujioka discloses in Fig. 10, Fig. 11-12, paragraph [0073]-[0096] a display panel, comprising: a second region [region adjacent region 310]; a first region [310] having a plurality of first light emitting units [180], wherein a light transmittance of the first region [310] is greater than a light transmittance of the second region [because there is no driving circuit is provided in the light-transmitting region 310]; a driving backboard [141 and PX] comprising a first driving circuit [PX] of the second region that is configured to drive at least one of the first light emitting units [180] to emit light, wherein the first driving circuit further comprises: an active layer [162b], a gate structure comprising a gate dielectric layer [164], a gate electrode layer [166] located on the gate dielectric layer [164], a first capacitor conductive layer [172] located on the gate dielectric layer [164], a capacitor dielectric layer [152] covering the gate electrode layer [166] and the first capacitor conductive layer [172], a second capacitor conductive layer [a portion of 168] located on the capacitor dielectric layer [152] and directly opposite to the first capacitor conductive layer [172] to form a storage capacitor. PNG media_image1.png 518 992 media_image1.png Greyscale PNG media_image2.png 580 704 media_image2.png Greyscale It is noted that “to form a storage capacitor” directs to intended function or manner of operation of the claimed structure comprising the first conductive layer, a second conductive layer located on the dielectric layer and directly opposite to the first conductive layer. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). MPEP 2114 (II). Further, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 6, 9-10, 15, 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Fujioka (US Pub. 20180293936) in view of Tokuda et al. (US Pub. 20140332781), Yang et al. (US Pub. 20170373124), and Nozawa et al. (US Pub. 20180240854). Regarding claims 1, 6, 9-10, Fujioka discloses in Fig. 10, Fig. 11-12, paragraph [0073]-[0096] a display panel, comprising a transition region and a light-transmitting region [310] having a plurality of first light emitting units [180], wherein a light transmittance of the light-transmitting region [310] is greater than a light transmittance of the transition region [because there is no driving circuit is provided in the light-transmitting region 310]; and the display panel further comprises: a driving backboard [141 and PX] comprising a first driving circuit [PX(1,3)] located in the transition region, and the first driving circuit [PX(1,3)] having a first output end; a first planarization layer [upper portion of 158] located on the driving backboard of the transition region and the light-transmitting region [310]; a first electrode layer [176] located at a side of the first planarization layer [upper portion of 158] of the transition region, the side of the first planarization layer [upper portion of 158] of the transition region being away from the driving backboard, and the first electrode layer [176] extending through the first planarization layer [upper portion of 158] to electrically connect with the first output end; a second planarization layer [194] located at a side of the first planarization layer [upper portion of 158] and the first electrode layer [176], the side of the first planarization layer [upper portion of 158] and the first electrode layer [176] being away from the driving backboard; a second electrode layer [182] located at a side of the second planarization layer [194] of the transition region and the light-transmitting region [310], the side of the second planarization layer [194] of the transition region and the light-transmitting region [310] being away from the driving backboard, and the second electrode layer [182] extending through the second planarization layer [194] to contact with the first electrode layer [176]; a pixel defining layer [178] in which the plurality of first light-emitting units is arranged, the pixel defining layer [178] located at the side of the second planarization layer [194] away from the driving backboard [141 and PX]; a cathode [186] located at a side of the pixel defining layer [178] away from the driving backboard [141 and PX][Fujioka defined in paragraph [0066] that anode is an electrode connected to driving transistor and cathode is an electrode not connected to driving transistor. Thus, the first electrode 182 of light emitting element 180 is an anode and the second electrode 186 of light emitting element 180 is a cathode]; a third driving circuit [PX(1,1)] comprising a third output end; a fifth electrode layer located at a side of the first planarization layer [upper portion of 158] away from the driving backboard [141 and PX] and extending through the first planarization layer [upper portion of 158] to contact with the third output end. PNG media_image3.png 533 763 media_image3.png Greyscale PNG media_image4.png 433 925 media_image4.png Greyscale PNG media_image1.png 518 992 media_image1.png Greyscale Fujioka fails to discloses wherein a light transmittance of the second electrode layer is greater than a light transmittance of the first electrode layer; wherein a material of the second electrode layer is a transparent conductive material. Tokuda et al. discloses in Fig. 2, paragraph [0029], [0035], [0037] wherein a light transmittance of the second electrode layer [108] is greater than a light transmittance of the first electrode layer [106]; wherein a material of the second electrode layer [108] is a transparent conductive material. It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Tokuda et al. into the method of Fujioka to include wherein a light transmittance of the second electrode layer is greater than or equal to a light transmittance of the first electrode layer; wherein a material of the second electrode layer is a transparent conductive material. The ordinary artisan would have been motivated to modify Fujioka in the above manner for the purpose of providing suitable material of the second electrode and enabling to provide an organic EL display device with excellent control of light emitting characteristics and improved visual angle characteristics without adding any changes to an organic EL layer or cathode electrode [paragraph [0037], [0045] of Tokuda et al.]. Fujioka fails to disclose a supporting column located at the side of the pixel defining layer away from the driving backboard, such that the cathode covers the supporting column. Yang et al. discloses in Fig. 1, Fig. 4 a supporting column [142 and/or 246] located at the side of the pixel defining layer [141] away from the driving backboard, such that the cathode [160] covers the supporting column [142 and/or 246]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yang et al. into the method of Fujioka to include a supporting column located at the side of the pixel defining layer away from the driving backboard, such that the cathode covers the supporting column. The ordinary artisan would have been motivated to modify Fujioka in the above manner for the purpose of improving reflection of external light and decreasing the reflection luminance; suppressing a defect caused by a contact with a mask when a plurality of transport layers or light emitting layers EML is formed on the emission structure or the second electrode is formed on the emission structure [paragraph [0120]-[0121], [0126], [0129] of Yang et al.]. Fujioka fails to disclose a plurality of discrete light-reflecting layers, wherein the plurality of light-reflecting layers is located at a side of the first planarization layer of the light-transmitting region, the side of the first planarization layer of the light-transmitting region is away from the driving backboard in a same layer as the fifth electrode layer, and each discrete light-reflecting layer of the plurality of light-reflecting layers corresponds to a respective position of each of the first light-emitting units; wherein an orthographic projection of each discrete light-reflecting layer of the plurality of the light-reflecting layers on the driving backboard is located in an orthographic projection of each of the first light-emitting units on the driving backboard; wherein the plurality of discrete light-reflecting layers and the first electrode layer are provided in the same layer, and a material of the plurality of discrete light-reflecting layers is the same as a material of the first electrode layer. Nozawa et al. discloses in Fig. 10, paragraph [0095]-[0096], [0102], [0123]-[0124] a plurality of discrete light-reflecting layers [14], wherein the plurality of light-reflecting layers [14] is located at a side of the first planarization layer [17] of the light-transmitting region, the side of the first planarization layer [17] of the light-transmitting region is away from the driving backboard in a same layer as the fifth electrode layer, and each discrete light-reflecting layer of the plurality of light-reflecting layers [14] corresponds to a respective position of each of the first light-emitting units; wherein an orthographic projection of each of the light- reflecting layers [14] on the driving backboard is located in an orthographic projection of each of the first light-emitting units on the driving backboard; wherein the light-reflecting layers [14] and the first electrode layer are provided in the same layer, and a material of the light-reflecting layers [14] is the same as a material of the first electrode layer. PNG media_image5.png 537 433 media_image5.png Greyscale It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Nozawa et al. into the method of Fujioka to include a plurality of discrete light-reflecting layers, wherein the light-reflecting layers are located at a side of the first planarization layer of the light-transmitting region, the side of the first planarization layer of the light-transmitting region is away from the driving backboard in a same layer as the fifth electrode layer, and each of the light-reflecting layers corresponds to a position of each of the first light-emitting units; wherein an orthographic projection of each of the light- reflecting layers on the driving backboard is located in an orthographic projection of each of the first light-emitting units on the driving backboard; wherein the light-reflecting layers and the first electrode layer are provided in the same layer, and a material of the light-reflecting layers is the same as a material of the first electrode layer. The ordinary artisan would have been motivated to modify Fujioka in the above manner for the purpose of enabling an optical resonance structure being constructed between a reflective layer and the second electrode, and obtaining intensified light brightness of emitted light [paragraph [0123]-[0124] of Nozawa et al.]. Regarding claim 2, Fujioka discloses in Fig. 10-12 wherein the plurality of first light-emitting units [180] is located at a side of the second electrode layer [182], the side of the second electrode layer [182] is away from the driving backboard, and the second electrode layer [182] is used for providing an electrical signal for the plurality of first light-emitting units. Regarding claim 15, Fujioka discloses in Fig. 10-12, paragraph [0073]-[0096] wherein the display panel further comprises a main screen region, and the transition region is located between the main screen region and the light- transmitting region; the driving backboard further comprises the third driving circuit in the main screen region, wherein the display panel further comprises: a main screen region electrode comprising: the fifth electrode layer; and a sixth electrode layer located at a side of the second planarization layer [194], the side of the second planarization layer being away from the driving backboard, and the sixth electrode layer extending through the second planarization layer [194] to contact with the fifth electrode layer; and a third light-emitting unit disposed in the main screen region, the third light-emitting unit being located at a side of the main screen region electrode, the side of the main screen region electrode being away from the driving backboard, and the main screen region electrode being used for providing an electrical signal for the third light-emitting unit. PNG media_image1.png 518 992 media_image1.png Greyscale PNG media_image3.png 533 763 media_image3.png Greyscale Regarding claim 22, Fujioka discloses in Fig. 11 wherein the first driving circuit comprises: an active layer [162b], a gate structure comprising a gate dielectric layer [164], and a gate electrode layer [166] located on the gate dielectric layer [164], a first capacitor conductive layer [172] located on the gate dielectric layer [164], a capacitor dielectric layer [152] covering the gate electrode layer [166] and the first capacitor conductive layer [172], a second capacitor conductive layer [a portion of 168] located on the capacitor dielectric layer [152] and directly opposite to the first capacitor conductive layer [172] to form a storage capacitor. PNG media_image2.png 580 704 media_image2.png Greyscale It is noted that “to form a storage capacitor” directs to intended function or manner of operation of the claimed structure comprising the first conductive layer, a second conductive layer located on the dielectric layer and directly opposite to the first conductive layer. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). MPEP 2114 (II). Further, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Regarding claim 23, Fujioka discloses in Fig. 1, Fig. 10, Fig. 11-12 a plurality of first light-emitting units in the light-transmitting region [310], wherein an orthographic projection of the first electrode layer [176] on the substrate does not overlap with an orthographic projection of each first light-emitting unit on the substrate. PNG media_image6.png 474 641 media_image6.png Greyscale PNG media_image7.png 503 1150 media_image7.png Greyscale Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Fujioka (US Pub. 20180293936) in view of Tokuda et al. (US Pub. 20140332781), Yang et al. (US Pub. 20170373124), and Nozawa et al. (US Pub. 20180240854) as applied to claims 1 above and further in view of Li et al. (CN110189639A). Regarding claims 4 and 5, Fujioka fails to discloses wherein the second electrode layer located in the light- transmitting region comprises a plurality of electrode blocks and a plurality of electrode bridges for connecting adjacent electrode blocks, and each of the first light-emitting units is correspondingly located at a side of each of the electrode blocks, the side of each of the electrode blocks is away from the driving backboard; wherein the second electrode layer of the light- transmitting region has a wave shape, and each of the electrode blocks is located at a peak of the wave shape or a trough of the wave shape. Li discloses in Fig. 4, Fig. 6, Fig. 7, paragraph [0100] wherein the second electrode layer [111] located in the light- transmitting region [10] comprises a plurality of electrode blocks [1111] and a plurality of electrode bridges [1112] for connecting adjacent electrode blocks [1111], and each of the first light-emitting units is correspondingly located at a side of each of the electrode blocks [1111], the side of each of the electrode blocks [1111] is away from the driving backboard; wherein the second electrode layer [111] of the light- transmitting region has a wave shape, and each of the electrode blocks [1111] is located at a peak of the wave shape or a trough of the wave shape. It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Li et al. into the method of Fujioka to include wherein the second electrode layer located in the light- transmitting region comprises a plurality of electrode blocks and a plurality of electrode bridges for connecting adjacent electrode blocks, and each of the first light-emitting units is correspondingly located at a side of each of the electrode blocks, the side of each of the electrode blocks is away from the driving backboard; wherein the second electrode layer of the light-transmitting region has a wave shape, and each of the electrode blocks is located at a peak of the wave shape or a trough of the wave shape. The ordinary artisan would have been motivated to modify Fujioka in the above manner for the purpose of reducing the complexity of the structure within the light-transmitting region, effectively improving the diffraction superposition phenomenon caused by the complex structure of the light-transmitting region during light transmission, thereby avoiding image distortion defects, simplifying the control of the light-transmitting region. [paragraph [0100] of Li et al.]. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Fujioka (US Pub. 20180293936) in view of Tokuda et al. (US Pub. 20140332781), Yang et al. (US Pub. 20170373124), and Nozawa et al. (US Pub. 20180240854) as applied to claim 1 above and further in view of Lee et al. (US Pub. 20180190944). Regarding claim 7, Fujioka fails to disclose wherein the first electrode layer comprises a first transparent electrode layer, a metal electrode layer and a second transparent electrode layer which are sequentially stacked. Lee et al. discloses in Fig. 2, paragraph [0057]-[0059] wherein the first electrode layer [41] comprises a first transparent electrode layer [41a], a metal electrode layer [41b] and a second transparent electrode layer [41c] which are sequentially stacked. It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Lee et al. into the method of Fujioka to include wherein the first electrode layer comprises a first transparent electrode layer, a metal electrode layer and a second transparent electrode layer which are sequentially stacked. The ordinary artisan would have been motivated to modify Fujioka in the above manner for the purpose of providing suitable structure of the first electrode layer exhibit high electrical conductivity, low resistance to external oxygen or moisture and high corrosion resistance [paragraph [0058]-[0059] of Lee et al.]. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Fujioka (US Pub. 20180293936) in view of Tokuda et al. (US Pub. 20140332781), Yang et al. (US Pub. 20170373124), and Nozawa et al. (US Pub. 20180240854) as applied to claim 15 above. Regarding claim 16, Fujioka discloses in Figs. 11-12, wherein the fifth electrode layer and the first electrode layer are provided in the same layer; and the sixth electrode layer and the second electrode layer are provided in the same layer. PNG media_image1.png 518 992 media_image1.png Greyscale Fujioka fails to explicitly disclose a material of the fifth electrode layer is same as a material of the first electrode layer; and a material of the sixth electrode layer is same as a material of the second electrode layer. It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the teachings of Fujioka to include a material of the fifth electrode layer is same as a material of the first electrode layer; and a material of the sixth electrode layer is same as a material of the second electrode layer. The ordinary artisan would have been motivated to modify Fujioka in the above manner for the purpose of enabling to form electrodes simultaneously and thus simplifying process of forming the first and fifth electrodes and process of forming the second and sixth electrodes. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Fujioka (US Pub. 20180293936) in view of Tokuda et al. (US Pub. 20140332781). Regarding claim 24, Fujioka discloses in Fig. 10, Fig. 11-12, paragraph [0073]-[0096] a display panel, comprising: a second region [region adjacent region 310]; a first region [310] having a plurality of first light emitting units [180], a driving backboard [141 and PX] comprising a first driving circuit [PX] having a first output end; a first planarization layer [upper portion of 158] located on the driving backboard of the first region [310] and the second region; a first electrode layer [176] located at a side of the first planarization layer [upper portion of 158] of the second region, wherein the first electrode layer [176] extends through the first planarization layer [upper portion of 158] to electrically connect with the first output end; a second planarization layer [194] located at a side of the first planarization layer [upper portion of 158] and the first electrode layer [176] away from the driving backboard; a second electrode layer [182] located at a side of the second planarization layer [194] away from the driving backboard, wherein the second electrode layer [182] extends through the second planarization layer [194] to contact with the first electrode layer [176], and the first driving circuit comprises: an active layer [162b], a gate dielectric layer [164], a gate electrode layer [166] located on the gate dielectric layer [164], a first capacitor conductive layer [172] located on the gate dielectric layer [164], a capacitor dielectric layer [upper portion of 152][See annotated drawing] covering the gate electrode layer [166] and the first capacitor conductive layer [172], a second capacitor conductive layer [a portion of 168] located on the capacitor dielectric layer [upper portion of 152] and directly opposite to the first capacitor conductive layer [172] to form a storage capacitor. PNG media_image1.png 518 992 media_image1.png Greyscale PNG media_image8.png 580 747 media_image8.png Greyscale It is noted that “to form a storage capacitor” directs to intended function or manner of operation of the claimed structure comprising the first conductive layer, a second conductive layer located on the dielectric layer and directly opposite to the first conductive layer. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). MPEP 2114 (II). Further, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Fujioka fails to discloses wherein a light transmittance of the second electrode layer is greater than or equal to a light transmittance of the first electrode layer Tokuda et al. discloses in Fig. 2, paragraph [0029], [0035], [0037] wherein a light transmittance of the second electrode layer [108] is greater than a light transmittance of the first electrode layer [106]. It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Tokuda et al. into the method of Fujioka to include wherein a light transmittance of the second electrode layer is greater than or equal to a light transmittance of the first electrode layer. The ordinary artisan would have been motivated to modify Fujioka in the above manner for the purpose of providing suitable material of the second electrode and enabling to provide an organic EL display device with excellent control of light emitting characteristics and improved visual angle characteristics without adding any changes to an organic EL layer or cathode electrode [paragraph [0037], [0045] of Tokuda et al.]. Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Fujioka (US Pub. 20180293936) as applied to claim 28 above and further in view of Tokuda et al. (US Pub. 20140332781). Regarding claim 29, Fujioka discloses in Fig. 10, Fig. 11-12, paragraph [0073]-[0096], the first driving circuit [PX (1,3)] having a first output end and the display panel further comprises: a first planarization layer [upper portion of 158] located on the driving backboard of the first region [310] and the second region; a first electrode layer [176] located at a side of the first planarization layer [upper portion of 158] of the second region, wherein the first electrode layer [176] extends through the first planarization layer [upper portion of 158] to electrically connect with the first output end; a second planarization layer [194] located at a side of the first planarization layer [upper portion of 158] and the first electrode layer [176] away from the driving backboard; a second electrode layer [182] located at a side of the second planarization layer [194] away from the driving backboard, wherein the second electrode layer [182] extends through the second planarization layer [194] to contact with the first electrode layer [176] PNG media_image1.png 518 992 media_image1.png Greyscale Fujioka fails to discloses wherein a light transmittance of the second electrode layer is greater than or equal to a light transmittance of the first electrode layer. Tokuda et al. discloses in Fig. 2, paragraph [0029], [0035], [0037] wherein a light transmittance of the second electrode layer [108] is greater than a light transmittance of the first electrode layer [106]. It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Tokuda et al. into the method of Fujioka to include wherein a light transmittance of the second electrode layer is greater than or equal to a light transmittance of the first electrode layer. The ordinary artisan would have been motivated to modify Fujioka in the above manner for the purpose of providing suitable material of the second electrode and enabling to provide an organic EL display device with excellent control of light emitting characteristics and improved visual angle characteristics without adding any changes to an organic EL layer or cathode electrode [paragraph [0037], [0045] of Tokuda et al.]. Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Fujioka (US Pub. 20180293936) in view of Tokuda et al. (US Pub. 20140332781) as applied to claim 24 above and further in view of Luo et al. (US Pub. 20220238614) Regarding claim 31, Fujioka fails to disclose an insulating dielectric layer covering the capacitor dielectric layer and the second capacitor conductive layer, wherein the gate dielectric layer, the capacitor dielectric layer and the insulating dielectric layer are located in the second area and the first area. Luo et al. discloses in Fig. 4 an insulating dielectric layer [44] covering the capacitor dielectric layer [43] and the second capacitor conductive layer [262], wherein the gate dielectric layer [42], the capacitor dielectric layer [43] and the insulating dielectric layer [44] are located in the second area [1012] and the first area [1011]. Luo et al. further suggests in Fig. 2, Fig. 3 that alternatively, the gate dielectric layer, the capacitor dielectric layer and the insulating dielectric layer are located only in the first area. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Luo et al. into the method of Fujioka to include an insulating dielectric layer covering the capacitor dielectric layer and the second capacitor conductive layer, wherein the gate dielectric layer, the capacitor dielectric layer and the insulating dielectric layer are located in the second area and the first area. The ordinary artisan would have been motivated to modify Fujioka in the above manner for the purpose of providing suitable configuration of insulating layers located in the first and second areas to reduce the probability of over-etching when the insulation layers are etched [paragraph [0069], [0076] of Luo et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Response to Arguments Applicant’s arguments with respect to claims 1-2, 4-7, 9-10, 15-16, 21-30 have been considered but are moot in view of the new ground of rejection. In addition, Applicant's arguments filed 10/02/2025 have been fully considered but they are not persuasive. Regarding Applicant’s argument on page 14 that “While Nozawa may have allegedly reflective layers 14 in Fig. 10, they are not in the same layer as the fifth electrode layer, so Nozawa does not remedy Fujioka's deficiencies.” Examiner respectfully disagrees because of the following reasons: First, as stated above, Nozawa et al. discloses in Fig. 10, a plurality of discrete light-reflecting layers [14] in a same layer as the fifth electrode layer, and wherein the light-reflecting layers [14] and the first electrode layer are provided in the same layer. PNG media_image5.png 537 433 media_image5.png Greyscale In addition, Applicant did not provide any argument with respect to the rejection of claim 10. Therefore, Applicant appears to agree that Nozawa et al. discloses in Fig. 10 the light-reflecting layers [14] and the first electrode layer are provided in the same layer. Fujioka suggests the fifth electrode layer is in the same layer as the first electrode layer. Consequently, the combination of Fujioka and Nozawa et al. would result to a plurality of discrete light-reflecting layers in a same layer as the fifth electrode layer. Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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Prosecution Timeline

Show 3 earlier events
Dec 27, 2024
Final Rejection mailed — §102, §103, §112
Mar 25, 2025
Response after Non-Final Action
Apr 28, 2025
Request for Continued Examination
May 01, 2025
Response after Non-Final Action
Jul 02, 2025
Non-Final Rejection mailed — §102, §103, §112
Oct 02, 2025
Response Filed
Oct 28, 2025
Final Rejection mailed — §102, §103, §112
Dec 29, 2025
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

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Prosecution Projections

4-5
Expected OA Rounds
45%
Grant Probability
58%
With Interview (+13.6%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 519 resolved cases by this examiner. Grant probability derived from career allowance rate.

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