Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is final and is in response to claims filed on 02/25/2026 via amendment. Claims 1-5, 7, and 13-19 are pending for examination. Claims 1, 3, 5, 13, and 15 are currently amended. Claims 2, 4, 7, 14, and 16-19 are as previously presented.
Response to Arguments
Claim Interpretations
Applicant has amended the language of claim 15. However, these amendments still are directed to contingent language. Therefore, the previous interpretation of claim 15 has been updated and maintained.
Claim Objections
Applicant has amended or cancelled the claims at issue, and, therefore, the previous objections have been withdrawn.
Rejections under 35 U.S.C. 112
Applicant has amended or cancelled the claims at issue, and, therefore, the previous rejections have been withdrawn.
Rejections under 35 U.S.C. 103
Applicant’s arguments regarding the 35 U.S.C. 103 rejections have been fully considered. Applicant argues “Amended independent claims 1 and 13 recite, inter alia, that an in-memory vector processor performs the parallel search by executing a "plurality of bitwise logical operations concurrently across its separate columns". This claimed structure and function are not taught by the prior art combination.” See Remarks 8 Filed 02/25/2026.
Examiner respectfully disagrees with Applicant’s arguments. Teague teaches of the in-memory processor, see Teague [0022] and Sharangpani teaches of searching the columns in parallel, see Sharangpani [0055], Fig. 2A, [0061], and [0039].
Applicant further argues “Teague's architecture is, by its very nature, incapable of performing the claimed "bitwise logical operations concurrently across said separate columns".”. See Remarks 8.
Examiner respectfully disagrees with Applicant’s arguments. Teague reads on the in memory processor while Sharangpani teaches the columns.
Applicant further argues “A POSA would immediately recognize that you cannot feed an analog voltage representing a mathematical sum into a digital search engine expecting a bit vector”. See Remarks 8.
Examiner respectfully disagrees with Applicant’s arguments. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). For example, the in-memory computing of Teague would increase the efficiency of the system as having the computing circuits in the memory would decrease the amount of data transfers needed. Also, according to Teague, the in memory computing would allow for a significant reduction in power used as taught by Teague in paragraph [0002]. One of ordinary skill in the art would recognize that using the DAC of Teague to convert the digital inputs into analog would increase the efficiency of the system as it would allow for the computations of Sharangpani to be performed in memory. In Teague, they a storing bits of a matrix in the CiM array and performing calculations on them, just as Sharangpani stores matrices and performs elementwise calculations on them for search purposes. See Teague [0020]-[0021].
Applicant further argues “Therefore, the Examiner's argument is based on improper hindsight”. See Remarks 8.
Examiner respectfully disagrees with Applicant’s arguments. In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). As shown in the previous office action filed 10/29/2025, the motivations for combining the references come from the references themselves.
Claim Objections
Claim 5 is objected to because of the following informalities:
Claim 5 recites “wherein said Cspan generator to generate at least an initial combination from each said at least one seed,”. This should be changed to something to the effect of “wherein said Cspan generator is configured to generate at least an initial combination from each said at least one seed,
Appropriate correction is required.
Claim Interpretation-Part I
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “a seed generator”, and “a Cspan generator”, “a rule checker” in claims 1, 3, 4, 5, and 6.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Interpretation – Part II
Claim 15 is directed to a method that recites conditional language. Claim 15 recites “said first generating comprising generating a next seed when all possible seeds for N and M have not been generated” (emphasis added).
The conditional nature of this claim language allows for an interpretation where any prior art meets the broadest reasonable interpretation of the claim without having the conditional language even occurring (and thus only the preceding limitations required by the prior art). For example, in claim 15, the “said first generating comprising generating a next seed when all possible seeds for N and M have not been generated” limitation is not required to be taught by prior art. See MPEP 2111.04(II); see also Ex parte Schulhauser. Examiner notes that the broadest reasonable interpretation of the method of claim 15 requires none of those “when” conditions to occur and thus the claim language ends. Examiner encourages claim amendments that specifically removes the conditional language of the claims and thus expressly has the claimed scenarios occur. For example changing the when statement to “determining that”. Nevertheless, the prior art cited below reads on the structure for performing all of the functionality in the non-method claims (i.e. claim 3), and thus, in an effort to advance compact prosecution, reads on all of the method claim(s) as well. Examiner respectfully reiterates that without changing the conditional nature of the claim, the method claims carry no patentable weight as noted above. The prior art mappings are solely to advance compact prosecution.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, and 13-19 are rejected as being unpatentable over Stomenovic et al. (“Listing combinatorial objects in parallel”), as included in the IDS filed 09/05/2022, hereinafter Stomenovic in view of Tredak et al. (US 20160162262 A1) hereinafter Tredak further in view of Teague et al. (US 20210343343 A1) hereinafter Teague further in view of Sharangpani et al. (US 20040059725 A1) hereinafter Sharangpani.
With regards to claim 1, Stomenovic teaches A system for parallel combinatorial design, the system comprising: a processor, (Stomenovic Page 130 Section 3: In this model, a number of processors)
and a storage unit; (Stomenovic Page 130 Section 3: In this model, a number of processors share a common memory)
[wherein said processor comprises: a seed generator to generate] at least one seed (Stomenovic Page 131 Section 3: A combinatorial object consists of n elements selected from a set of m elements S= {s1,s2,...,Sm})
to generate combinations of M out of N items, (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
a Cspan generator to generate at least one combination from said at least one seed (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
and to store each said at least one combination in a [separate column of said in-memory vector processor;] (Stomenovic Page 131 Section 3: in a parallel algorithm the corresponding value ai may be stored in a local memory of a processor)
said storage unit [to receive search results of said rule checker from said in- memory vector processor] (Stomenovic Page 130 Section 3: In this model, a number of processors share a common memory).
While Stomenovic teaches of storing the combinations, they fail to teach an in-memory vector processor, [and to store each said at least one combination in a] separate column of said in-memory vector processor, a rule checker to generate a parallel search request to said in- memory vector processor for a specific combination related to a received rule, and said rule checker to receive search results from said in- memory vector processor.
However, Teague teaches an in-memory vector processor (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[and to store each said at least one combination in a] separate column of said in-memory vector processor; (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[a rule checker to generate a parallel search request to said] in- memory vector processor [for a specific combination related to a received rule] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[said] in-memory vector processor [to perform said parallel search by executing a plurality of bitwise logical operations concurrently across said separate columns to identify which of said combinations satisfy said rule] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[said rule checker to receive search results from said] in- memory vector processor (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic with the in-memory vector processor and storing the data in columns of the processor as taught by Teague. One of ordinary skill in the art would be motivated to make this combination because it allows for a significant reduction in power used as taught by Teague (Teague [0002]).
While Stomenovic in view of Teague teaches of a seed, they fail to teach wherein said processor comprises: a seed generator to generate [at least one seed].
However, Tredak teaches wherein said processor comprises: a seed generator to generate [at least one seed] (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague with generating the seed as taught by Tredak. One of ordinary skill in the art would be motivated to make this combination because it would be advantageous to provide a parallel procedure for pseudo-random, number generation based on the MT19937 with efficient use of available hardware resources in a highly parallel architecture thereby improving the computation speed as taught by Tredak (Tredak [0005]). It would also allow for different seeds to be used increasing the flexibility of if the system.
Stomenovic in view of Teague further in view of Tredak fails to teach and a rule checker to generate a parallel search request to said [in- memory vector processor] for a specific combination related to a received rule, said [in-memory vector] processor to perform said parallel search by executing a plurality of bitwise logical operations concurrently across said separate columns to identify which of said combinations satisfy said rule, and said rule checker to receive search results from said [in-memory vector processor].
However, Sharangpani teaches and a rule checker to generate a parallel search request to said [in- memory vector processor] for a specific combination related to a received rule; (Sharangpani [0046]: A rule processing architecture is described for use in a rule processor for content analysis that allows for parallel and recursive sequencing of rules against the content payload. The architecture provides for parallel pattern matching capability coupled to the capability of making multiple rapid content-based state transitions)
said [in-memory vector processor] to perform said parallel search by executing a plurality of bitwise logical operations concurrently across said separate columns to identify which of said combinations satisfy said rule (Sharangpani [0055]: Irrespective of the manner in which the searchable data is organized throughout search array 202c, search array 202c receives a pattern 201b and mask 201c. Pattern 201b is compared against entries in search array 202c; Sharangpani Fig. 2A: shows the system searching in columns in a bitwise manner; Sharangpani [0061]: The circuit operates in a manner that provides a fully parallel search operation by performing a simultaneous search within all its rows in one clock period. When a search operation is conducted, all byte level match lines 401 in a column simultaneously indicate matches with their respective stored bytes; Sharangpani [0039]: as well as logical and computational operators to be applied to the search results)
and said rule checker to receive search results from said [in- memory vector processor] (Sharangpani [0051]: Search execution unit 202 outputs a result 203 that, in one embodiment, is comprised of an indication of the success of the search operation and additionally includes one or more parameters such as, but not limited to, an index that indicates the location within the search register that met the search instruction of the search operation; Sharangpani [0056]: Additionally, sorter 202b may also be coupled to a register file for storage of results).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak with the rule checker as taught by Sharangpani. One of ordinary skill in the art would be motivated to make this combination because it would enable efficient processing of workloads intensive in rule-grammars as taught by Sharangpani (Sharangpani [0031]). It would also ensure that only the combinations that are required by the rules are stored, increasing the efficiency of the system.
With regards to claim 2, Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani teaches all of the limitations of claim 1 above. Stomenovic further teaches wherein said storage unit is implemented in one of said processor and said in-memory vector processor (Stomenovic Page 130 Section 3: In this model, a number of processors share a common memory).
With regards to claim 3, Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani teaches all of the limitations of claim 1 above. Stomenovic further teaches and said Cspan generator is configured to generate a plurality of combinations from said next seed (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
and to store said combinations [separately in columns of said in-memory vector processor] (Stomenovic Page 131 Section 3: in a parallel algorithm the corresponding value ai may be stored in a local memory of a processor).
Stomenovic fails to teach [and to store said combinations] separately in columns of said in-memory vector processor.
However, Teague teaches [and to store said combinations] separately in columns of said in-memory vector processor (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani with storing the data in columns of the processor as taught by Teague. One of ordinary skill in the art would be motivated to make this combination because it allows for a significant reduction in power used as taught by Teague (Teague [0002]).
Stomenovic in view of Teague fails to teach wherein said seed generator is configured to generate a next seed if all possible seeds for N and M have not been generated.
However, Tredak teaches wherein said seed generator is configured to generate a next seed if all possible seeds for N and M have not been generated (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers comprises… computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani with generating the seeds as taught by Tredak. One of ordinary skill in the art would be motivated to make this combination because it would be advantageous to provide a parallel procedure for pseudo-random, number generation based on the MT19937 with efficient use of available hardware resources in a highly parallel architecture thereby improving the computation speed as taught by Tredak (Tredak [0005]). It would also allow for different seeds to be used increasing the flexibility of if the system.
With regards to claim 4, Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani teaches all of the limitations of claim 1 above. Stomenovic fails to teach wherein said seed generator is a recursive, parallel seed generator to recursively generate a multiplicity of threads, each thread generating a plurality of seeds.
However, Tredak does teach wherein said seed generator is a recursive, parallel seed generator (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers comprises… computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function)
to recursively generate a multiplicity of threads, (Tredak [0008]: computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function)
each thread generating a plurality of seeds (Tredak [0008]: computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani with generating the seeds as taught by Tredak. One of ordinary skill in the art would be motivated to make this combination because it would be advantageous to provide a parallel procedure for pseudo-random, number generation based on the MT19937 with efficient use of available hardware resources in a highly parallel architecture thereby improving the computation speed as taught by Tredak (Tredak [0005]). It would also allow for different seeds to be used increasing the flexibility of if the system.
With regards to claim 5, Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani teaches all of the limitations of claim 4 above. Stomenovic further teaches wherein said Cspan generator to generate at least an initial combination from each said at least one seed, (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
to store each said initial combination [in said separate column] (Stomenovic Page 131 Section 3: in a parallel algorithm the corresponding value ai may be stored in a local memory of a processor)
and to generate a next combination from a current combination for each combination currently stored [in said separate column] (Stomenovic Page 130 Section 3: Using this model, algorithms are designed to generate combinations [2], permutations [2], etc; Stomenovic Page 131 Section 3: There are usually many instances of a combinatorial object. For example, two combinations of n out of m given elements are distinct if they differ in the elements they contain, while two permutations of m given elements are distinct if they differ in the order of their elements; Stomenovic Page 136 Section 5: The nth element sweeps from one end of the (n - 1)-permutation to the other by a sequence of adjacent swaps, producing a new n-permutation each time).
Stomenovic fails to teach that the combinations are stored in columns.
However, Teague teaches [to store each said initial combination] in said separate column (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[and to generate a next combination from a current combination for each combination currently stored] in said separate column (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani with storing the data in columns of the processor as taught by Teague. One of ordinary skill in the art would be motivated to make this combination because it allows for a significant reduction in power used as taught by Teague (Teague [0002]).
With regards to claim 7, Stomenovic teaches A system for parallel combinatorial design, the system comprising (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
and a combination portion, (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
[an in-memory] Cspan generator to generate at least an initial combination from each said start-up seed and from each said further seed (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
and to store each said initial combination [in a separate column of said combination portion;] (Stomenovic Page 131 Section 3: in a parallel algorithm the corresponding value a; may be stored in a local memory of a processor)
and a storage area of said combination portion [to receive search results of said in-memory rule checker,] (Stomenovic Page 130 Section 3: In this model, a number of processors share a common memory)
[said in-memory] Cspan generator to generate a next combination from a current combination for each combination currently stored [in said separate column] of said combination portion; (Stomenovic Page 130 Section 3: Using this model, algorithms are designed to generate combinations [2], permutations [2], etc; Stomenovic Page 131 Section 3: There are usually many instances of a combinatorial object. For example, two combinations of n out of m given elements are distinct if they differ in the elements they contain, while two permutations of m given elements are distinct if they differ in the order of their elements; Stomenovic Page 136 Section 5: The nth element sweeps from one end of the (n - 1)-permutation to the other by a sequence of adjacent swaps, producing a new n-permutation each time)
[said in-memory rule checker to check which said next combination satisfies said rule with respect to said search results stored in] said storage area (Stomenovic Page 130 Section 3: In this model, a number of processors share a common memory).
Stomenovic fails to teach in-memory vector processor, comprising a memory array, and a controller, said memory array having a seed portion, said controller comprising: an in-memory seed generator to generate a plurality of further seeds from start-up seeds, each start-up seed being held in a separate column of said seed portion, and said in-memory seed generator to operate on a plurality of said separate columns in parallel to generate said further seeds, an in-memory Cspan generator to generate at least an initial combination from each said start-up seed and from each said further seed, and to store each said initial combination in a separate column of said combination portion, an in-memory rule checker to search in said combination portion for combinations which satisfy a rule, and a storage area of said combination portion to receive search results of said in-memory rule checker, said in-memory Cspan generator to generate a next combination from a current combination for each combination currently stored in said separate column of said combination portion, said in-memory rule checker to check which said next combination satisfies said rule with respect to said search results stored in said storage area.
However, Teague teaches in-memory vector processor (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
comprising a memory array (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
and a controller, (Teague [0052]: The various illustrative circuits described in connection with aspects described herein may be implemented in or with an integrated circuit (IC), such as a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller)
said memory array having [a seed portion] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
said controller comprising: an in-memory [seed generator to generate a plurality of further seeds from start-up seeds,] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[each start-up seed being held in] a separate column [of said seed portion] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
and said in-memory [seed generator to operate] on a plurality of said separate columns [in parallel to generate said further seeds;] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
an in-memory [Cspan generator to generate at least an initial combination from each said start-up seed and from each said further seed] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[and to store each said initial combination] in a separate column of said combination portion; (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
an in-memory [rule checker to search in said combination portion for combinations which satisfy a rule;] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[and a storage area of said combination portion to receive search results of] said in-memory [rule checker,] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
said in-memory [Cspan generator to generate a next combination from a current combination for each combination currently stored] in said separate column [of said combination portion;] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
said in-memory [rule checker to check which said next combination satisfies said rule with respect to said search results stored in said storage area] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic with the in-memory vector processor and storing the data in columns of the processor as taught by Teague. One of ordinary skill in the art would be motivated to make this combination because it allows for a significant reduction in power used as taught by Teague (Teague [0002]).
While Stomenovic in view of Teague teaches of a seed, they fail to teach [said memory array having] a seed portion, [said controller comprising: an in-memory] seed generator to generate a plurality of further seeds from start-up seeds, each start-up seed being held [in a separate column] of said seed portion, and [and said in-memory] seed generator to operate [on a plurality of said separate columns] in parallel to generate said further seeds.
However, Tredak teaches said memory array having] a seed portion (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers)
[said controller comprising: an in-memory] seed generator to generate a plurality of further seeds from start-up seeds, (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers comprises… computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function based on respective first values of the element i, element i+c, and element i+M)
each start-up seed being held [in a separate column] of said seed portion, (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers comprises… computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function based on respective first values of the element i, element i+c, and element i+M)
[and said in-memory] seed generator to operate [on a plurality of said separate columns] in parallel to generate said further seeds (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers comprises… computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function based on respective first values of the element i, element i+c, and element i+M).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague with generating the seed as taught by Tredak. One of ordinary skill in the art would be motivated to make this combination because it would be advantageous to provide a parallel procedure for pseudo-random, number generation based on the MT19937 with efficient use of available hardware resources in a highly parallel architecture thereby improving the computation speed as taught by Tredak (Tredak [0005]). It would also allow for different seeds to be used increasing the flexibility of if the system.
Stomenovic in view of Teague further in view of Tredak fails to teach [an in-memory] rule checker to search in said combination portion for combinations which satisfy a rule, [and a storage area of said combination portion] to receive search results of said [in-memory] rule checker, and said [in-memory] rule checker to check which said next combination satisfies said rule with respect to said search results stored [in said storage area].
However, Sharangpani teaches [an in-memory] rule checker to search in said combination portion for combinations which satisfy a rule; (Sharangpani [0046]: A rule processing architecture is described for use in a rule processor for content analysis that allows for parallel and recursive sequencing of rules against the content payload. The architecture provides for parallel pattern matching capability coupled to the capability of making multiple rapid content-based state transitions)
[and a storage area of said combination portion] to receive search results of said [in-memory] rule checker, (Sharangpani [0051]: Search execution unit 202 outputs a result 203 that, in one embodiment, is comprised of an indication of the success of the search operation and additionally includes one or more parameters such as, but not limited to, an index that indicates the location within the search register that met the search instruction of the search operation; Sharangpani [0056]: Additionally, sorter 202b may also be coupled to a register file for storage of results)
said [in-memory] rule checker to check which said next combination satisfies said rule with respect to said search results stored [in said storage area] (Sharangpani [0056]: The operations are specified by opcode 201a in search instruction 201. Sorter 202b may store intermediate or final results of previous operations that may be used in subsequent operations in conjunction with the match indication lines from search array 202c).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak with the rule checker as taught by Sharangpani. One of ordinary skill in the art would be motivated to make this combination because it would enable efficient processing of workloads intensive in rule-grammars as taught by Sharangpani (Sharangpani [0031]). It would also ensure that only the combinations that are required by the rules are stored, increasing the efficiency of the system.
With regards to claim 13, Stomenovic teaches A method for parallel combinatorial design, the method comprising: [first generating] at least one seed (Stomenovic Page 130 Section 3: In this model, a number of processors; Stomenovic Page 131 Section 3: A combinatorial object consists of n elements selected from a set of m elements S= {s1,s2,...,Sm})
to generate combinations of M out of N items; (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
second generating at least one combination from said at least one seed; (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
storing each said at least one combination in a [separate column of an in-memory vector processor;] (Stomenovic Page 131 Section 3: in a parallel algorithm the corresponding value ai may be stored in a local memory of a processor).
While Stomenovic teaches of storing the combinations, they fail to teach storing each said at least one combination in a [separate column of an in-memory vector processor;], [performing a parallel search at least] in said in-memory vector processor [for combinations which satisfy a rule;], and [and receiving results of said parallel search from] said in-memory vector processor.
However, Teague teaches [storing each said at least one combination in a] separate column of an in-memory vector processor; (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[performing a parallel search at least] in said in-memory vector processor [for combinations which satisfy a rule;] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[and receiving results of said parallel search from] said in-memory vector processor (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic with the in-memory vector processor and storing the data in columns of the processor as taught by Teague. One of ordinary skill in the art would be motivated to make this combination because it allows for a significant reduction in power used as taught by Teague (Teague [0002]).
While Stomenovic in view of Teague teaches of a seed, they fail to teach first generating [at least one seed].
However, Tredak teaches first generating [at least one seed] (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague with generating the seed as taught by Tredak. One of ordinary skill in the art would be motivated to make this combination because it would be advantageous to provide a parallel procedure for pseudo-random, number generation based on the MT19937 with efficient use of available hardware resources in a highly parallel architecture thereby improving the computation speed as taught by Tredak (Tredak [0005]). It would also allow for different seeds to be used increasing the flexibility of if the system.
Stomenovic in view of Teague further in view of Tredak fails to teach performing a parallel search at least in said [in-memory vector processor] using a plurality of bitwise logical operations concurrently across said separate columns to identify which of said combinations satisfy a rule, and and receiving results of said parallel search from [said in-memory vector processor].
However, Sharangpani teaches performing a parallel search at least in said [in-memory vector processor] using a plurality of bitwise logical operations concurrently across said separate columns to identify which of said combinations satisfy a rule; (Sharangpani [0046]: A rule processing architecture is described for use in a rule processor for content analysis that allows for parallel and recursive sequencing of rules against the content payload. The architecture provides for parallel pattern matching capability coupled to the capability of making multiple rapid content-based state transitions; Sharangpani [0055]: Irrespective of the manner in which the searchable data is organized throughout search array 202c, search array 202c receives a pattern 201b and mask 201c. Pattern 201b is compared against entries in search array 202c; Sharangpani Fig. 2A: shows the system searching in columns in a bitwise manner; Sharangpani [0061]: The circuit operates in a manner that provides a fully parallel search operation by performing a simultaneous search within all its rows in one clock period. When a search operation is conducted, all byte level match lines 401 in a column simultaneously indicate matches with their respective stored bytes; Sharangpani [0039]: as well as logical and computational operators to be applied to the search results)
and receiving results of said parallel search from [said in-memory vector processor] (Sharangpani [0051]: Search execution unit 202 outputs a result 203 that, in one embodiment, is comprised of an indication of the success of the search operation and additionally includes one or more parameters such as, but not limited to, an index that indicates the location within the search register that met the search instruction of the search operation; Sharangpani [0056]: Additionally, sorter 202b may also be coupled to a register file for storage of results).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak with the rule checker as taught by Sharangpani. One of ordinary skill in the art would be motivated to make this combination because it would enable efficient processing of workloads intensive in rule-grammars as taught by Sharangpani (Sharangpani [0031]). It would also ensure that only the combinations that are required by the rules are stored, increasing the efficiency of the system.
With regards to claim 14, Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani teaches all of the limitations of claim 13 above. Stomenovic fails to teach wherein said receiving results comprising storing said results in said in-memory vector processor.
However, Teague does teach [wherein said receiving results comprising storing said results] in said in-memory vector processor (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani with the in-memory vector processor as taught by Teague. One of ordinary skill in the art would be motivated to make this combination because it allows for a significant reduction in power used as taught by Teague (Teague [0002]).
Stomenovic in view of Teague fails to teach wherein said receiving results comprising storing said results [in said in-memory vector processor].
However, Sharangpani teaches wherein said receiving results comprising storing said results [in said in-memory vector processor] (Sharangpani [0051]: Search execution unit 202 outputs a result 203 that, in one embodiment, is comprised of an indication of the success of the search operation and additionally includes one or more parameters such as, but not limited to, an index that indicates the location within the search register that met the search instruction of the search operation; Sharangpani [0056]: Additionally, sorter 202b may also be coupled to a register file for storage of results)
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani with the rule checker as taught by Sharangpani. One of ordinary skill in the art would be motivated to make this combination because it would enable efficient processing of workloads intensive in rule-grammars as taught by Sharangpani (Sharangpani [0031]). It would also ensure that only the combinations that are required by the rules are stored, increasing the efficiency of the system.
With regards to claim 15, Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani teaches all of the limitations of claim 13 above. Stomenovic further teaches and said second generating comprising generating a plurality of combinations from said next seed (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements).
Stomenovic fails to teach said first generating comprising generating a next seed when all possible seeds for N and M have not been generated.
However, Tredak teaches said first generating comprising generating a next seed when all possible seeds for N and M have not been generated (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers comprises… computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani with generating the seeds as taught by Tredak. One of ordinary skill in the art would be motivated to make this combination because it would be advantageous to provide a parallel procedure for pseudo-random, number generation based on the MT19937 with efficient use of available hardware resources in a highly parallel architecture thereby improving the computation speed as taught by Tredak (Tredak [0005]). It would also allow for different seeds to be used increasing the flexibility of if the system.
With regards to claim 16, Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani teaches all of the limitations of claim 13 above. Stomenovic fails to teach wherein said first generating comprising recursively generating a multiplicity of threads, each thread generating a plurality of seeds.
However, Tredak teaches wherein said first generating comprising recursively generating a multiplicity of threads, (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers comprises… computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function)
each thread generating a plurality of seeds (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers comprises… computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani with generating the seeds as taught by Tredak. One of ordinary skill in the art would be motivated to make this combination because it would be advantageous to provide a parallel procedure for pseudo-random, number generation based on the MT19937 with efficient use of available hardware resources in a highly parallel architecture thereby improving the computation speed as taught by Tredak (Tredak [0005]). It would also allow for different seeds to be used increasing the flexibility of if the system.
With regards to claim 17, Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani teaches all of the limitations of claim 13 above. Stomenovic further teaches said second generating comprising generating at least an initial combination from each said at least one seed, (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
storing each said initial combination [in said separate column,] (Stomenovic Page 131 Section 3: in a parallel algorithm the corresponding value ai may be stored in a local memory of a processor)
and generating a next combination from a current combination for each combination currently stored [in said separate column] (Stomenovic Page 130 Section 3: Using this model, algorithms are designed to generate combinations [2], permutations [2], etc; Stomenovic Page 131 Section 3: There are usually many instances of a combinatorial object. For example, two combinations of n out of m given elements are distinct if they differ in the elements they contain, while two permutations of m given elements are distinct if they differ in the order of their elements; Stomenovic Page 136 Section 5: The nth element sweeps from one end of the (n - 1)-permutation to the other by a sequence of adjacent swaps, producing a new n-permutation each time).
Stomenovic fails to teach that the combinations are stored in columns.
However, Teague teaches [storing each said initial combination] in said separate column (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[and generating a next combination from a current combination for each combination currently stored] in said separate column (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani with storing the data in columns of the processor as taught by Teague. One of ordinary skill in the art would be motivated to make this combination because it allows for a significant reduction in power used as taught by Teague (Teague [0002]).
With regards to claim 18, Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani teaches all of the limitations of claim 17 above. Stomenovic fails to teach and also comprising checking which said next combination satisfies said rule with respect to previous said results.
However, Sharangpani teaches and also comprising checking which said next combination satisfies said rule with respect to previous said results (Sharangpani [0056]: The operations are specified by opcode 201a in search instruction 201. Sorter 202b may store intermediate or final results of previous operations that may be used in subsequent operations in conjunction with the match indication lines from search array 202c.).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak further in view of Sharangpani with the rule checker as taught by Sharangpani. One of ordinary skill in the art would be motivated to make this combination because it would enable efficient processing of workloads intensive in rule-grammars as taught by Sharangpani (Sharangpani [0031]). It would also ensure that only the combinations that are required by the rules are stored, increasing the efficiency of the system.
With regards to claim 19, Stomenovic teaches A method for parallel combinatorial design, the method comprising: [in-memory generating a plurality of further seeds from start-up seeds,] (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
[in-memory] generating at least an initial combination from each said start-up seed and from each said further seed; (Stomenovic Page 131 Section 3: Using this approach, algorithms are designed to generate various combinatorial objects… A combinatorial object consists of n elements selected from a set of m elements)
storing each said initial combination [in a separate column of a combination portion of said memory array;] (Stomenovic Page 131 Section 3: in a parallel algorithm the corresponding value a; may be stored in a local memory of a processor)
[in-memory] generating a next combination from a current combination for each combination currently stored [in said separate column] of said combination portion; (Stomenovic Page 130 Section 3: Using this model, algorithms are designed to generate combinations [2], permutations [2], etc; Stomenovic Page 131 Section 3: There are usually many instances of a combinatorial object. For example, two combinations of n out of m given elements are distinct if they differ in the elements they contain, while two permutations of m given elements are distinct if they differ in the order of their elements; Stomenovic Page 136 Section 5: The nth element sweeps from one end of the (n - 1)-permutation to the other by a sequence of adjacent swaps, producing a new n-permutation each time).
Stomenovic fails to teach [A method for parallel combinatorial design, the method comprising:] in-memory [generating a plurality of further seeds from start-up seeds,], [each start-up seed being held in a] separate column of a seed portion of a memory array, [said generating operating in parallel] on a plurality of said separate columns of said seed portion [to generate said further seeds;], in-memory [generating at least an initial combination from each said start-up seed and from each said further seed;], [storing each said initial combination] in a separate column of a combination portion of said memory array, in-memory [searching in said combination portion for combinations which satisfy a rule;], [receiving results of said searching] in said combination portion, in-memory [generating a next combination from a current combination for each combination currently stored] in said separate column [of said combination portion;], and and in-memory [checking which said next combination satisfies said rule with respect to said results].
However, Teague teaches [A method for parallel combinatorial design, the method comprising:] in-memory [generating a plurality of further seeds from start-up seeds,] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[each start-up seed being held in a] separate column of a seed portion of a memory array (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[said generating operating in parallel] on a plurality of said separate columns of said seed portion [to generate said further seeds;] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
in-memory [generating at least an initial combination from each said start-up seed and from each said further seed;] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[storing each said initial combination] in a separate column of a combination portion of said memory array (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
in-memory [searching in said combination portion for combinations which satisfy a rule;] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
[receiving results of said searching] in said combination portion (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
in-memory [generating a next combination from a current combination for each combination currently stored] in said separate column [of said combination portion;] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector)
and in-memory [checking which said next combination satisfies said rule with respect to said results] (Teague [0022]: Each column of the CIM array 201 may store the ten values of a corresponding filter 212, essentially transforming the 2-dimensional filter 212 into a one-dimensional vector).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic with the in-memory vector processor and storing the data in columns of the processor as taught by Teague. One of ordinary skill in the art would be motivated to make this combination because it allows for a significant reduction in power used as taught by Teague (Teague [0002]).
Stomenovic in view of Teague fails to teach [A method for parallel combinatorial design, the method comprising: in-memory] generating a plurality of further seeds from start-up seeds, each start-up seed being held in a [separate column of a seed portion of a memory array], and said generating operating in parallel [on a plurality of said separate columns of said seed portion] to generate said further seeds.
However, Tredak teaches [A method for parallel combinatorial design, the method comprising: in-memory] generating a plurality of further seeds from start-up seeds, (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers comprises… computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function based on respective first values of the element i, element i+c, and element i+M)
each start-up seed being held in a [separate column of a seed portion of a memory array] (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers comprises… computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function based on respective first values of the element i, element i+c, and element i+M)
said generating operating in parallel [on a plurality of said separate columns of said seed portion] to generate said further seeds (Tredak [0008]: In another embodiment of the present disclosure, a computer implemented method of generating pseudo-random numbers comprises… computing respective second values of the N elements by the K execution threads in parallel, wherein a second value of element i is computed in accordance with a recursive function based on respective first values of the element i, element i+c, and element i+M).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague with generating the seed as taught by Tredak. One of ordinary skill in the art would be motivated to make this combination because it would be advantageous to provide a parallel procedure for pseudo-random, number generation based on the MT19937 with efficient use of available hardware resources in a highly parallel architecture thereby improving the computation speed as taught by Tredak (Tredak [0005]). It would also allow for different seeds to be used increasing the flexibility of if the system.
Stomenovic in view of Teague further in view of Tredak fails to teach [in-memory] searching in said combination portion for combinations which satisfy a rule, receiving results of said searching [in said combination portion;], and [and in-memory] checking which said next combination satisfies said rule with respect to said results.
However, Sharangpani teaches [in-memory] searching in said combination portion for combinations which satisfy a rule, (Sharangpani [0046]: A rule processing architecture is described for use in a rule processor for content analysis that allows for parallel and recursive sequencing of rules against the content payload. The architecture provides for parallel pattern matching capability coupled to the capability of making multiple rapid content-based state transitions)
receiving results of said searching [in said combination portion;] (Sharangpani [0051]: Search execution unit 202 outputs a result 203 that, in one embodiment, is comprised of an indication of the success of the search operation and additionally includes one or more parameters such as, but not limited to, an index that indicates the location within the search register that met the search instruction of the search operation; Sharangpani [0056]: Additionally, sorter 202b may also be coupled to a register file for storage of results)
[and in-memory] checking which said next combination satisfies said rule with respect to said results (Sharangpani [0056]: The operations are specified by opcode 201a in search instruction 201. Sorter 202b may store intermediate or final results of previous operations that may be used in subsequent operations in conjunction with the match indication lines from search array 202c).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Stomenovic in view of Teague further in view of Tredak with the rule checker as taught by Sharangpani. One of ordinary skill in the art would be motivated to make this combination because it would enable efficient processing of workloads intensive in rule-grammars as taught by Sharangpani (Sharangpani [0031]). It would also ensure that only the combinations that are required by the rules are stored, increasing the efficiency of the system.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.O.G./Examiner, Art Unit 2151
/NICHOLAS KLICOS/Primary Examiner, Art Unit 2118
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