DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 5, 7 – 10, 12 – 18, and 20 are pending.
Response to Arguments
Applicant’s arguments, see pages 7 – 12, filed 02 June 2025, with respect to the rejection(s) of claim(s) 1 – 5, 7 – 10, 12 – 18, and 20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 – 5, 7 – 10, 12 – 18, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Independent claims 1, 9, and 15, as currently amended, require three signals/requests to be sent from the claimed memory system to the claimed host; a first release request, an early completion signal, and a second release request. The specification as originally filed does not describe three signals being transmitted to the host device from the memory system. Applicant has pointed to paragraphs [0029] – [0035] and [0079] of the originally filed specification as providing support for the three signals/requests, specifically the newly added “first release request regarding the program command after obtaining the program command from the host.” However, the Examiner is unable to locate any discussion of a third signal/request sent to the host from the memory system. Paragraphs [0029] – [0035] only describe an early completion signal and a single release request being sent to the host device, which equate to the “early completion signal” and “second release request” of the claimed invention. Paragraph [0075] describes two release requests, but these the two release requests again equate to the "early completion signal" and the "second release request" of the claimed invention. The specification does not describe a third signal transmitted to the host that is separate and in addition to the "early completion signal" and the "second release request." Therefore, the claimed limitation of “transmit, to the host, a first release request regarding the program command after obtaining the program command from the host” of independent claim 1, and similar limitations of independent claims 9 and 15, are not supported by the originally filed specification and are considered new matter.
Claims 2 – 5, 7, 8, 10, 12 – 14, 16 – 18, and 20 are also rejected because of their inheritance of the deficiencies of independent claims 1, 9, and 15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 5, 7, 8, 15 – 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11,494,125 (hereinafter Markus) in view of US Patent No. 11,481,145 (hereinafter Yoon), further in view of US Patent No. 10,649,898 (hereinafter Kim), and further in view of US Patent Application Publication No. 9,880,783 (hereinafter Sela).
As per claim 1, Markus teaches a data processing system, comprising a host (Markus; Figure 4 Item 300) configured to store a program command in a submission queue (Markus; Figure 4 Item 306) and store program data corresponding to the program command in a host data buffer (Markus; Figure 4 Item 305); and a memory system (Markus; Figure 4 Item 100) in communication with the host and configured to: obtain the program data stored in the host data buffer (Markus; Col 6 Line 60 – Col 7 Line 3); transmit an early completion signal (Markus; Figure 5 “RSP 1”, Figure 6 Item 640) to the host in response to resources being secured and allocated for performing a program operation corresponding to the program command and program data (Markus; Col 9 Lines 8 – 10) (Examiner’s note: The Examiner has interpreted the storing of the data in the SRAM as the securing and allocation of resources to perform the program operation since SRAM must be allocated and reserved for the data to be stored in the SRAM, and the storing of the data in the SRAM is required to perform the program operation according to the program command), after obtaining the program data corresponding to the program command, the early completion signal (Markus; Figure 5 “RSP 1”, Figure 6 Item 640) being different from a program completion signal (Markus; Figure 5 “RSP 2”, Figure 6 Item 660) being sent in response to a completion of programming of the program data in a memory group; and transmit, to the host, a release request (Markus; Figure 5 “RSP 2”, Figure 6 Item 660) for releasing the program data from the host data buffer (Markus; Col 9 Lines 19 – 24).
Markus does not teach wherein the memory system is configured to transmit, to the host, a first release request regarding the program command after obtaining the program command from the host; the program data is obtained based on an operation status of an internal buffer and releasing the program data from the internal buffer in response to the program completion signal from the memory group.
However, Yoon teaches a storage system obtaining program data based on an operation state of an internal buffer (Yoon; Col 6 Lines 40 – 51 and Col 8 Lines 18 – 30).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Markus to include the state of the internal buffer because doing so allows for ensuring available buffer space to store the data is present.
Markus in combination with Yoon does not teach the memory system is configured to transmit, to the host, a first release request regarding the program command after obtaining the program command from the host; releasing the program data from the internal buffer in response to the program completion signal from the memory group.
However, Kim teaches a storage system which releases (Kim; Figure 4 Circle 6) program data from an internal buffer (Kim; Figure 4 Item 123, Col 4 Lines 43 – 48) in response to the completion signal (Kim; Figure 4 Circle 5, Col 10 Lines 10 – 21) outputted from the memory group (Kim; Figure 4 Item 122).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Markus in combination with Yoon to include the internal buffer release because doing so allows for securing reliability of write data (Kim; Col 10 Lines 63 – 67).
Markus in combination with Yoon and Kim does not teach the memory system is configured to transmit, to the host, a first release request regarding the program command after obtaining the program command from the host.
However, Sela teaches a memory system which transmits a release request to the host regarding a program command after obtaining the program command from the host (Sela; Figure 8 Item 810).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Markus in combination with Yoon and Kim to include the release request because doing so allows for efficient buffer usage.
As per claim 2, Sela also teaches wherein a data processing system in which the host comprises: at least one input/output (I/O) core (Sela; Figure 2A Item 214) configured to control at least one pair of the submission queue (Sela; Figure 2A Item 220) and a completion queue (Sela; Figure 2A Item 224) corresponding to the submission queue, and control at least one pair of the host data buffer (Sela; Figure 2A Item 218) and a buffer release queue (Sela; Figure 2A Item 222) corresponding to the host data buffer.
As per claim 3, Markus in combination with Yoon, Kim, and Sela also teaches wherein the host is configured to send a notification regarding the program command and the program data to the memory system (Sela; Col 9 Lines 35 – 42), the at least one I/O core is configured to transfer information stored in the submission queue and the host data buffer to the memory system (Sela; Col 9 Lines 44 – 52), and the at least one I/O core is configured to a command from the submission queue based on information stored in the completion queue (Markus; Figure 6 Item 650), and release data from the host data buffer based on information stored in the buffer release queue Markus; Figure 6 Item 670) (Sela; Col 13 Lines 31 – 39).
As per claim 4, Markus in combination with Yoon and Kim also teaches wherein the memory system comprises: a memory group (Markus; Figure 4 Item 104) including non-volatile memory cells (Kim; Figure 4 Item 122); a controller (Markus; Figure 4 Item 102) (Kim; Figure 4 Item 121) configured to transfer the program data from the host to the memory group via data communication; and the internal buffer (Markus; Figure 4 Item 402) (Kim; Figure 4 Item 123, Col 4 Lines 43 – 48) configured to temporarily store the program data.
As per claim 5, Kim also teaches wherein the memory group (Kim; Figure 4 Item 122) is configured to send a program completion signal (Kim; Figure 4 Circle 5) regarding the program data in response to a completion of programming of the program data in the non-volatile memory cell (Kim; Col 10 Lines 10 – 12).
As per claims 7 and 18, Kim also teaches wherein the controller is configured to release the program data from the internal buffer after sending the program data to the memory group (Kim; Col 9 Lines 26 – 28 and Col 10 Lines 10 – 12).
As per claim 8, Yoon also teaches wherein the controller (Yoon; Figure 2 Item 206) is configured to monitor an available space in the internal buffer (Yoon; Figure 2 Item 204) for determining the operation status of the internal memory (Yoon; Col 6 Lines 40 – 51, Col 8 Lines 18 – 30).
As per claim 15, Markus teaches a memory system, comprising: a memory device (Markus; Figure 4 Item 104), including plural non-volatile memory cells, configured to perform a data input/output operation; an internal memory (Markus; Figure 4 Item 402) configured to temporarily store data associated with the data input/output operation; and a controller (Markus; Figure 4 Item 102) configured to obtain a program command associated with program data from an external device (Markus; Figure 4 Item 300), send an early completion signal (Markus; Figure 5 “RSP 1”, Figure 6 Item 640) regarding the program data to the external device in response to resources being secured and allocated for performing a program operation corresponding to the program command and program data (Markus; Col 9 Lines 8 – 10) (Examiner’s note: The Examiner has interpreted the storing of the data in the SRAM as the securing and allocation of resources to perform the program operation since SRAM must be allocated and reserved for the data to be stored in the SRAM, and the storing of the data in the SRAM is required to perform the program operation according to the program command), the early completion signal (Markus; Figure 5 “RSP 1”, Figure 6 Item 640) being different from a program completion signal (Markus; Figure 5 “RSP 2”, Figure 6 Item 660) being sent in response to a completion of programming of the program data, and send a release request (Markus; Figure 5 “RSP 2”, Figure 6 Item 660) for releasing the program data to the external device after the program data is programmed in the plural non-volatile memory cells (Markus; Figure 6 Item 670).
Markus does not teach wherein the controller is configured to send, to the external device, a first release request regarding the program command after obtaining the program command, determine a timing for obtaining the program data from the external device based on an operation state of the internal memory and releasing the program data from the internal buffer in response to the program completion signal from the memory group.
However, Yoon teaches a data storage system (Yoon; Figure 2 Item 202) in which a storage controller (Yoon; Figure 2 Item 206) determines timing for obtaining program data (Yoon; Figure 2 Items 211, 214, and 219) from an external device (Yoon; Figure 2 Item 201) based on an operation state (Yoon; Col 6 Lines 40 – 51 and Col 8 Lines 18 – 30) of the internal memory (Yoon; Figure 2 Item 204).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Markus to include the timing because doing so allows for minimizing average write throughput degradation, migrating write performance fluctuation, and containing write command latency for Write QoS handling (Yoon; Col 3 Lines 17 – 21).
Markus in combination with Yoon does not teach wherein the controller is configured to send, to the external device, a first release request regarding the program command after obtaining the program command; and releasing the program data from the internal buffer in response to the program completion signal from the memory group.
However, Kim teaches a storage system which releases (Kim; Figure 4 Circle 6) program data from an internal buffer (Kim; Figure 4 Item 123, Col 4 Lines 43 – 48) in response to the completion signal (Kim; Figure 4 Circle 5, Col 10 Lines 10 – 21) outputted from the memory group (Kim; Figure 4 Item 122).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Markus in combination with Yoon to include the internal buffer release because doing so allows for securing reliability of write data (Kim; Col 10 Lines 63 – 67).
Markus in combination with Yoon and Kim does not teach the memory system is configured to transmit, to the host, a first release request regarding the program command after obtaining the program command from the host.
However, Sela teaches a memory system which transmits a release request to the host regarding a program command after obtaining the program command from the host (Sela; Figure 8 Item 810).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Markus in combination with Yoon and Kim to include the release request because doing so allows for efficient buffer usage.
As per claim 16, Markus in combination with Yoon, Kim, and Sela also teaches wherein the controller is configured to obtain the program command from a first region of the external device (Markus; Figure 4 Item 306); obtain the program data from a second region of the external device (Markus; Figure 4 Item 305); store the early completion signal in a third region (Sela; Figure 2A Item 224) of the external device; and store the release request in a fourth region (Sela; Figure 2A Item 222) of the external device.
As per claim 17, Yoon also teach wherein the controller is further configured to monitor an available space in the internal buffer for determining the operation status of the internal buffer (Yoon; Col 6 Lines 40 – 51 and Col 8 Lines 18 – 30).
As per claim 20, Markus also teaches wherein the controller is configured to send the early completion signal to the external device after obtaining the program data from the external device (Markus; Figure 6 Item 640).
Claim(s) 9, 10, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11,494,125 (hereinafter Markus) in view US Patent No. 10,649,898 (hereinafter Kim), and further in view of US Patent Application Publication No. 9,880,783 (hereinafter Sela).
As per claim 9, Markus teaches a memory system, comprising: a storage device (Markus; Figure 4 Item 104) including plural non-volatile memory cells and configured to perform a data input/output operation; a controller (Markus; Figure 4 Item 102) in communication with the storage device and an external device (Markus; Figure 4 Item 300) and configured to control the data input/output operation, and wherein the controller is further configured to send an early completion signal (Markus; Figure 5 “RSP 1”, Figure 6 Item 640) to the external device in response to resources being secured and allocated for performing a program operation corresponding to a program command (Markus; Col 9 Lines 8 – 10) (Examiner’s note: The Examiner has interpreted the storing of the data in the SRAM as the securing and allocation of resources to perform the program operation since SRAM must be allocated and reserved for the data to be stored in the SRAM, and the storing of the data in the SRAM is required to perform the program operation according to the program command), the early completion signal (Markus; Figure 5 “RSP 1”, Figure 6 Item 640) being different from a program completion signal (Markus; Figure 5 “RSP 2”, Figure 6 Item 660) being sent in response to a completion of programming of the program data, and the controller is further configured to program data (Markus; Figure 6 Item 660), after obtaining data corresponding to the program command and send, to the external device, a release request (Markus; Figure 5 “RSP 2”, Figure 6 Item 660) for releasing the program data after the storage device completes the program operation regarding the program data (Markus; Figure 6 Item 670).
Markus does not teach wherein the controller is configured to send, to the external device, a first release request regarding a program command after obtaining the program command from the external device; and releasing the program data from an internal buffer in response to the program completion signal outputted from the storage device.
However, Kim teaches a storage system which releases (Kim; Figure 4 Circle 6) program data from an internal buffer (Kim; Figure 4 Item 123, Col 4 Lines 43 – 48) in response to the completion signal (Kim; Figure 4 Circle 5, Col 10 Lines 10 – 21) outputted from the memory group (Kim; Figure 4 Item 122).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Markus to include the internal buffer release because doing so allows for securing reliability of write data (Kim; Col 10 Lines 63 – 67).
Markus in combination with Kim does not teach wherein the controller is configured to send, to the external device, a first release request regarding a program command after obtaining the program command from the external device.
However, Sela teaches a memory system which transmits a release request to the host regarding a program command after obtaining the program command from the host (Sela; Figure 8 Item 810).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Markus in combination with Kim to include the release request because doing so allows for efficient buffer usage.
As per claim 10, Kim also teaches wherein the memory group (Kim; Figure 4 Item 122) is configured to send a program completion signal (Kim; Figure 4 Circle 5) regarding the program data in response to a completion of programming of the program data in the non-volatile memory cell (Kim; Col 10 Lines 10 – 12).
As per claim 12, Kim also teaches wherein the controller is configured to release the program data from the internal buffer after sending the program data to the memory group (Kim; Col 9 Lines 26 – 28 and Col 10 Lines 10 – 12).
As per claim 13, Sela also teaches wherein the controller is further configured to store the early completion signal in a first region (Sela; Figure 2A Item 224) in the external device and the release request in a second region (Sela; Figure 2A Item 222) in the external device.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11,494,125 (hereinafter Markus) in view US Patent No. 10,649,898 (hereinafter Kim), further in view of US Patent Application Publication No. 9,880,783 (hereinafter Sela), and further in view of US Patent No. 11,481,145 (hereinafter Yoon).
As per claim 14, Markus in combination with Kim and Sela teaches the system as described per claim 9 (see rejection of claim 9 above).
Markus in combination with Kim and Sela does not teach wherein the controller is further configured to monitor an available space of an internal memory to determine an operation state of the internal memory, and determine a timing that the program data is obtained from the external device in response to the operation state.
However, Yoon teaches a data storage system (Yoon; Figure 2 Item 202) in which a storage controller (Yoon; Figure 2 Item 206) monitors available space of an internal memory (Yoon; Figure 2 Item 204) to determine an operation state of the internal memory (Yoon; Col 6 Lines 40 – 51, Col 8 Lines 18 – 30), and determines timing for obtaining program data (Yoon; Figure 2 Items 211, 214, and 219) from an external device (Yoon; Figure 2 Item 201) based on an operation state (Yoon; Col 6 Lines 40 – 51) of the internal memory (Yoon; Figure 2 Item 204).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Markus in combination with Kim and Sela to include the timing because doing so allows for minimizing average write throughput degradation, migrating write performance fluctuation, and containing write command latency for Write QoS handling (Yoon; Col 3 Lines 17 – 21).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
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/RICHARD B FRANKLIN/Examiner, Art Unit 2181
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181