Prosecution Insights
Last updated: October 27, 2026
Application No. 17/592,741

POWER DELIVERY ARCHITECTURE USING AN INTERMEDIATE BUS CONVERTER WITH TARGET VOLTAGE TRACKING CAPABILITY

Non-Final OA §103
Filed
Feb 04, 2022
Examiner
WEINMANN, RYU-SUNG PETER
Art Unit
2859
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
5 (Non-Final)
53%
Grant Probability
Moderate
5-6
OA Rounds
0m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 53% of resolved cases
53%
Career Allowance Rate
16 granted / 30 resolved
-14.7% vs TC avg
Strong +19% interview lift
Without
With
+19.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
17 currently pending
Career history
69
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
44.8%
+4.8% vs TC avg
§102
31.9%
-8.1% vs TC avg
§112
17.9%
-22.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 30 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/27/2026 has been entered. Response to Amendment Claims 1-21 remain pending in the application, and no claims have been canceled. Response to Arguments Applicant's arguments filed 8/27/2026 have been fully considered but they are not persuasive. On page 6/8 of Remarks, applicant submits that nowhere does Wei or Batson teach controlling a system input voltage to be at a level above the voltage level of an associated battery. Wei controls its voltage, e.g., for a constant current charging mode, to go up as the battery is being charged but this battery voltage is the same as the system input voltage. Nowhere does it, or Batson, teach controlling its system input voltage to be at a voltage level that is above the battery voltage, let alone to be at a set level above the battery voltage. This is not trivial as is pointed out in Applicant's disclosure: [0026] Additionally, the battery power supplementing the power from the adapter occurs automatically, as the Vsys node is very close to the battery voltage. The switch M1 is turned on by the charger controller 52, after detecting a lower voltage on the Vsys line than that of the battery voltage. This operation enables an extremely fast response (e.g., low latency) as in the case of NVDC architecture. By keeping the system input voltage above, but close, to the battery voltage, it can be used to trigger an automatic supplemental turbo mode that is extremely fast. Wei, on the other hand, uses adapter current monitoring for its turbo activation. (See, e.g., Wei at 0054). The examiner submits that limitations such as automatic supplemental turbo mode are not recited in claim language. Wei teaches delivering power Vin to battery 104 and a load Vsys through output node 210 (Fig. 3 and ¶0034, 0036-0039, and 0058). Constant charging current mode implies a variation of voltage higher than battery voltage, which is supplied to both the battery 104 and the output node 210 which are interpreted by the examiner respectively as the associated battery and system input voltage as mentioned in the applicant’s arguments above. Voltage is supplied to both battery 104 and output node 210 as they are coupled as shown in Fig. 3 of Wei through FET 214 and switch 254. Claim Objections Claim 17 is objected to because of the following informalities: Claim 17 recites “using a reduced version of the system power input” instead of “using the system power input through a resistor divider” as is currently amended in claims 1 and 9. Appropriate correction is required. NOTE: The terms “reference input” and “feedback input”, recited in claims 1 and 9, are understood respectively as the “sensed battery voltage 72” and the “feedback voltage from the resistor divider R3/R4” as described in the amended specification [0026]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wei (US 20180076647 A1) in view of Batson (US 20080238356 A1) and Young (US 20040004463 A1). Regarding independent claim 1, Wei teaches a computing system (Fig. 1: 100) comprising: a host processor (CPU 116); and a power delivery circuit (charger 102) coupled to the host processor, the power delivery circuit including: a charger controller (Fig. 2 and ¶0023: integrated circuit 202) coupled to a battery output (battery 104), and an intermediate bus converter (Fig. 2 and ¶0025: field-effect transistors, Q1-Q4, and nodes, 206, 208, 216, and 212) coupled to an external adapter output (¶0024: input node 204), a system power input (¶0025: output node 210) and the battery output, wherein the intermediate bus converter is to vary a voltage level of the system power input based on the battery output (Fig. 3 and ¶0034, 0036-0039, and 0053: constant charging current mode implies a variation of voltage higher than battery voltage, which is supplied to both the battery and the output node 210). Wei does not explicitly teach the intermediate bus converter includes a control circuit with a reference input coupled to the battery output and a feedback input coupled to the system power input through a resistor divider circuit to control a voltage level of the system power input to track, at a higher voltage level, the battery output voltage. Batson teaches a control circuit (Fig. 3: power storage and charging module 16) with a reference input coupled to the battery output (Fig. 3: connection between battery 20 and controller 70, where controller 70 comprises analog to digital converter 74 inside microprocessor 72) and a feedback input coupled to the system power (Fig. 3 and ¶[92]: load battery 18 connected to microprocessor 72 via line 82.) to control a voltage level of the system power input to track, at a higher voltage level, the battery output voltage (Fig. 3 and ¶[84, 86, 90]: the controller 50 monitors the voltage of battery 20, and controller 70 monitors the voltage of and applies constant voltage to external battery 18. As battery 18 is being charged, its current and voltage will inherently be larger than the digital voltage value processed by the microprocessor 72 to determine voltage the battery 18). Wei and Batson teach the management of batteries as a backup source of power. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to incorporate the feedback adjustment mechanism in Batson into Wei to ensure current and voltage supplied to the load is accurately maintained. Wei and Batson do not teach a feedback input coupled to the system power input through a resistor divider circuit. Young teaches a device (Fig. 1) using an analog to digital converter 22 connected to a resistor divider 50 (¶[13]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to incorporate the resistor divider coupled to the analog to digital converter (ADC) in Young into the system of Wei modified by Batson to scale down the high input voltages so they safely fit within an ADC’s operating range and accurately measure the voltage. Regarding independent claim 9, Wei teaches a power delivery circuit (charger 102) comprising: a charger controller (Fig. 2 and ¶0023: integrated circuit 202) coupled to a battery output (battery 104); and an intermediate bus converter (Fig. 2 and ¶0025: field-effect transistors, Q1-Q4, and nodes, 206, 208, 216, and 212) coupled to an external adapter output (¶0024: input node 204), a system power input (¶0025: output node 210) and the battery output, wherein the intermediate bus converter is to vary a voltage level of the system power input based on the battery output (Fig. 3 and ¶0034, 0036-0039, and 0058: constant charging current mode implies a variation of voltage higher than battery voltage, which is supplied to both the battery and the output node 210). Wei does not explicitly teach the intermediate bus converter includes a control circuit with a reference input coupled to the battery output and a feedback input coupled to the system power input through a resistor divider circuit to control a voltage level of the system power input to track, at a higher voltage level, the battery output voltage. Batson teaches a control circuit (Fig. 3: power storage and charging module 16) with a reference input coupled to the battery output (Fig. 3: connection between battery 20 and controller 70) and a feedback input coupled to the system power input (Fig. 3 and ¶[92]: load battery 18 connected to microprocessor 72 via line 82.) to control a voltage level of the system power input to be at a predetermined level above a voltage at the battery output (Fig. 3 and ¶[94]: measured voltage value received by battery 18 (the load) is sent to the controller 80 using line 82 so the controller 70 adjusts current flowing to the battery 18 and the current converges to a value substantially equal to the charging current level). Wei and Batson teach the management of batteries as a backup source of power. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to incorporate the feedback adjustment mechanism in Batson into Wei to ensure current and voltage supplied to the load is accurately maintained. Wei and Batson do not teach a feedback input coupled to the system power input through a resistor divider circuit. Young teaches a device (Fig. 1) using an analog to digital converter 22 connected to a resistor divider 50 (¶[13]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to incorporate the resistor divider coupled to the analog to digital converter (ADC) in Young into the system of Wei modified by Batson to scale down the high input voltages so they safely fit within an ADC’s operating range and accurately measure the voltage. Regarding claim 2, Wei teaches the computing system of claim 1, wherein the voltage level of the system power input is to be one or more of a percentage value or an absolute value greater than a voltage level of the battery output (¶0058: constant charging current mode is well known in the art to have charging voltage level greater than one percentage value of the battery voltage at least at some point of time during charging). Regarding claim 3, Wei teaches the computing system of claim 1, wherein the charger controller (Fig. 2: 202) is to connect the battery output (104) to the system power input whenever a voltage level of the system power input falls below a voltage level of the battery output (¶0020 and Fig. 1: when the power adapter is not plugged into port 106, the battery 104 is used to power the load 118). Regarding claim 4, Wei teaches the computing system of claim 1, wherein the charger controller (Fig. 2: 202) is coupled to the battery output (104) via a charging power path (Fig. 2: integrated circuit 202 is couple to the charging power path in various places, 204, Q1, Q4, and 214). Regarding claim 5, Wei teaches the computing system of claim 1, wherein the intermediate bus converter (Fig. 2 and ¶0025: field-effect transistors, Q1-Q4, and nodes, 206, 208, 216, and 212) is coupled to the system power input (210) via a bypass power path (switch 252). Regarding claim 6, Wei teaches the computing system of claim 1, wherein the charger controller is a hybrid power buck-boost (HPBB) charger (Fig. 2 and ¶0006: integrated circuit 202 comprises narrow voltage DC buck-boost module 220 and turbo buck-boost module 222). Regarding claim 7, Wei teaches the computing system of claim 6, wherein the HPBB charger is to operate in a narrow voltage direct charger mode (¶0006: narrow voltage DC (NVDC) buck-boost charger mode). Regarding claim 8, Wei teaches the computing system of claim 1, wherein the adapter output is one of an extended power range output or a standard power range output (¶0031-0032: various USB adapters with limited or greater power range). Regarding claim 10, Wei teaches the power delivery circuit of claim 9, wherein the voltage level of the system power input is to be one or more of a percentage value or an absolute value greater than a voltage level of the battery output (¶0058: constant charging current mode is well known in the art to have charging voltage level greater than one percentage value of the battery voltage at least at some point of time during charging). Regarding claim 11, Wei teaches the power delivery circuit of claim 9, wherein the charger controller (Fig. 2: 202) is to connect the battery output (104) to the system power input whenever a voltage level of the system power input falls below a voltage level of the battery output (¶0020 and Fig. 1: when the power adapter is not plugged into port 106, the battery 104 is used to power the load 118). Regarding claim 12, Wei teaches the power delivery circuit of claim 9, wherein the charger controller (Fig. 2: 202) is coupled to the battery output (104) via a charging power path (Fig. 2: integrated circuit 202 is couple to the charging power path in various places, 204, Q1, Q4, and 214). Regarding claim 13, Wei teaches the power delivery circuit of claim 9, wherein the intermediate bus converter (Fig. 2 and ¶0025: field-effect transistors, Q1-Q4, and nodes, 206, 208, 216, and 212) is coupled to the system power input (210) via a bypass power path (switch 252). Regarding claim 14, Wei teaches the power delivery circuit of claim 9, wherein the charger controller is a hybrid power buck-boost (HPBB) charger (Fig. 2 and ¶0006: integrated circuit 202 comprises narrow voltage DC buck-boost module 220 and turbo buck-boost module 222). Regarding claim 15, Wei teaches the power delivery circuit of claim 14, wherein the HPBB charger is to operate in a narrow voltage direct charger mode (¶0006: narrow voltage DC (NVDC) buck-boost charger mode). Regarding claim 16, Wei teaches the power delivery circuit of claim 9, wherein the adapter output is one of an extended power range output or a standard power range output (¶0031-0032: various USB adapters with limited or greater power range). Claims 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of Batson. Regarding independent claim 17, Wei teaches a method comprising: controlling, by an intermediate bus converter (Fig. 2 and ¶0025: field-effect transistors, Q1-Q4, and nodes, 206, 208, 216, and 212), a system power input voltage (¶0025: output node 210) based on a battery output voltage (battery 102), wherein the intermediate bus converter is coupled to an external adapter output (¶0024: input node 204), the system power input (210) and the battery output (Fig. 3 and ¶0034, 0036-0039, and 0058: constant charging current mode implies a variation of voltage higher than battery voltage, which is supplied to both the battery and the output node 210); and connecting, by a charger controller, the battery output to the system power input responsive to the system power input voltage falling below a voltage level of the battery output (¶0020 and Fig. 1: when the power adapter is not plugged into port 106, the battery 104 is used to power the load 118). Wei does not teach tracking, at a higher level, a battery output voltage using a reduced version of the system power input. Batson teaches tracking, at a higher level, a battery output using a reduced version of the system power input (Fig. 3 and ¶[84, 86, 90]: the controller 50 monitors the voltage of battery 20, and controller 70 monitors the voltage of and applies constant voltage to load, external battery 18.) (Wei - Fig. 3 and ¶0034, 0036-0039, and 0058: constant charging current mode implies a variation of voltage higher than battery voltage, which is supplied to both the battery 104 and the output node 210). Wei and Batson teach the management of batteries as a backup source of power. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to incorporate the feedback adjustment mechanism in Batson into Wei to ensure current and voltage supplied to the load is accurately maintained. Regarding claim 18, Wei teaches the method of claim 17, wherein the voltage level of the system power input is one or more of a percentage value or an absolute value greater than a voltage level of the battery output (¶0058: constant charging current mode is well known in the art to have charging voltage level greater than one percentage value of the battery voltage at least at some point of time during charging). Regarding claim 19, Wei teaches the method of claim 17, wherein the charger controller is coupled to the battery output via a charging power path. Regarding claim 20, Wei teaches the method of claim 17, wherein the charger controller (Fig. 2: 202) is coupled to the battery output (104) via a charging power path (Fig. 2: integrated circuit 202 is couple to the charging power path in various places, 204, Q1, Q4, and 214). Regarding claim 21, Wei teaches the method of claim 17, further including operating the charger controller in a narrow voltage direct charger mode, wherein the charger controller is a hybrid power buck-boost (HPBB) charger (Fig. 2 and ¶0006: integrated circuit 202 comprises narrow voltage DC buck-boost module 220 and turbo buck-boost module 222). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bourilkov (US 20030155887 A1) teaches a circuit for allowing a narrow voltage range at the device power supply terminal which makes the device internal voltage regulation more efficient (¶0008) and adjustable output voltage via resistors based on feedback input of a converter (¶0020). Electrical Engineering (“ADC – Why is a voltage divider used when reading analog sensors?” < https://electronics.stackexchange.com/questions/417036/why-is-a-voltage-divider-used-when-reading-analog-sensors >, posted online 1/15/2019, 5 pages) Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryu-Sung P. Weinmann whose telephone number is (703)756-5964. The examiner can normally be reached Monday-Friday 9am-5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julian Huffman, can be reached at (571) 272-2147. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Ryu-Sung P. Weinmann/Examiner, Art Unit 2859 September 24, 2026 /JULIAN D HUFFMAN/Supervisory Patent Examiner, Art Unit 2859
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Prosecution Timeline

Show 8 earlier events
Jan 16, 2026
Non-Final Rejection mailed — §103
Apr 16, 2026
Response Filed
May 27, 2026
Final Rejection mailed — §103
Jul 21, 2026
Interview Requested
Jul 27, 2026
Response after Non-Final Action
Aug 27, 2026
Request for Continued Examination
Sep 02, 2026
Response after Non-Final Action
Oct 05, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
53%
Grant Probability
72%
With Interview (+19.0%)
3y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 30 resolved cases by this examiner. Grant probability derived from career allowance rate.

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