Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is final and is in response to claims filed on 07/16/2025 via amendment. Claims 1-6 and 8-15 are pending for examination. Claims 1-6 and 8-15 are currently amended.
Response to Arguments
Objections to the Specification
Applicant has amended specification at issue and therefore the previous objections have been withdrawn.
Rejections Under 35 U.S.C. 101
Applicant’s arguments, see Remarks 17-21, filed 07/16/2025, with respect to claims 1-6 and 8-15 have been fully considered and are persuasive. The rejections for claims 1-6 and 8-15 under 35 U.S.C. 101 have been withdrawn.
Examiner notes that the claims as amended are integrated into a practical application, and cannot be performed in the human mind. The recitation of the hardware aspects of the claims integrates it into a practical application.
Rejections Under 35 U.S.C. 103
Applicant’s arguments with respect to claims 1-6 and 8-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 1, 4-5, 11, and 13 are objected to because of the following informalities:
Claims 1 and 15 recite “the plurality of input lines of the first arithmetic circuit unit is configured to receive electrical signals corresponding to input values” and should be changed to “the plurality of input lines of the first arithmetic circuit unit [is] are configured to receive electrical signals corresponding to input values”.
“the plurality of analog circuits of the first arithmetic circuit unit is configured to multiply the input values by weight values” should be changed to “the plurality of analog circuits of the first arithmetic circuit unit [is] are configured to multiply the input values by weight values”.
“the plurality of output lines of the first arithmetic circuit unit is configured to output multiply-accumulate signals representing a sum of product values” should be “the plurality of output lines of the first arithmetic circuit unit [is] are configured to output multiply-accumulate signals representing a sum of product values”.
“the end portions of the two endmost output lines is located on a side of the second arithmetic circuit unit” should be “the end portions of the two endmost output lines [is] are located on a side of the second arithmetic circuit unit”.
“the end portions of the two endmost input lines is located on a side of the first arithmetic circuit unit” should be “the end portions of the two endmost input lines [is] are located on a side of the first arithmetic circuit unit”.
With regards to claim 4, it recites “wherein the position in the first direction of the at least one of the first end portion or the second end portion is” and should be “wherein the position in the first direction of
With regards to claim 5, it recites “wherein the position in the first direction of the at least one of the third end portion or the fourth end portion is” and should be “wherein the position in the first direction of
With regards to claim 11, it recites “wherein in the each of the plurality of arithmetic circuit units, end portions on an input side of the plurality of input lines are located” and should be changed to “wherein in
With regards to claim 13, it recites “wherein the each of the plurality of arithmetic circuit units further includes:” and should be “wherein
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Buchanan et al. (US 20180253643 A1) hereinafter Buchanan in view of the English machine translation of Watabe et al. (JP H0451382 A) hereinafter Watabe further in view of Jaffe et al. (US 6510518 B1) hereinafter Jaffe.
With regards to claim 1 Buchanan teaches An arithmetic apparatus, comprising; a plurality of arithmetic circuit units that includes a first arithmetic circuit unit and a second arithmetic circuit unit, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan [0006]: FIG. 4 is block diagram illustrating an example electronic device that includes multiple neural network layers and output circuitry for generating an analog output vector)
wherein each of the plurality of arithmetic circuit units includes a plurality of input lines, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows an arithmetic circuit unit with a plurality of input lines)
a plurality of output lines, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows an arithmetic circuit unit with a plurality of output lines)
and a plurality of analog circuits, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows an arithmetic circuit unit with a plurality of analog circuits (memristors))
the plurality of input lines of the first arithmetic circuit unit is configured to receive electrical signals corresponding to input values, respectively, (Buchanan [0011]: voltages may be applied to the rows of the crossbar array based on an input vector)
the plurality of analog circuits of the first arithmetic circuit unit is configured to multiply the input values by weight values, (Buchanan [0011]: voltages may be applied to the rows of the crossbar array based on an input vector, and an output vector may be determined based on the currents flowing through the memristors as a result of the applied voltages. An input stage may be used to generate the appropriate voltages for each row based on the input vector. For example, the crossbar array may form one layer of neurons in an artificial neural network (“ANN”), with each of the MACs forming an artificial neuron and weights for the neurons being set by adjusting the conductances of the corresponding memristors)
the plurality of output lines of the each of the plurality of arithmetic circuit units intersects with the plurality of input lines of the each of the plurality of arithmetic circuit units, respectively, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows an arithmetic circuit unit where the output lines intersect the input lines)
the plurality of output lines of the first arithmetic circuit unit is configured to output multiply-accumulate signals representing a sum of product values obtained by the multiplication of the input values by the weight values, (Buchanan [0011]: voltages may be applied to the rows of the crossbar array based on an input vector, and an output vector may be determined based on the currents flowing through the memristors as a result of the applied voltages. An input stage may be used to generate the appropriate voltages for each row based on the input vector. For example, the crossbar array may form one layer of neurons in an artificial neural network (“ANN”), with each of the MACs forming an artificial neuron and weights for the neurons being set by adjusting the conductances of the corresponding memristors; Buchanan [0013]: The column output circuitry for each column line may be configured to generate an output signal that corresponds to a sum of the currents that flow on the corresponding column line)
the multiply-accumulate signals output from the plurality of output lines of the first arithmetic circuit unit are input into the plurality of input lines of the second arithmetic circuit unit as the electrical signals corresponding to the input values, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the AN)
an arrangement of the plurality of output lines of the first arithmetic circuit unit is parallel in a direction different from the first direction, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows an arithmetic circuit unit where the output lines are parallel in a different direction to the input lines)
end portions of two endmost output lines, which are located at endmost positions of the plurality of output lines in the first arithmetic circuit unit, corresponds to a first end portion and a second end portion, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the ANN; Buchanan Fig. 4: shows the output lines of the first MAC unit)
end portions of two endmost input lines, which are located at endmost positions of the plurality of input lines in the second arithmetic circuit unit, corresponds to a third end portion and a fourth end portion, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the ANN; Buchanan Fig. 4: shows the input lines of the second MAC unit)
the end portions of the two endmost output lines is located on a side of the second arithmetic circuit unit, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the ANN; Buchanan Fig. 4: shows the output lines on the side of the second MAC unit)
the end portions of the two endmost input lines is located on a side of the first arithmetic circuit unit, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the ANN; Buchanan Fig. 4: shows the input lines on the side of the first MAC unit).
Buchanan fails to teach a first direction that is an extending direction of the plurality of input lines of the first arithmetic circuit unit is parallel to a second direction that is the extending direction of the plurality of output lines of the second arithmetic circuit unit, an arrangement of the plurality of input lines of the second arithmetic circuit unit is parallel in the direction different from the second direction, one of a position in the first direction of at least one of the first end portion or the second end portion is between a position in the first direction of the third end portion and a position in the first direction of the fourth end portion, and or the position in the first direction of at least one of the third end portion or the fourth end portion is between the position in the first direction of the first end portion and the position in the first direction of the second end portion.
However, Watabe does teach a first direction that is an extending direction of the plurality of input lines of the first arithmetic circuit unit is parallel to a second direction that is the extending direction of the plurality of output lines of the second arithmetic circuit unit, (Watabe page 3 last paragraph: An information processing device having a plurality of input lines and a plurality of output lines, and configured using a plurality of arithmetic units that input information from the plurality of input lines and obtain outputs in parallel to the plurality of output lines; Watabe Fig. 5: shows n1 and n3 being parallel to each other)
an arrangement of the plurality of input lines of the second arithmetic circuit unit is parallel in the direction different from the second direction, (Watabe page 3 last paragraph: An information processing device having a plurality of input lines and a plurality of output lines, and configured using a plurality of arithmetic units that input information from the plurality of input lines and obtain outputs in parallel to the plurality of output lines; Watabe Fig. 5: shows n2 in a different direction to n3)
one of a position in the first direction of at least one of the first end portion or the second end portion is between a position in the first direction of the third end portion and a position in the first direction of the fourth end portion (Watabe abstract: the output of VMM 1, are transmitted to the input line of the vector/matrix multiplier VMM 2 through n2-number of wirings; Watabe Fig. 5: shows the outputs of VMM1 being connected to the inputs of VMM2)
or the position in the first direction of at least one of the third end portion or the fourth end portion is between the position in the first direction of the first end portion and the position in the first direction of the second end portion (Watabe abstract: the output of VMM 1, are transmitted to the input line of the vector/matrix multiplier VMM 2 through n2-number of wirings; Watabe Fig. 5: shows the outputs of VMM1 being connected to the inputs of VMM2).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Buchanan with the inputs and outputs being parallel, and the positions of the endpoints as taught by Watabe. One of ordinary skill in the art would be motivated to make this combination because it allows for more compact placement of the circuits on the chip, saving space and reducing the distance between the circuits.
Buchanan in view of Watabe fails to teach and wires from the end portions of the two endmost output lines of the first arithmetic circuit unit to the end portions of the two endmost input lines of the second arithmetic circuit unit have equal wire lengths.
However, Jaffe does teach and wires from the end portions of the two endmost output lines of the first arithmetic circuit unit to the end portions of the two endmost input lines of the second arithmetic circuit unit have equal wire lengths (Jaffe Column 15 Lines 47-50: A circuit designer can choose to lay out component gates, wires, etc. so that input and output lines are of equal lengths and have equivalent electrical characteristics).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Buchanan in view of Watabe with the lengths of the wires as taught by Jaffe. ne of ordinary skill in the art would be motivated to make this combination because it would make the system consume less power, as asymmetries in wire routing between leakless logic gates can introduce differences in capacitance, resistance, inductance, signal timing, etc., ultimately introducing differences in externally-measurable characteristics such as electromagnetic radiation and/or power consumption as taught by Jaffe (Jaffe Column 15 Lines 42-47).
With regards to claim 2, Buchanan in view of Watabe further in view of Jaffe teaches all of the limitations of claim 1 above. Buchanan fails to teach wherein each of the position in the first direction of the third end portion and the position in the first direction of the fourth end portion is between the position in the first direction of the first end portion and the position in the first direction of the second end portion.
However, Watabe does teach wherein each of the position in the first direction of the third end portion and the position in the first direction of the fourth end portion is between the position in the first direction of the first end portion and the position in the first direction of the second end portion (Watabe abstract: the output of VMM 1, are transmitted to the input line of the vector/matrix multiplier VMM 2 through n2-number of wirings; Watabe Fig. 5: shows the outputs of VMM1 being connected to the inputs of VMM2).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Buchanan with the positions of the endpoints as taught by Watabe. One of ordinary skill in the art would be motivated to make this combination because it allows for more compact placement of the circuits on the chip, saving space and reducing the distance between the circuits.
With regards to claim 3, Buchanan in view of Watabe further in view of Jaffe teaches all of the limitations of claim 1 above. Buchanan fails to teach wherein each of the position in the first direction of the third end portion and the position in the first direction of the fourth end portion is between the position in the first direction of the first end portion and the position in the first direction of the second end portion.
However, Watabe does teach wherein each of the position in the first direction of the third end portion and the position in the first direction of the fourth end portion is between the position in the first direction of the first end portion and the position in the first direction of the second end portion (Watabe abstract: the output of VMM 1, are transmitted to the input line of the vector/matrix multiplier VMM 2 through n2-number of wirings; Watabe Fig. 5: shows the outputs of VMM1 being connected to the inputs of VMM2).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Buchanan with the positions of the endpoints as taught by Watabe. One of ordinary skill in the art would be motivated to make this combination because it allows for more compact placement of the circuits on the chip, saving space and reducing the distance between the circuits.
With regards to claim 6, Buchanan in view of Watabe further in view of Jaffe teaches all of the limitations of claim 1 above. Buchanan fails to teach wherein the direction of the plurality of output lines of the first arithmetic circuit unit is parallel to the direction of the plurality of input lines of the second arithmetic circuit unit.
However, Watabe does teach wherein the direction of the plurality of output lines of the first arithmetic circuit unit is parallel to the direction of the plurality of input lines of the second arithmetic circuit unit (Watabe page 3 last paragraph: An information processing device having a plurality of input lines and a plurality of output lines, and configured using a plurality of arithmetic units that input information from the plurality of input lines and obtain outputs in parallel to the plurality of output lines; Watabe Fig. 5: shows n1 and n3 being parallel to each other).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Buchanan with the inputs and outputs being parallel as taught by Watabe. One of ordinary skill in the art would be motivated to make this combination because it allows for more compact placement of the circuits on the chip, saving space and reducing the distance between the circuits.
With regards to claim 11, Buchanan in view of Watabe further in view of Jaffe teaches all of the limitations of claim 1 above. Buchanan further teaches wherein in the each of the plurality of arithmetic circuit units, end portions on an input side of the plurality of input lines are located in a same straight line and end portions on an output side of the plurality of output lines are located on a same straight line, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows the input lines and output lines being in parallel on a same line)
the end portions on the input side of the plurality of input lines of the plurality of arithmetic circuit units includes the end portions of the two endmost input lines of the second arithmetic circuit unit, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the ANN; Buchanan Fig. 4: shows the input lines of the second MAC unit)
the end portions on the output side of the plurality of output lines of the plurality of arithmetic circuit units includes the end portions of the two endmost output lines of the first arithmetic circuit unit, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the ANN; Buchanan Fig. 4: shows the output lines of the first MAC unit)
an arrangement of the end portions on the output side of the plurality of output lines of the first arithmetic circuit unit is side by side in a straight line direction, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows the input lines being parallel on the same straight line direction)
an arrangement of the end portions on the input side of the plurality of input lines of the second arithmetic circuit unit is side by side in a straight line direction, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the ANN; Buchanan Fig. 4: shows the input lines of the second unit being side by side in the same straight line direction).
Buchanan fails to teach and the straight line direction of the end portions on the output side of the plurality of output lines of the first arithmetic circuit unit is parallel to the straight line direction of the end portions on the input side of the plurality of input lines of the second arithmetic circuit unit.
However, Watabe teaches and the straight line direction of the end portions on the output side of the plurality of output lines of the first arithmetic circuit unit is parallel to the straight line direction of the end portions on the input side of the plurality of input lines of the second arithmetic circuit unit (Watabe page 3 last paragraph: An information processing device having a plurality of input lines and a plurality of output lines, and configured using a plurality of arithmetic units that input information from the plurality of input lines and obtain outputs in parallel to the plurality of output lines; Watabe abstract: the output of VMM 1, are transmitted to the input line of the vector/matrix multiplier VMM 2 through n2-number of wirings; Watabe Fig. 5: shows the outputs of VMM1 being connected to the inputs of VMM2).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Buchanan with the inputs of the second unit and outputs of the first unit being parallel, as taught by Watabe. One of ordinary skill in the art would be motivated to make this combination because it allows for more compact placement of the circuits on the chip, saving space and reducing the distance between the circuits.
With regards to claim 12, Buchanan in view of Watabe further in view of Jaffe teaches all of the limitations of claim 1 above. Buchanan fails to teach wherein pitches of the plurality of output lines in the first arithmetic circuit unit is different from pitches of the plurality of input lines in the second arithmetic circuit unit.
However, Watabe teaches wherein pitches of the plurality of output lines in the first arithmetic circuit unit is different from pitches of the plurality of input lines in the second arithmetic circuit unit (Watabe page 6 paragraph 13: the pitch of the input line and output line cannot be made the same).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Buchanan with the pitches of the outputs of the first circuit and inputs of the second circuit are different as taught by Watabe. One of ordinary skill in the art would be motivated to make this combination because it allows for the circuits to be different sizes to fit on the chip.
With regards to claim 13, Buchanan in view of Watabe further in view of Jaffe teaches all of the limitations of claim 1 above. Buchanan further teaches wherein the each of the plurality of arithmetic circuit units further includes: a plurality of multiplication units (Buchanan [0010]: using one or more memristors to perform a multiply portion of the multiply-accumulate operation; Buchanan Fig. 5: Shows the MAC unit with multiple multiplication units)
configured to: generate, based on the electrical signals respectively input into the plurality of input lines of the first arithmetic circuit unit, charges corresponding to the product values obtained by the multiplication of the input values by the weight values; (Buchanan [0011]: voltages may be applied to the rows of the crossbar array based on an input vector, and an output vector may be determined based on the currents flowing through the memristors as a result of the applied voltages. An input stage may be used to generate the appropriate voltages for each row based on the input vector. For example, the crossbar array may form one layer of neurons in an artificial neural network (“ANN”), with each of the MACs forming an artificial neuron and weights for the neurons being set by adjusting the conductances of the corresponding memristors; Buchanan [0013]: The column output circuitry for each column line may be configured to generate an output signal that corresponds to a sum of the currents that flow on the corresponding column line)
and output the charges as the multiply-accumulate signals to the plurality of output lines of the first arithmetic circuit unit; (Buchanan [0011]: voltages may be applied to the rows of the crossbar array based on an input vector, and an output vector may be determined based on the currents flowing through the memristors as a result of the applied voltages. An input stage may be used to generate the appropriate voltages for each row based on the input vector. For example, the crossbar array may form one layer of neurons in an artificial neural network (“ANN”), with each of the MACs forming an artificial neuron and weights for the neurons being set by adjusting the conductances of the corresponding memristors; Buchanan [0013]: The column output circuitry for each column line may be configured to generate an output signal that corresponds to a sum of the currents that flow on the corresponding column line)
an accumulation unit configured to accumulate the charges corresponding to the product values respectively output to the plurality of output lines of the first arithmetic circuit unit; (Buchanan [0019]: The column output circuits 300 may each include an integration capacitor Cint; Cint is the accumulator)
a charging unit configured to charge the accumulation unit in which the charges corresponding to the product values are accumulated (Buchanan [0019]: that is to, when the switch S1 is closed, flow an integration current to or from an electrode of the integration capacitor Cint whose magnitude mirrors a current flowing on the corresponding column line CL. When it is said that the current mirroring circuitry 301 is to flow an integration current “to or from” an electrode of the integration capacitor Cint (or the like), this should be understood to mean that one possible configuration of the current mirroring circuitry 301 is to flow current to the integration capacitor Cint while another possible configuration of the current mirroring circuitry 301 is to flow current away from the integration capacitor Cint; the current mirroring circuitry is the charging unit)
in which the charges corresponding to the product values are accumulated (Buchanan [0019]: flow an integration current to or from an electrode of the integration capacitor Cint whose magnitude mirrors a current flowing on the corresponding column line CL)
and an output unit configured to: perform after the charging unit starts charging, threshold determination on a voltage retained by the accumulation unit with a specific threshold; (Buchanan [0043]: also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits; Buchanan [0025] (equation 3): ΔVc=Vdd-Vc)
and output, based on the threshold determination on the voltage retained by the accumulation unit, a multiply-accumulate result signal including information regarding a timing corresponding to the sum of the product values obtained by the multiplication of the input values by the weight values (Buchanan [0025] (equation 3): ΔVc=Vdd-Vc = (tint / Cint) Σ(Vxn GRLn); The equation shows the timing tint based on the threshold determination).
With regards to claim 14, Buchanan in view of Watabe further in view of Jaffe teaches all of the limitations of claim 13 above. Buchanan further teaches the plurality of multiplication units includes at least one of a positive weight multiplication unit or a negative weight multiplication unit, (Buchanan [0049]: Each of the column output circuits 310 corresponds to a pair of column lines comprising one of the positive-weight column lines CL+ and its corresponding negative-weight column line CL−; Buchanan Fig. 5: shows positive weight multiplication units and negative weight multiplication units)
the positive weight multiplication unit is configured to: generate a positive weight charge corresponding to a first product value obtained by the multiplication of an input value of the input values by a positive weight value, (Buchanan [0049]: Each of the column output circuits 310 corresponds to a pair of column lines comprising one of the positive-weight column lines CL+; Buchanan [0011]: voltages may be applied to the rows of the crossbar array based on an input vector, and an output vector may be determined based on the currents flowing through the memristors as a result of the applied voltages. An input stage may be used to generate the appropriate voltages for each row based on the input vector. For example, the crossbar array may form one layer of neurons in an artificial neural network (“ANN”), with each of the MACs forming an artificial neuron and weights for the neurons being set by adjusting the conductances of the corresponding memristors)
wherein the product values includes the first product value, and the weight values includes the positive weight value; (Buchanan [0049]: Each of the column output circuits 310 corresponds to a pair of column lines comprising one of the positive-weight column lines CL+; Buchanan [0011]: voltages may be applied to the rows of the crossbar array based on an input vector, and an output vector may be determined based on the currents flowing through the memristors as a result of the applied voltages. An input stage may be used to generate the appropriate voltages for each row based on the input vector. For example, the crossbar array may form one layer of neurons in an artificial neural network (“ANN”), with each of the MACs forming an artificial neuron and weights for the neurons being set by adjusting the conductances of the corresponding memristors)
and output the positive weight charge to the positive charge output line as a first multiply-accumulate signal of the multiply-accumulate signals, (Buchanan [0050]: The column output circuits 310 of FIG. 5 are similar to the column output circuits 300 described above, with the exception that second mirroring circuitry 302 is provided in addition to the first mirroring circuitry 301, and the integration capacitor Cint is connected to an intermediate voltage Vdd/2 rather than to the high voltage Vdd. In particular, the first mirroring circuitry 301 may be connected to the corresponding positive-weight column line CL+, while the second mirroring circuitry 302 may be connected to the corresponding negative-weight column line CL−... the switch S3 that selectively connects the second current mirroring circuitry 302 to the integration capacitor Cint may be a separate device from the switch S1; This allows for Cint to only accumulate the positive weight results)
the negative weight multiplication unit is configured to: generate a negative weight charge corresponding to a second product value obtained by the multiplication of the input value by a values includes the negative weight value; (Buchanan [0049]: Each of the column output circuits 310 corresponds to a pair of column lines comprising one of the positive-weight column lines CL+ and its corresponding negative-weight column line CL−; Buchanan [0011]: voltages may be applied to the rows of the crossbar array based on an input vector, and an output vector may be determined based on the currents flowing through the memristors as a result of the applied voltages. An input stage may be used to generate the appropriate voltages for each row based on the input vector. For example, the crossbar array may form one layer of neurons in an artificial neural network (“ANN”), with each of the MACs forming an artificial neuron and weights for the neurons being set by adjusting the conductances of the corresponding memristors)
and output the negative weight charge to the negative charge output line as a second multiply-accumulate signal of the multiply-accumulate signals, (Buchanan [0050]: The column output circuits 310 of FIG. 5 are similar to the column output circuits 300 described above, with the exception that second mirroring circuitry 302 is provided in addition to the first mirroring circuitry 301, and the integration capacitor Cint is connected to an intermediate voltage Vdd/2 rather than to the high voltage Vdd. In particular, the first mirroring circuitry 301 may be connected to the corresponding positive-weight column line CL+, while the second mirroring circuitry 302 may be connected to the corresponding negative-weight column line CL−... the switch S3 that selectively connects the second current mirroring circuitry 302 to the integration capacitor Cint may be a separate device from the switch S1; This allows for Cint to only accumulate the negative weight results)
the accumulation unit includes a positive charge accumulation unit and a negative charge accumulation unit, (Buchanan [0050]: The column output circuits 310 of FIG. 5 are similar to the column output circuits 300 described above, with the exception that second mirroring circuitry 302 is provided in addition to the first mirroring circuitry 301, and the integration capacitor Cint is connected to an intermediate voltage Vdd/2 rather than to the high voltage Vdd. In particular, the first mirroring circuitry 301 may be connected to the corresponding positive-weight column line CL+, while the second mirroring circuitry 302 may be connected to the corresponding negative-weight column line CL−… the switch S3 that selectively connects the second current mirroring circuitry 302 to the integration capacitor Cint may be a separate device from the switch S1)
the positive charge accumulation unit is configured to accumulate the positive weight charge output to the positive charge output line by the positive weight multiplication unit, (Buchanan [0050]: The column output circuits 310 of FIG. 5 are similar to the column output circuits 300 described above, with the exception that second mirroring circuitry 302 is provided in addition to the first mirroring circuitry 301, and the integration capacitor Cint is connected to an intermediate voltage Vdd/2 rather than to the high voltage Vdd. In particular, the first mirroring circuitry 301 may be connected to the corresponding positive-weight column line CL+)
the negative charge accumulation unit is configured to accumulate the negative weight charge output to the negative charge output line by the negative weight multiplication unit, (Buchanan [0050]: while the second mirroring circuitry 302 may be connected to the corresponding negative-weight column line CL−… the switch S3 that selectively connects the second current mirroring circuitry 302 to the integration capacitor Cint may be a separate device from the switch S1)
the charging unit is further configured to charge the positive charge accumulation unit and the negative charge accumulation unit, (Buchanan [0050]: The column output circuits 310 of FIG. 5 are similar to the column output circuits 300 described above, with the exception that second mirroring circuitry 302 is provided in addition to the first mirroring circuitry 301, and the integration capacitor Cint is connected to an intermediate voltage Vdd/2 rather than to the high voltage Vdd. In particular, the first mirroring circuitry 301 may be connected to the corresponding positive-weight column line CL+, while the second mirroring circuitry 302 may be connected to the corresponding negative-weight column line CL−)
and the output unit is further configured to: perform the threshold determination with respect to each of the positive charge accumulation unit and the negative charge accumulation unit with the specific threshold; (Buchanan [0043] also includes an output circuit 600 that generates the analog output values y′.sub.1-y′.sub.M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits; Buchanan [0025] (equation 3): ΔVc=Vdd-Vc)
and output, based on the threshold determination with respect to the each of the positive charge accumulation unit and the negative charge accumulation unit the multiply-accumulate result signal (Buchanan [0043] also includes an output circuit 600 that generates the analog output values y′.sub.1-y′.sub.M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits; Buchanan [0025] (equation 3): ΔVc=Vdd-Vc).
With regards to claim 15, Buchanan teaches A multiply-accumulate system, comprising: a plurality of arithmetic circuit units that includes a first arithmetic circuit unit and a second arithmetic circuit unit; (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan [0006]: FIG. 4 is block diagram illustrating an example electronic device that includes multiple neural network layers and output circuitry for generating an analog output vector)
And a network circuit configured by connection of the plurality of arithmetic circuit units, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the AN; Buchanan Fig. 4: shows multiple MAC units connected together through output circuits)
wherein each of the plurality of arithmetic circuit units includes a plurality of input lines, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows an arithmetic circuit unit with a plurality of input lines)
a plurality of output lines, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows an arithmetic circuit unit with a plurality of output lines)
and a plurality of analog circuits, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows an arithmetic circuit unit with a plurality of analog circuits (memristors))
the plurality of input lines of the first arithmetic circuit unit is configured to receive electrical signals corresponding to input values, respectively, (Buchanan [0011]: voltages may be applied to the rows of the crossbar array based on an input vector)
the plurality of analog circuits of the first arithmetic circuit unit is configured to multiply the input values by weight values, (Buchanan [0011]: voltages may be applied to the rows of the crossbar array based on an input vector, and an output vector may be determined based on the currents flowing through the memristors as a result of the applied voltages. An input stage may be used to generate the appropriate voltages for each row based on the input vector. For example, the crossbar array may form one layer of neurons in an artificial neural network (“ANN”), with each of the MACs forming an artificial neuron and weights for the neurons being set by adjusting the conductances of the corresponding memristors)
the plurality of output lines of the each of the plurality of arithmetic circuit units intersects with the plurality of input lines of the each of the plurality of arithmetic circuit units, respectively, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows an arithmetic circuit unit where the output lines intersect the input lines)
the plurality of output lines of the first arithmetic circuit unit is configured to output multiply-accumulate signals representing a sum of product values obtained by the multiplication of the input values by the weight values, (Buchanan [0011]: voltages may be applied to the rows of the crossbar array based on an input vector, and an output vector may be determined based on the currents flowing through the memristors as a result of the applied voltages. An input stage may be used to generate the appropriate voltages for each row based on the input vector. For example, the crossbar array may form one layer of neurons in an artificial neural network (“ANN”), with each of the MACs forming an artificial neuron and weights for the neurons being set by adjusting the conductances of the corresponding memristors; Buchanan [0013]: The column output circuitry for each column line may be configured to generate an output signal that corresponds to a sum of the currents that flow on the corresponding column line)
the multiply-accumulate signals output from the plurality of output lines of the first arithmetic circuit unit are input into the plurality of input lines of the second arithmetic circuit unit as the electrical signals corresponding to the input values, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the AN)
an arrangement of the plurality of output lines of the first arithmetic circuit unit is parallel in a direction different from the first direction, (Buchanan [0011]: example electronic devices may include a memristor crossbar array, which may include column lines, row lines, and memristors arranged in an array with each of the memristors connected between one of the column lines and one of the row lines; Buchanan Fig. 5: shows an arithmetic circuit unit where the output lines are parallel in a different direction to the input lines)
end portions of two endmost output lines, which are located at endmost positions of the plurality of output lines in the first arithmetic circuit unit, corresponds to a first end portion and a second end portion, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the ANN; Buchanan Fig. 4: shows the output lines of the first MAC unit)
end portions of two endmost input lines, which are located at endmost positions of the plurality of input lines in the second arithmetic circuit unit, corresponds to a third end portion and a fourth end portion, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the ANN; Buchanan Fig. 4: shows the input lines of the second MAC unit)
the end portions of the two endmost output lines is located on a side of the second arithmetic circuit unit, (Buchanan [0043]: The example electronic device 10 also includes an output circuit 600 that generates the analog output values y′1-y′M (collectively the analog output vector Y′) based on the voltage differences ΔVC of the column output circuits 300_1 to 300_M, respectively, and feeds the analog output values y′1-y′M to an input stage 2001 of a second layer 1001 of the ANN; Buchanan Fig. 4: shows the output lines on the side o