DETAILED ACTION
This communication is in response to Application No. 17/599,565 originally filed 09/29/2021. The Request for Continued Examination and Amendment presented on 12/17/2025 which provides amendments to claims 1, 3, 5, 8, 9, 11, 13, 17 and adds new claim 19 is hereby acknowledged.
Currently claims 1-19 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/17/2025 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/17/2025 have been fully considered but they are not persuasive.
The Office notes that Zhou expressly teaches providing a linear approach for adjusting the horizontal period. As a linear approach and corresponding formulae’s are provided, The Office considers this an express teaching of “linear equipartition” as claimed. Zhou also expressly stats “where the adjustment charging duration of every gate line in each gate line group are identical” and “each gate line group includes at least one gate line”. See Zhou at [0005], [0012], [0067-0080] and also Figure 8. For these reasons The Office does not find Applicants arguments persuasive and the rejection will be maintained.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhou et al. U.S. Patent Application Publication No. 2020/0388235 A1 hereinafter Zhou.
Consider Claim 1:
Zhou discloses a driving method of a display panel, including: (Zhou, See Abstract.)
detecting, by using at least two detection points provided within the display panel along a column of sub- pixels in the display panel, a first charging time required for one of the sub-pixels at each of the at least two detection points to be fully charged to a target voltage common for the column of sub-pixels; (Zhou, [0041], [0012], [0008], “Optionally, the pre-storing the adjustment charging duration of each gate line, further includes: determining a width of H-Blank data of video data corresponding to a i.sup.th row of gate lines to be adjusted, to obtain a resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines; determining the adjustment charging duration of the i.sup.th row of gate lines based on the resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines.”)
wherein the at least two detection points comprise detection points for detecting a first row of sub-pixels and a last row of sub-pixels, respectively; (Zhou, [0005], [0012], [0067-0080], [0012], “A driving circuitry of a display panel is further provided in the present disclosure, where the display panel includes Y gate lines, the Y gate lines are divided into a plurality of gate line groups based on a scanning sequence of the Y gate lines, and each gate line group includes at least one gate line; the driving circuitry includes: a determination circuit, configured to determine an i.sup.th gate line to be scanned, where 1≤i≤Y; an adjustment circuit, configured to adjust an original charging duration of a scanning signal corresponding to the i.sup.th gate line to an adjustment charging duration, where the adjustment charging duration of every gate line in each gate line group are identical, and the adjustment charging durations of respective gate line groups gradually increase in a direction away from a source driver; and an output circuit, configured to output the scanning signal corresponding to the i.sup.th gate line to the i.sup.th gate line, based on the adjustment charging duration of the i.sup.th gate line.”)
determining the first charging time as a second charging time for a row of sub- pixels in which the one of the sub-pixels is located: (Zhou, [0064], “Refer to FIG. 7 which is a schematic view of video data of which a width of H-Blank data is adjusted in at least one embodiment of the present disclosure, the widths of H-Blank data of every two rows of video data are adjusted. That is, the Y gate lines are divided into Y/2 gate line groups, i.e., each gate line group includes two gate lines, and the widths of the H-Blank data of the two gate lines within the same gate line group are the same.”)
obtaining a third charging time required for each row of sub-pixels in the display panel to reach a target voltage based by means of linear equipartition on the second charging time corresponding to each of the at least two detection points, wherein the third charging time refers to a duration from a time when the each row of the sub-pixels starts to scan to a time when a voltage of the each row of the sub-pixels reaches the target voltage; (Zhou, [0009-0011], [0067-0080], [0103], “The H-Blank data width adjustment circuit may calculate the resultant width of H-Blank data of video data corresponding to the i.sup.th row of gate lines through a linear algorithm.” [0009], “Optionally, the determining the width of the H-Blank data of the video data corresponding to the i.sup.th row of gate lines to be adjusted, to obtain the resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines, further includes: determining a width k0 of the H-Blank data of the video data corresponding to a first row of gate lines to be reduced; calculating a resultant width n(1) of the H-Blank data corresponding to the first row of gate lines, where n(1)=HB−k0; calculating a difference Δk between the resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines and n(1)”)
adjusting a duty ratio of a scan drive signal corresponding to each row of the sub- pixels by adjusting a length of an on time of the scan drive signal to be equal to that of the third charging time, based on the third charging time, to obtain adjusted scan drive signals with different duty cycles along the column of sub-pixels; and (Zhou, [0094], [0051], “Step S44: adjusting the original charging duration of the scanning signal corresponding to the i.sup.th gate line to the acquired adjustment charging duration of the i.sup.th gate line; and”)
scanning the display panel row by row based on the adjusted scan drive signals, so that sub-pixels at respective positions of the display panel are capable of being fully charged to the target voltage. (Zhou, [0057-0094], [0052], “Step S45: outputting the scanning signal corresponding to the i.sup.th gate line to the i.sup.th gate line based on the adjustment charging duration of the i.sup.th gate line.”)
Consider Claim 2:
Zhou discloses the driving method of the display panel of claim 1, wherein the step of obtaining the third charging time required for each row of the sub- pixels in the display panel to reach the target voltage comprises: obtaining the second charging times required for rows of sub-pixels respectively at two adjacent ones of the at least two detection points to reach the target voltage; and determining the third charging time required for each row of the sub-pixels between two adjacent detection points in the at least two detection points to reach the target voltage based on the second charging times required for the rows of sub-pixels respectively at the two adjacent ones of the at least two detection points. (Zhou, [0041], [0012], “A driving circuitry of a display panel is further provided in the present disclosure, where the display panel includes Y gate lines, the Y gate lines are divided into a plurality of gate line groups based on a scanning sequence of the Y gate lines, and each gate line group includes at least one gate line; the driving circuitry includes: a determination circuit, configured to determine an i.sup.th gate line to be scanned, where 1≤i≤Y; an adjustment circuit, configured to adjust an original charging duration of a scanning signal corresponding to the i.sup.th gate line to an adjustment charging duration, where the adjustment charging duration of every gate line in each gate line group are identical, and the adjustment charging durations of respective gate line groups gradually increase in a direction away from a source driver; and an output circuit, configured to output the scanning signal corresponding to the i.sup.th gate line to the i.sup.th gate line, based on the adjustment charging duration of the i.sup.th gate line.”)
Consider Claim 3:
Zhou discloses the driving method of the display panel of claim 2, wherein the at least two detection points comprise a first detection point and a second detection point, the first detection point is configured to detect the second charging time required for the first row of the sub-pixels in the display panel to reach the target voltage, and the second detection point is configured to detect the second charging time required for the last row of the sub-pixels in the display panel to reach the target voltage. (Zhou, [0041], “Referring to FIG. 3 which is a schematic view of a display device in at least one embodiment of the present disclosure. As shown in FIG. 3, based on a scanning sequence of the Y gate lines, the Y gate lines on the display panel are divided into m gate lines group (gate line group 1, gate line group 2 . . . gate line group m), where each gate line group includes 12 gate lines (not all shown in the figure), where gate line group 1 is closest to the source driver, and gate line group m is farthest from the source driver. The adjustment charging duration of respective gate line groups gradually increases in a direction away from a source driver. It can be seen from FIG. 3 that the adjustment charging duration of the gate line group 1 is t1, the adjustment charging duration of the gate line group m is tm, where tm is greater than t1, and the difference between the two is Δt.”)
Consider Claim 4:
Zhou discloses the driving method of the display panel of claim 3, wherein the at least two detection points further comprise a third detection point, and the third detection point is configured to detect the second charging time required for a middle row of sub-pixels located between the first row of the sub-pixels and the last row of the sub-pixels to reach the target voltage. (Zhou, [0041], “Referring to FIG. 3 which is a schematic view of a display device in at least one embodiment of the present disclosure. As shown in FIG. 3, based on a scanning sequence of the Y gate lines, the Y gate lines on the display panel are divided into m gate lines group (gate line group 1, gate line group 2 . . . gate line group m), where each gate line group includes 12 gate lines (not all shown in the figure), where gate line group 1 is closest to the source driver, and gate line group m is farthest from the source driver. The adjustment charging duration of respective gate line groups gradually increases in a direction away from a source driver. It can be seen from FIG. 3 that the adjustment charging duration of the gate line group 1 is t1, the adjustment charging duration of the gate line group m is tm, where tm is greater than t1, and the difference between the two is Δt.”)
Consider Claim 5:
Zhou discloses the driving method of the display panel of claim 2, wherein the display panel comprises a plurality of scan line groups, and each of the scan line groups comprises at least two scan lines; (Zhou, [0032], “In the related art, as shown in FIG. 1, a liquid crystal display device includes a time sequence controller (TCON), a source driver, a gate driver and a display panel. The display panel is provided with lengthways data lines (not shown), transversal gate lines (not shown) and pixel array in the pixel areas defined by the gate lines and data lines. The time sequence controller is used for outputting a clock signal CPV, an enablement signal OE and a frame trigger signal STV to the gate driver, so as to control the gate driver to charge a corresponding pixel in the pixel array through a corresponding gate line, thereby transmitting video data output by the source driver to the corresponding pixel and displaying an image.”)
the step of determining the third charging time required for each row of the sub- pixels between the two adjacent detection points in the at least two detection points to reach the target voltage based on the second charging times required for the rows of the sub-pixels at the two adjacent ones of the at least two detection points comprises: obtaining a fourth charging time required for the sub-pixels corresponding to each scan line group between the two adjacent ones of the at least two detection points to reach the target voltage by means of linear equipartition to based on the second charging times required for the rows of the sub-pixels at the two adjacent ones of the at least two detection points to reach the target voltage and a number of the scan line groups between the two adjacent ones of the at least two detection points; wherein the rows of the sub-pixels respectively corresponding to respective ones of the scan lines in a same one of the scan line groups require a same charging time to reach the target voltage. (Zhou, [0064], “Refer to FIG. 7 which is a schematic view of video data of which a width of H-Blank data is adjusted in at least one embodiment of the present disclosure, the widths of H-Blank data of every two rows of video data are adjusted. That is, the Y gate lines are divided into Y/2 gate line groups, i.e., each gate line group includes two gate lines, and the widths of the H-Blank data of the two gate lines within the same gate line group are the same.”)
Consider Claim 6:
Zhou discloses the driving method of the display panel of claim 5, wherein the step of adjusting the duty ratio of the scan drive signal corresponding to each row of the sub-pixels based on the third charging time comprises: adjusting a duty ratio of a clock signal corresponding to each scan line group based on the fourth charging time required for the sub-pixels corresponding to each scan line group to reach the target voltage, to obtain an adjusted clock signal; and (Zhou, [0064], “Refer to FIG. 7 which is a schematic view of video data of which a width of H-Blank data is adjusted in at least one embodiment of the present disclosure, the widths of H-Blank data of every two rows of video data are adjusted. That is, the Y gate lines are divided into Y/2 gate line groups, i.e., each gate line group includes two gate lines, and the widths of the H-Blank data of the two gate lines within the same gate line group are the same.”)
adjusting duty ratios of scan drive signals respectively corresponding to respective ones of the scan lines in each scan line group in turn based on the adjusted clock signal corresponding to each scan line group. (Zhou, [0061], “In at least one embodiment of the present disclosure, the original charging duration of each gate line may be adjusted by adjusting the width of the H-Blank data corresponding to each gate line. Specifically, the greater the width of the H-Blank data, the longer the original charging duration of the gate line may be, while the smaller the width of the H-Blank data, the shorter the original charging duration of the gate line may be.”)
Consider Claim 7:
Zhou discloses the driving method of the display panel of claim 6, wherein a high level duration of the clock signal corresponding to each scan line group is same as high level durations of the scan drive signals respectively corresponding to a plurality of rows of sub-pixels connected to the scan line group. (Zhou, [0059], “It can be seen from FIG. 5 that, the width of valid data and H-Blank data in each row of video data received by the time sequence controller is fixed. In each row of video data, the number of valid data is X, the width of the H-Blank is HB, and the unit is Pixel. The video data corresponding to each frame of image has Y rows. The total amount of video data corresponding to each frame is (X+HB)*Y. The total amount of H-Blank data is HB*Y.”)
Consider Claim 8:
Zhou discloses the driving method of the display panel of claim 6, wherein from a first one of the scan line groups to a last one of the scan line groups, the duty ratio of the clock signal gradually increases, and duty ratios of the clock signals respectively corresponding to respective ones of the scan lines in a same one of the scan line groups are same as each other. (Zhou, [0079], [0078], [0103], “The H-Blank data width adjustment circuit may calculate the resultant width of H-Blank data of video data corresponding to the i.sup.th row of gate lines through a linear algorithm. Optionally, the H-Blank data width adjustment circuit further includes: a first determination circuit, configured to determine a width k0 of the H-Blank data of the video data corresponding to a first row of gate lines to be reduced; a first calculation circuit, configured to calculate a resultant width n(1) of the H-Blank data corresponding to the first row of gate lines, where n(1)=HB−k0; a second calculation circuit, configured to calculate a difference Δk between the resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines and n(1), where {equation 18} Y is a total number of the gate lines of the display panel, and m is a total number of the gate line groups; and a fourth calculation circuit, configured to calculate a resultant width n(i) of the H-Blank data corresponding to the i.sup.th row of gate lines, where n(i)=HB−k0+Δk, HB is a width of the H-Blank data of the video data corresponding to the i.sup.th row of gate lines.”)
Consider Claim 9:
Zhou discloses a display panel, including: (Zhou, See Abstract.)
a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixels arranged in an array; wherein the sub-pixels in a same row in the plurality of sub-pixels are connected to a same scan line, and the sub-pixels in a same column in the plurality of sub-pixels are connected to a same data line; and the display panel further comprises: (Zhou, [0032], “In the related art, as shown in FIG. 1, a liquid crystal display device includes a time sequence controller (TCON), a source driver, a gate driver and a display panel. The display panel is provided with lengthways data lines (not shown), transversal gate lines (not shown) and pixel array in the pixel areas defined by the gate lines and data lines. The time sequence controller is used for outputting a clock signal CPV, an enablement signal OE and a frame trigger signal STV to the gate driver, so as to control the gate driver to charge a corresponding pixel in the pixel array through a corresponding gate line, thereby transmitting video data output by the source driver to the corresponding pixel and displaying an image.”)
a detection module, configured to: detect, by using at least two detection points provided within the display panel along a column of sub-pixels in the plurality of sub-pixels, a first charging time required for one of the sub-pixels at each of the at least two detection points to be fully charged to a target voltage common for the column of sub-pixels; (Zhou, [0041], [0012], [0008], “Optionally, the pre-storing the adjustment charging duration of each gate line, further includes: determining a width of H-Blank data of video data corresponding to a i.sup.th row of gate lines to be adjusted, to obtain a resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines; determining the adjustment charging duration of the i.sup.th row of gate lines based on the resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines.”)
wherein the at least two detection points comprise detection points for detecting a first row of sub-pixels and a last row of sub-pixels, respectively; (Zhou, [0005], [0012], [0067-0080], [0012], “A driving circuitry of a display panel is further provided in the present disclosure, where the display panel includes Y gate lines, the Y gate lines are divided into a plurality of gate line groups based on a scanning sequence of the Y gate lines, and each gate line group includes at least one gate line; the driving circuitry includes: a determination circuit, configured to determine an i.sup.th gate line to be scanned, where 1≤i≤Y; an adjustment circuit, configured to adjust an original charging duration of a scanning signal corresponding to the i.sup.th gate line to an adjustment charging duration, where the adjustment charging duration of every gate line in each gate line group are identical, and the adjustment charging durations of respective gate line groups gradually increase in a direction away from a source driver; and an output circuit, configured to output the scanning signal corresponding to the i.sup.th gate line to the i.sup.th gate line, based on the adjustment charging duration of the i.sup.th gate line.”)
determine the first charging time as a second charging time for a row of sub-pixels in which the one of the sub-pixels is located in the plurality of sub- pixels; and (Zhou, [0064], “Refer to FIG. 7 which is a schematic view of video data of which a width of H-Blank data is adjusted in at least one embodiment of the present disclosure, the widths of H-Blank data of every two rows of video data are adjusted. That is, the Y gate lines are divided into Y/2 gate line groups, i.e., each gate line group includes two gate lines, and the widths of the H-Blank data of the two gate lines within the same gate line group are the same.”)
obtain a third charging time required for each row of the sub-pixels in the plurality of sub-pixels to reach a target voltage by means of linear equipartition based on the second charging time corresponding to each of the at least two detection points, wherein the third charging time refers to a duration from a time when the each row of the sub-pixels starts to scan to a time when a voltage of the each row of the sub-pixels reaches the target voltage; (Zhou, [0009-0011], [0067-0080], [0103], “The H-Blank data width adjustment circuit may calculate the resultant width of H-Blank data of video data corresponding to the i.sup.th row of gate lines through a linear algorithm.” [0009], “Optionally, the determining the width of the H-Blank data of the video data corresponding to the i.sup.th row of gate lines to be adjusted, to obtain the resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines, further includes: determining a width k0 of the H-Blank data of the video data corresponding to a first row of gate lines to be reduced; calculating a resultant width n(1) of the H-Blank data corresponding to the first row of gate lines, where n(1)=HB−k0; calculating a difference Δk between the resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines and n(1)”)
a timing control module, configured to adjust a duty ratio of a scan drive signal corresponding to each row of the sub-pixels by adjusting a length of an on time of the scan drive signal to be equal to that of the third charging time, based on the third charging time, to obtain adjusted scan drive signals with different duty cycles along the column of sub-pixels; and (Zhou, [0094], [0051], “Step S44: adjusting the original charging duration of the scanning signal corresponding to the i.sup.th gate line to the acquired adjustment charging duration of the i.sup.th gate line; and”)
a gate driving module, configured to scan the plurality of sub-pixels row by row based on the adjusted scan drive signals, so that sub-pixels at respective positions of the display panel are capable of being fully charged to the target voltage. (Zhou, [0057-0094], [0052], “Step S45: outputting the scanning signal corresponding to the i.sup.th gate line to the i.sup.th gate line based on the adjustment charging duration of the i.sup.th gate line.”)
Consider Claim 10:
Zhou discloses the display panel of claim 9, wherein the detection module comprises: a calculation module, configured to calculate the third charging time required for each row of the sub-pixels between two adjacent detection points in the at least two detection points to reach the target voltage based on the second charging times required for the rows of sub-pixels respectively at the two adjacent ones of the at least two detection points. (Zhou, [0012], “A driving circuitry of a display panel is further provided in the present disclosure, where the display panel includes Y gate lines, the Y gate lines are divided into a plurality of gate line groups based on a scanning sequence of the Y gate lines, and each gate line group includes at least one gate line; the driving circuitry includes: a determination circuit, configured to determine an i.sup.th gate line to be scanned, where 1≤i≤Y; an adjustment circuit, configured to adjust an original charging duration of a scanning signal corresponding to the i.sup.th gate line to an adjustment charging duration, where the adjustment charging duration of every gate line in each gate line group are identical, and the adjustment charging durations of respective gate line groups gradually increase in a direction away from a source driver; and an output circuit, configured to output the scanning signal corresponding to the i.sup.th gate line to the i.sup.th gate line, based on the adjustment charging duration of the i.sup.th gate line.”)
Consider Claim 11:
Zhou discloses the display panel of claim 10, wherein the at least two detection points comprise a first detection point and a second detection point, the first detection point is configured to detect the second charging time required for the first row of sub-pixels in the display panel to reach the target voltage, and the second detection point is configured to detect the second charging time required for the last row of sub-pixels in the display panel to reach the target voltage. (Zhou, [0041], “Referring to FIG. 3 which is a schematic view of a display device in at least one embodiment of the present disclosure. As shown in FIG. 3, based on a scanning sequence of the Y gate lines, the Y gate lines on the display panel are divided into m gate lines group (gate line group 1, gate line group 2 . . . gate line group m), where each gate line group includes 12 gate lines (not all shown in the figure), where gate line group 1 is closest to the source driver, and gate line group m is farthest from the source driver. The adjustment charging duration of respective gate line groups gradually increases in a direction away from a source driver. It can be seen from FIG. 3 that the adjustment charging duration of the gate line group 1 is t1, the adjustment charging duration of the gate line group m is tm, where tm is greater than t1, and the difference between the two is Δt.”)
Consider Claim 12:
Zhou discloses the display panel of claim 11, wherein the at least two detection points further comprise a third detection point, and the third detection point is configured to detect the second charging time required for a middle row of sub-pixels located between the first row of sub-pixels and the last row of sub-pixels to reach the target voltage. (Zhou, [0041], “Referring to FIG. 3 which is a schematic view of a display device in at least one embodiment of the present disclosure. As shown in FIG. 3, based on a scanning sequence of the Y gate lines, the Y gate lines on the display panel are divided into m gate lines group (gate line group 1, gate line group 2 . . . gate line group m), where each gate line group includes 12 gate lines (not all shown in the figure), where gate line group 1 is closest to the source driver, and gate line group m is farthest from the source driver. The adjustment charging duration of respective gate line groups gradually increases in a direction away from a source driver. It can be seen from FIG. 3 that the adjustment charging duration of the gate line group 1 is t1, the adjustment charging duration of the gate line group m is tm, where tm is greater than t1, and the difference between the two is Δt.”)
Consider Claim 13:
Zhou discloses the display panel of claim 11, wherein the display panel comprises a plurality of scan line groups, and each of the scan line groups comprises at least two scan lines, and (Zhou, [0064], “Refer to FIG. 7 which is a schematic view of video data of which a width of H-Blank data is adjusted in at least one embodiment of the present disclosure, the widths of H-Blank data of every two rows of video data are adjusted. That is, the Y gate lines are divided into Y/2 gate line groups, i.e., each gate line group includes two gate lines, and the widths of the H-Blank data of the two gate lines within the same gate line group are the same.”)
rows of the sub-pixels respectively corresponding to respective ones of the scan lines in a same one of the scan line groups require a same charging time to reach the target voltage. (Zhou, [0079], [0078], [0103], “The H-Blank data width adjustment circuit may calculate the resultant width of H-Blank data of video data corresponding to the i.sup.th row of gate lines through a linear algorithm. Optionally, the H-Blank data width adjustment circuit further includes: a first determination circuit, configured to determine a width k0 of the H-Blank data of the video data corresponding to a first row of gate lines to be reduced; a first calculation circuit, configured to calculate a resultant width n(1) of the H-Blank data corresponding to the first row of gate lines, where n(1)=HB−k0; a second calculation circuit, configured to calculate a difference Δk between the resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines and n(1), where {equation 18} Y is a total number of the gate lines of the display panel, and m is a total number of the gate line groups; and a fourth calculation circuit, configured to calculate a resultant width n(i) of the H-Blank data corresponding to the i.sup.th row of gate lines, where n(i)=HB−k0+Δk, HB is a width of the H-Blank data of the video data corresponding to the i.sup.th row of gate lines.”)
Consider Claim 14:
Zhou discloses the display panel of claim 13, wherein a high level duration of a clock signal corresponding to each scan line group is same as high level durations of the scan drive signals respectively corresponding to a plurality of rows of sub-pixels connected to the scan line group. (Zhou, [0064], “Refer to FIG. 7 which is a schematic view of video data of which a width of H-Blank data is adjusted in at least one embodiment of the present disclosure, the widths of H-Blank data of every two rows of video data are adjusted. That is, the Y gate lines are divided into Y/2 gate line groups, i.e., each gate line group includes two gate lines, and the widths of the H-Blank data of the two gate lines within the same gate line group are the same.”)
Consider Claim 15:
Zhou discloses the display panel of claim 13, wherein the calculation module is further configured to obtain a fourth charging time required for the sub-pixels corresponding to each scan line group between the two adjacent ones of the at least two detection points to reach the target voltage by means of linear equipartition based on the second charging times required for the rows of the sub-pixels at the two adjacent ones of the at least two detection points to reach the target voltage and a number of the scan line groups between the two adjacent ones of the at least two detection points. (Zhou, [0066-0090], [0066], “Method one: calculating the width n(i) of H-Blank data of video data corresponding to the i.sup.th row of gate lines through a linear algorithm.”)
Consider Claim 16:
Zhou discloses the display panel of claim 15, wherein the timing control module comprises: an adjustment module, configured to adjust a duty ratio of a clock signal corresponding to each scan line group based on the fourth charging time required for the sub-pixels corresponding to each scan line group to reach the target voltage, to obtain an adjusted clock signal. (Zhou, [0064], “Refer to FIG. 7 which is a schematic view of video data of which a width of H-Blank data is adjusted in at least one embodiment of the present disclosure, the widths of H-Blank data of every two rows of video data are adjusted. That is, the Y gate lines are divided into Y/2 gate line groups, i.e., each gate line group includes two gate lines, and the widths of the H-Blank data of the two gate lines within the same gate line group are the same.”)
Consider Claim 17:
Zhou discloses the display panel of claim 16, wherein from a first one of the scan line groups to a last one of the scan line (Zhou, [0079], [0078], [0103], “The H-Blank data width adjustment circuit may calculate the resultant width of H-Blank data of video data corresponding to the i.sup.th row of gate lines through a linear algorithm. Optionally, the H-Blank data width adjustment circuit further includes: a first determination circuit, configured to determine a width k0 of the H-Blank data of the video data corresponding to a first row of gate lines to be reduced; a first calculation circuit, configured to calculate a resultant width n(1) of the H-Blank data corresponding to the first row of gate lines, where n(1)=HB−k0; a second calculation circuit, configured to calculate a difference Δk between the resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines and n(1), where {equation 18} Y is a total number of the gate lines of the display panel, and m is a total number of the gate line groups; and a fourth calculation circuit, configured to calculate a resultant width n(i) of the H-Blank data corresponding to the i.sup.th row of gate lines, where n(i)=HB−k0+Δk, HB is a width of the H-Blank data of the video data corresponding to the i.sup.th row of gate lines.”)
Consider Claim 18:
Zhou discloses the driving method of the display panel of claim 1, wherein the detection point is an actual detection point or a virtual detection point. (Zhou, [0041], [0012], “A driving circuitry of a display panel is further provided in the present disclosure, where the display panel includes Y gate lines, the Y gate lines are divided into a plurality of gate line groups based on a scanning sequence of the Y gate lines, and each gate line group includes at least one gate line; the driving circuitry includes: a determination circuit, configured to determine an i.sup.th gate line to be scanned, where 1≤i≤Y; an adjustment circuit, configured to adjust an original charging duration of a scanning signal corresponding to the i.sup.th gate line to an adjustment charging duration, where the adjustment charging duration of every gate line in each gate line group are identical, and the adjustment charging durations of respective gate line groups gradually increase in a direction away from a source driver; and an output circuit, configured to output the scanning signal corresponding to the i.sup.th gate line to the i.sup.th gate line, based on the adjustment charging duration of the i.sup.th gate line.”)
Consider Claim 19:
Zhou discloses the driving method of the display panel of claim 5, wherein a difference in charging time between any two adjacent ones of the scan line groups is a constant value. (Zhou, [0005], [0012], [0067-0080], [0103], “The H-Blank data width adjustment circuit may calculate the resultant width of H-Blank data of video data corresponding to the i.sup.th row of gate lines through a linear algorithm. Optionally, the H-Blank data width adjustment circuit further includes: a first determination circuit, configured to determine a width k0 of the H-Blank data of the video data corresponding to a first row of gate lines to be reduced; a first calculation circuit, configured to calculate a resultant width n(1) of the H-Blank data corresponding to the first row of gate lines, where n(1)=HB−k0; a second calculation circuit, configured to calculate a difference Δk between the resultant width of the H-Blank data corresponding to the i.sup.th row of gate lines and n(1), where {equation 18} Y is a total number of the gate lines of the display panel, and m is a total number of the gate line groups; and a fourth calculation circuit, configured to calculate a resultant width n(i) of the H-Blank data corresponding to the i.sup.th row of gate lines, where n(i)=HB−k0+Δk, HB is a width of the H-Blank data of the video data corresponding to the i.sup.th row of gate lines.”)
Conclusion
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626