DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 11/31/2025 has been acknowledged. Claims 1, 9, and 17 have been amended. Claims 6-7 and 18-19 are canceled. No new matter has been added.
This office action considers claims 1-5, 8-9, 17 and 20 pending for prosecution and are examined on their merits.
Drawings
Corrected drawings sheets for Figs. 2, 3, 4, 5, 7, and 9, are accepted. All objections to drawings are withdrawn.
Response to Arguments
Applicant’s arguments filed 11/31/2025 with respect to the rejection of claim 1 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. Rejections for claims 2-5 and 8-9, being dependent on claim 1 have been withdrawn.
Applicant’s arguments filed 11/31/2025 with respect to the rejection of claim 17 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20230217711 A1 – hereinafter Lin) in view of Jiang et al. (US 20170301707 A1 – hereinafter Jiang), and Choi et al. (US 20170194402 A1 – hereinafter Choi).
Regarding independent claim 17, Lin teaches
(Currently amended) A display panel (100 – Fig. 1C – [0029] – “display
device 100”) a plurality of pixel regions ([0032] – “the display device 100 may include a plurality of sub-pixels” – hereinafter ‘px’), wherein the display panel (100) comprises:
a substrate (101 – Fig. 3C – [0029] – “substrate 101”);
a thin-film transistor layer (Fig. 1C annotated, see below – hereinafter ‘12’)
provided on the substrate (101), and comprising a first stacking structure (Fig. 1C annotated, see below – hereinafter ‘de1’) and a second stacking structure (Fig. 1C annotated, see below – hereinafter ‘de2’), wherein the first stacking structure (de1) comprises a plurality of conductive layers (Fig. 1C annotated, see below – [0031] – “thin film transistor 120 may include a metal oxide semiconductor 121, a gate electrode 122 overlapping the metal oxide semiconductor 121, a source electrode 124 and a drain electrode 123 which may be electrically connected with the metal oxide semiconductor 121, but the present disclosure is not limited thereto” – both of these are conductive layers, hereinafter ‘12a’) arranged in different layers (Fig. 1C shows this), and a plurality of insulating layers (Fig. 1C annotated, see below – [0031] – “The materials of the first inorganic layer 110, the second inorganic layer 112 and/or the third inorganic layer 113 may include insulating materials” – hereinafter ‘12b’), the second stacking structure (de2) comprises a compensation layer (Fig. 1C annotated, see below – [0031] – “first electrode 131” – this corresponds to the compensation layer, hereinafter ‘12c’) and the insulating layers (12b), wherein a number of the conductive layers (12a) of the first stacking structure (de1) is greater than a number of conductive layers (Fig. 1C annotated shows this) of the second stacking structure (de2); and
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a height (Fig. 2B annotated, see below – hereinafter ‘h1) of the first stacking structure (de1) is greater than or equal to a height (Fig. 2B annotated, see below – hereinafter ‘h2) of the second stacking structure (de2), and
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the compensation layer (12c) is used to increase the height (h2) of the second stacking structure (de2);
a planarization layer (140 – fig. 1C – [0034] – “first organic layer 140 may be
used as a planarization layer”) covering the thin-film transistor layer (12);
an electrode layer (151 – Fig. 1C – 0032] – “anode 151” – this corresponds to
the electrode layer) provided on the planarization layer (140);
a pixel definition layer (142 – Fig. 1C – [0034] – “patterned second organic
layer 142 may be used as a pixel definition layer (PDL)”) provided on the electrode layer (142 – Fig. 1C shows this), and comprising a plurality of openings (Fig. 1C annotated, see above – [0032] – “although only one blue organic light emitting diode 150 is illustrated in FIG. 1B and in FIG. 1C, the display device 100 may include a plurality of blue organic light emitting diodes 150” – hereinafter ‘OP’), one of the openings (OP) is corresponding to one of the pixel regions (px – Fig. 1C annotated, see above – [0032] – “When the sub-pixel is a blue sub-pixel, the blue blocking layer 170 and/or the wavelength conversion element 166 may optionally not be provided (or disposed) on the blue organic light emitting diode 150 in the sub-pixel”), and the first stacking structure (de1) the second stacking structure (de2) provided corresponding to a same opening; and
a light-emitting layer (153 – Fig. 1C – [0034] – “light emitting layer 153”)
provided in the opening (OP – Fig. 1C annotated shows this);
wherein a surface of the first stacking structure away from the substrate is flush with a surface of the second stacking structure away from the substrate; and a portion of a surface of the planarization layer (140) away from the substrate (101) corresponding to the pixel regions ([0032] – “the display device 100 may include a plurality of sub-pixels” – hereinafter ‘px’) is a planar surface (Fig. 1C shows this);
wherein the compensation layer is provided at any position on the substrate in a stacking direction of the second stacking structure (de2);
wherein the compensation layer has multiple layers, and the multiple layers of the compensation layer are arranged in different layers from each other in the stacking direction of the second stacking structure (de2).
Lin does not expressly disclose the other limitations of claim 17.
However, in an analogous art, Jiang teaches
the compensation layer is used to increase ([0023] – “the thickness compensation layer 30 can be used to compensate a thickness difference between a region of the display substrate assembly corresponding to the first region and a region of the display substrate assembly corresponding to the second region, so that the thickness of the region of the assembled display substrate assembly corresponding to the first region is the same as that of the region of the assembled display substrate assembly corresponding to the second region, that is, the thickness of the assembled display substrate assembly everywhere is the same. As a result, non-uniformity of the thickness of the assembled display substrate assembly, caused due to non-uniformity of thicknesses of the metal functional layers located on the display substrate assembly, can be eliminated, to improve quality of a picture displayed in the display apparatus”) the height of the second stacking structure,
wherein a surface of the first stacking structure (Fig. 2 annotated, see below – hereinafter ‘a1’) away from the substrate (11 – Fig. 2 – [0023] – “substrate 11) is flush with a surface of the second stacking structure (Fig. 2 annotated, see below – hereinafter ‘a2’) away from the substrate (11),
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wherein the compensation layer (30 – fig 4) is provided at any position on the substrate (11) in a stacking direction of the second stacking structure;
wherein the compensation layer (30) has multiple layers (31 and 32 – Fig. 4 – [0032] – “compensation layer 30 further comprises a first compensation layer 31 and a second compensation layer 32”), and the multiple layers of the compensation layer (31 and 32) are arranged in different layers from each other in the stacking direction ([0032] – “the first compensation layer 31 is located between the gate lines 12 within the first region and the first substrate 11, and the first compensation layer 31 is in contact respectively with the gate lines 12 and the first substrate 11. The first compensation layer 31 is provided in the same layer with the common electrode layer 13 but is not connected to the common electrode layer 13. The second compensation layer 32 is located on the passivation layer 15 within the first region, and the second compensation layer 32 is provided in the same layer with the pixel electrode layer 16 but is not connected to the pixel electrode layer 16” – Fig. 4 shows this) of the second stacking structure.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate using the height of the compensation structure to adjust the height of the stacking structure as taught by Jiang into Lin.
An ordinary artisan would have been motivated to use the known technique of Jiang in the manner set forth above to produce the predictable result [0023] – “As a result, non-uniformity of the thickness of the assembled display substrate assembly, caused due to non-uniformity of thicknesses of the metal functional layers located on the display substrate assembly, can be eliminated, to improve quality of a picture displayed in the display apparatus.”
Lin and Jiang do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Choi teaches
corresponding to a same opening (Fig. 2 shows the transistor and the capacitor corresponding to the same opening).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the position of the stacking structures to correspond to the same opening as taught by Choi into Lin and Jiang.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result of [0008] – “an organic light-emitting display apparatus that has improved image quality by reducing an influence of current generated from a parasitic capacitor to an organic light-emitting device.”
Regarding claim 20, Lin, as modified by Jiang, and Choi, teaches claim 17 from which claim 20 depends. Lin further teaches
(Original) The display panel according to claim 17, wherein the
second stacking structure (de2) further comprises at least one of the conductive layers (12a – Fig. 1C annotated, see above, shows this).
Allowable Subject Matter
Claims 1-5 and 8-9 are allowed. Claims 10-16 are rejoined and allowed.
The following is an examiner’s statement of reasons for allowance:
In reference to claim 1, the prior art of record to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding the second compensation structure comprises a second compensation layer and the insulating layers, a number of the conductive layers of the second compensation structure is less than a number of the conductive layers of the first compensation structure in combination with the other recited limitations.
Claims 2-5 and 8-16 depend on claim 1 and are therefore allowable.
The closest prior art of record is Lin et al. (US 20230217711 A1 – hereinafter Lin). Lin teaches the second compensation structure (de2) comprises a second compensation layer and the insulating layers, a number of the conductive layers of the second compensation structure is less than a number of the conductive layers of the first compensation structure.
This specific structure of a second compensation layer and the insulating layers, a number of the conductive layers is not taught or rendered obvious by the prior art of record. The instant application states that the beneficial effect of the flatness of the of the planarization layer is [0002] – “One of the main influencing factors of ink spreadability is the substrate flatness in the pixel area. It is required that the maximum step difference of the entire pixel area is as small as possible. If the ink spreadability is uneven, and goes beyond the specification, the film thickness will be uneven after drying, which will eventually affect the luminescence effect, so the flatness of the planarization layer of IJP-AMOLED has a more demanding requirement.”
Any comments considered necessary by applicant must be submitted no later
than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Pertinent Art
For the benefits of the Applicant, US 20220255047 A1 and US 20170117345 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the compensation layer structure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897