DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to a claim of priority to international application PCT/CN2021/101402 filed on June 22nd, 2021, and a claim of foreign priority to Chinese application CN202110629782.5 filed on June 7th, 2021. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) filed on May 8th, 2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Group I (Claims 1-16) in the reply filed on is acknowledged. The arguments made in the traversal document are found to be persuasive. The restriction requirement filed on April 20, 2026 stands withdrawn and all claims are being considered on their merits
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-14, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (JP2010177450A).
Regarding claim 9;
Yamazaki et al. teaches in Figure 1A a semiconductor device (e.g. Fig. 1A ref 150), comprising: a substrate (e.g. Fig. 1A ref 100; Description [0026] “1 includes a substrate 100 (e.g., a substrate having an insulating surface)…”), a source (e.g. Fig. 1A ref 104; Description [0026] “…the first electrode layer 104 functions as a source electrode…”), a drain (e.g. Fig. 1A ref 124; Description [0026] “…he second electrode layer 124 functions as a drain electrode…”), a semiconductor layer (e.g. Fig. 1A ref 114; Description [0070] “the oxide semiconductor layer 114 serves as an active layer of the transistor.”), and a gate (e.g. Fig. 1A ref 126; Description [0026] …” the third electrode layer 126 functions as a gate electrode.”), wherein a main body portion of the source and a main body portion of the drain are disposed on different faces (e.g. Fig. 1A; as can been seen in the examiner markup, the drain and source are disposed on different faces of the active layer and thus their main body portions are also disposed on different faces), the semiconductor layer is disposed on a side of the main body portion of the source (e.g. Fig. 1A; as can be seen by the examiner markup, the active layer is disposed on at least one side of a main body portion of the source layer), at least part of the semiconductor layer covers the main body portion of the source (e.g. Fig. 1A; as can be seen by the examiner markup, the active layer is disposed so as to overlap at least partly with a main body portion of the source layer), and the gate is disposed on a non-main body portion of the source (e.g. Fig. 1A; as can be seen by the examiner markup, the gate layer is present on the non-main body portion of the source layer).
PNG
media_image1.png
479
781
media_image1.png
Greyscale
Regarding claim 10;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein the semiconductor layer comprises a main body portion (e.g. interpreted under BRI as the portion most significantly in electrical contact with an electrode layer) and an extension portion (e.g. interpreted under BRI as the portion not significantly in electrical contact with electrode layers), the main body portion of the semiconductor layer is disposed on the source (e.g. Fig. 1A; see examiner markup), and the extension portion of the semiconductor layer is disposed on a surface of the substrate (e.g. Fig. 1A, See examiner markup below).
PNG
media_image2.png
479
781
media_image2.png
Greyscale
Regarding claim 11;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein one end of the drain is disposed on the semiconductor layer (e.g. Fig. 1A, See examiner markup below), and an other end of the drain is disposed on the surface of the substrate (e.g. Fig. 1A, See examiner markup below).
PNG
media_image3.png
479
781
media_image3.png
Greyscale
Regarding claim 12;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein a projection of the gate on the substrate is located outside a projection of the drain on the substrate (e.g. Fig. 1A, See examiner markup below).
PNG
media_image4.png
479
781
media_image4.png
Greyscale
Regarding claim 13;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein the semiconductor device further comprises an insulating layer (e.g. Fig. 1A ref 126), one end of the insulating layer is disposed on the source (e.g. Fig. 1A, see examiners markup), and an other end of the insulating layer is disposed on the main body portion of the drain (e.g. Fig. 1A, see examiners markup).
PNG
media_image5.png
479
781
media_image5.png
Greyscale
Regarding claim 14;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein the insulating layer comprises a bent portion disposed between one end of the insulating layer and the other end of the insulating layer (e.g. Fig. 1A, see examiners markup), the bent portion is in contact with a side face of the semiconductor layer as well as a side face of the drain (e.g. Fig. 1A, see examiners markup), and the gate is disposed on the insulating layer corresponding to the non-main body portion of the source and is in contact with the bent portion (e.g. Fig. 1A, see examiners markup).
PNG
media_image6.png
479
793
media_image6.png
Greyscale
• Regarding claim 16;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein the semiconductor device further comprises a first contact electrode and a second contact electrode (e.g. Fig. 1A), the first contact electrode is disposed on a side of the drain (e.g. Fig. 1A ref 116; Description [0070] “ …the second low-resistance semiconductor layer 116…[has] an effect of realizing ohmic contact with the electrode layer.” ), and the second contact electrode is disposed on a side of the source (e.g. Fig. 1A ref 112; Description [0070] “ …the first low-resistance semiconductor layer 112…[has] an effect of realizing ohmic contact with the electrode layer.”).
PNG
media_image7.png
633
1034
media_image7.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8, and 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (JP2010177450A) in view of Luo (CN109166911A) for the following reasons:
Regarding claim 1;
Yamazaki et al. teaches in Figure 1A a semiconductor device (e.g. Fig. 1A ref 150), comprising: a substrate (e.g. Fig. 1A ref 100; Description [0026] “1 includes a substrate 100 (e.g., a substrate having an insulating surface)…”), a source (e.g. Fig. 1A ref 104; Description [0026] “…the first electrode layer 104 functions as a source electrode…”), a drain (e.g. Fig. 1A ref 124; Description [0026] “…he second electrode layer 124 functions as a drain electrode…”), a semiconductor layer (e.g. Fig. 1A ref 114; Description [0070] “the oxide semiconductor layer 114 serves as an active layer of the transistor.”), and a gate (e.g. Fig. 1A ref 126; Description [0026] …” the third electrode layer 126 functions as a gate electrode.”), wherein a main body portion of the source and a main body portion of the drain are disposed on different faces (e.g. Fig. 1A; as can been seen in the examiner markup, the drain and source are disposed on different faces of the active layer and thus their main body portions are also disposed on different faces), the semiconductor layer is disposed on a side of the main body portion of the source (e.g. Fig. 1A; as can be seen by the examiner markup, the active layer is disposed on at least one side of a main body portion of the source layer), at least part of the semiconductor layer covers the main body portion of the source (e.g. Fig. 1A; as can be seen by the examiner markup, the active layer is disposed so as to overlap at least partly with a main body portion of the source layer), and the gate is disposed on a non-main body portion of the source (e.g. Fig. 1A; as can be seen by the examiner markup, the gate layer is present on the non-main body portion of the source layer).
PNG
media_image1.png
479
781
media_image1.png
Greyscale
Yamazaki et al. is silent to the drain being arranged in a grid shape as claimed.
However, Luo teaches in figure 6 a drain electrode (e.g. ref 5b) formed with hollow patterns (e.g. ref 7).
PNG
media_image8.png
781
829
media_image8.png
Greyscale
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to modify the source electrode taught in Yamazaki et al. to be formed in the grid pattern taught by Luo because such an arrangement reduces the face area of the electrode which can decrease the parasitic capacitance between overlapping electrodes, as well as improve the flexibility of the device if used in a flexible electronic application (e.g. [Detailed ways, Example 2]).
Regarding claim 2;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein the semiconductor layer comprises a main body portion and an extension portion, the main body portion of the semiconductor layer is disposed on the source (e.g. Fig. 1A, See examiner markup below), and the extension portion of the semiconductor layer is disposed on a surface of the substrate (e.g. Fig. 1A, See examiner markup below).
PNG
media_image2.png
479
781
media_image2.png
Greyscale
Regarding claim 3;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein one end of the drain is disposed on the semiconductor layer (e.g. Fig. 1A, See examiner markup below), and an other end of the drain is disposed on the surface of the substrate (e.g. Fig. 1A, See examiner markup below).
PNG
media_image3.png
479
781
media_image3.png
Greyscale
Regarding claim 4;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein a projection of the gate on the substrate is located outside a projection of the drain on the substrate (e.g. Fig. 1A, See examiner markup below).
PNG
media_image4.png
479
781
media_image4.png
Greyscale
Regarding claim 5;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein the semiconductor device further comprises an insulating layer (e.g. Fig. 1A ref 118), one end of the insulating layer is disposed on the source (e.g. Fig. 1A, see examiners markup), and another end of the insulating layer is disposed on the main body portion of the drain (e.g. Fig. 1A, see examiners markup).
PNG
media_image5.png
479
781
media_image5.png
Greyscale
Regarding claim 6;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein the insulating layer comprises a bent portion disposed between one end of the insulating layer and the other end of the insulating layer (e.g. Fig. 1A, see examiners markup), the bent portion is in contact with a side face of the semiconductor layer as well as a side face of the drain (e.g. Fig. 1A, see examiners markup), and the gate is disposed on the insulating layer corresponding to the non-main body portion of the source and is in contact with the bent portion (e.g. Fig. 1A, see examiners markup).
PNG
media_image6.png
479
793
media_image6.png
Greyscale
Regarding claim 7 and 15;
Yamazaki et al. is silent to the source being arranged in a grid shape as claimed.
However, Luo teaches in figure 6 a source electrode (e.g. ref 5a) formed with hollow patterns (e.g. ref 7).
PNG
media_image8.png
781
829
media_image8.png
Greyscale
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to modify the source electrode taught in Yamazaki et al. to be formed in the grid pattern taught by Luo because such an arrangement reduces the face area of the electrode which can decrease the parasitic capacitance between overlapping electrodes, as well as improve the flexibility of the device if used in a flexible electronic application (e.g. [Detailed ways, Example 2]).
Regarding claim 8;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein the semiconductor device further comprises a first contact electrode and a second contact electrode (e.g. Fig. 1A), the first contact electrode is disposed on a side of the drain (e.g. Fig. 1A ref 116; ), and the second contact electrode is disposed on a side of the source (e.g. Fig. 1A ref 114; ).
PNG
media_image7.png
633
1034
media_image7.png
Greyscale
Regarding claim 19;
Yamazaki et al. teaches a method of preparing a semiconductor device but is silent to the drain being disposed in a grid shape during its preparation as claimed.
However, Luo teaches photomask process which directly etches a grid pattern onto deposited electrode layers (e.g. [Detailed ways, Example 1] “the hollow pattern 7 is formed in the source electrode 5a and the drain electrode 5b by a photomask process…after depositing the metal thin film layer for forming the source/drain electrodes, the metal thin film layer is directly etched by using a photomask process…”).
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to modify the method of preparing a semiconductor device taught in Yamazaki et al. to include the photomask process which directly etches the grid pattern onto a source/drain electrode taught by Luo because such an electrode arrangement reduces the face area of the electrode which can decrease the parasitic capacitance between overlapping electrodes, as well as improve the flexibility of the device if used in a flexible electronic application (e.g. [Detailed ways, Example 2]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (JP2010177450A)
Regarding claim 17;
Yamazaki et al. teaches a method for preparing a semiconductor device (e.g. Fig. 1A), the method comprising steps of: B100: preparing a first insulating layer on a substrate (e.g. Description [0054] “As the substrate 100…[a] substrate in which the surface of a conductive substrate made of a conductor is coated with an insulating material can be used.”); B101: preparing a source on the first insulating layer (e.g. Fig.2A-2B; Description [0053] “First, the conductive layer 102 is formed over the substrate 100 (for example, a substrate having an insulating surface) (see FIG. 2A).” [0057] “Next, a resist mask is formed over the conductive layer 102, and the conductive layer 102 is selectively etched using the resist mask, so that the first electrode layer 104 is formed (see FIG. 2B)” [0058] “The first electrode layer 104 functions as a source electrode (or a drain electrode) of the transistor.”); B102: preparing a semiconductor layer on a side of the source, wherein at least part of the semiconductor layer covers a main body portion of the source (e.g. Fig. 2C-2D; Description [0059] “Next, a first low-resistance semiconductor layer 106, an oxide semiconductor layer 108, and a second low-resistance semiconductor layer 110 are sequentially stacked to cover the first electrode layer 104 (FIG. 2C)” [0070] “Next, a resist mask is formed over the second low-resistance semiconductor layer 110, and the first low-resistance semiconductor layer 106, the oxide semiconductor layer 108, and the second low-resistance semiconductor layer 110 are formed using the resist mask. Are selectively etched, so that the first low-resistance semiconductor layer 112, the oxide semiconductor layer 114, and the second low-resistance semiconductor layer 116 are formed (see FIG. 2D).”); B103: preparing a drain on the semiconductor layer (e.g. Fig. 3C-3D); B104: preparing a second insulating layer on the source, wherein the second insulating layer is in contact with a side face of the semiconductor layer and at least part of the drain (e.g. Fig.3A-3B); and B105: preparing a gate on the second insulating layer (e.g. Fig. 3C-3D; ).
PNG
media_image9.png
709
518
media_image9.png
Greyscale
PNG
media_image10.png
818
571
media_image10.png
Greyscale
Yamazaki et al. is silent to at least part of a projection of the drain on the main body portion of the source overlapping the main body portion of the source as claimed.
PNG
media_image1.png
479
781
media_image1.png
Greyscale
PNG
media_image11.png
467
793
media_image11.png
Greyscale
However, Yamazaki et al. teaches another embodiment of a semiconductor device which can be produced using the same manufacturing method steps (e.g. Fig. 8A; Description [0112] “The semiconductor device illustrated in FIG. 8 is an example of a modification of the semiconductor device illustrated in FIG. 1…” [0117] “Note that the functions of the semiconductor device and the transistor 150 are not significantly changed.”).
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to modify the method taught in Yamazaki et al. Figures 2-3 to produce the semiconductor device taught in Yamazaki et al. Figure 8A by increasing the etching width of the insulating layer removal step (i.e. removing a greater portion of insulating layer and exposing more of the active/semiconductor layer) because a device produced by this method would have shortened channel lengths due to the vertical stacking and overlap of electrode layers (e.g. Description [0084]) leading to improved performance for the resulting device.
Claims 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (JP2010177450A) in view of Choi et al. (J. Korean Phys. Soc. 72, 939–942 (2018)) for the following reasons:
Regarding claim 18;
Yamazaki et al. teaches a method for preparing a semiconductor device (e.g. Fig. 1A), the method comprising steps of: B100: preparing a first insulating layer on a substrate (e.g. Description [0054] “As the substrate 100…[a] substrate in which the surface of a conductive substrate made of a conductor is coated with an insulating material can be used.”); B101: preparing a source on the first insulating layer (e.g. Fig.2A-2B; Description [0053] “First, the conductive layer 102 is formed over the substrate 100 (for example, a substrate having an insulating surface) (see FIG. 2A).” [0057] “Next, a resist mask is formed over the conductive layer 102, and the conductive layer 102 is selectively etched using the resist mask, so that the first electrode layer 104 is formed (see FIG. 2B)” [0058] “The first electrode layer 104 functions as a source electrode (or a drain electrode) of the transistor.”); B102: preparing a semiconductor layer on a side of the source, wherein at least part of the semiconductor layer covers a main body portion of the source (e.g. Fig. 2C-2D; Description [0059] “Next, a first low-resistance semiconductor layer 106, an oxide semiconductor layer 108, and a second low-resistance semiconductor layer 110 are sequentially stacked to cover the first electrode layer 104 (FIG. 2C)” [0070] “Next, a resist mask is formed over the second low-resistance semiconductor layer 110, and the first low-resistance semiconductor layer 106, the oxide semiconductor layer 108, and the second low-resistance semiconductor layer 110 are formed using the resist mask. Are selectively etched, so that the first low-resistance semiconductor layer 112, the oxide semiconductor layer 114, and the second low-resistance semiconductor layer 116 are formed (see FIG. 2D).”); B103: preparing a drain on the semiconductor layer (e.g. Fig. 3C-3D); B104: preparing a second insulating layer on the source, wherein the second insulating layer is in contact with a side face of the semiconductor layer and at least part of the drain (e.g. Fig.3A-3B); and B105: preparing a gate on the second insulating layer (e.g. Fig. 3C-3D).
Yamazaki et al. is silent to the semiconductor layer processing step B102 using a blue laser annealing process as claimed but does teach that during the preparation of the semiconductor layer a heat treatment process is performed (e.g. Description [0082] “…heat treatment is performed at 350 ° C. for one hour in a nitrogen atmosphere. By this heat treatment, the semiconductor characteristics of the oxide semiconductor layer 114 can be improved.”).
However, Choi et al. teaches a laser annealing process using high-power blue laser diodes (e.g. II. Experiment “The a-Si layer was annealed using a blue laser diode with a 450-nm wavelength in the CW mode in a nitrogen atmosphere.”).
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to modify the heat treatment step taught by Yamazaki et al. to be performed by the laser annealing process taught by Choi et al. because such low-temperature annealing processes not only provide improved material properties of the resulting device (e.g. III. Results and Discussion), but also exploit the advantageous characteristics of semiconducting laser technology (i.e. improved lifetime, low maintenance cost, stable power output, etc.) (e.g. III. Results and Discussion, IV. Conclusion)
Regarding claim 20;
Yamazaki et al. further teaches in Figure 1A a semiconductor device wherein one end of the drain is disposed on the semiconductor layer (e.g. Fig. 1A, see rejections of claims 3 and 11), and an other end of the drain is disposed on the surface of the substrate (e.g. Fig. 1A, see rejections of claims 3 and 11).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights