DETAILED ACTION
This action is pursuant to claims filed on December 7, 2025. Claims 1-3, 5-6 and 11-12 are pending. Claims 4, and 7-10 is/are canceled. A final action on the merits of claims 1-3, 5-6 and 11-12 is as follows.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-6 and 11-12 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Masmanidis et al. (hereinafter ‘Masmanidis’, U.S. PGPub. No. 2009/0177144).
In regards to independent claim 1, Masmanidis discloses an electric wire array (single sided neural probe in Fig. 2A) comprising:
a substrate portion ([0031]: the probe is fabricated by etching a thin silicon wafer); and
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a plurality of electric wire units being disposed on the substrate portion and being stacked on top of each other in a thickness direction ([0035]: metallization forming the electrodes and the interconnects corresponding to annotations ‘1-5’ in Fig. 3 are disposed on the substrate forming two electric wire units; note that each of the interconnects are in the stacked configuration in which the interconnects associated with ‘4’ and ‘5’ are on top of the interconnects associated with ‘1’, ‘2’ and ‘3’ along the thickness direction);
wherein the plurality of electric wire units each comprise:
a plurality of electric wires extending on the substrate portion in a length direction (the plurality of interconnects ‘1’, ‘2’, and ‘3’ extending along the length of the probe); and
an insulating layer covering the plurality of electric wires and having a plurality of electrode holds formed therein so as to expose respective first end portions of the plurality of electric wires ([0036]: a film or layer of insulating material, such as a polymer film, such as parylene, is deposited over metallization layer and exposes only the corresponding electrodes),
wherein the plurality of electric wires each comprise:
a plurality of electric wires being arranged on top of the substrate portion in such a manner to extend in a length direction (interconnects associated with electrodes ‘1’-‘5’ in the annotated Fig. 3);
a plurality of electrode holes being positioned in respective first end portion, respectively of the plurality of electric wires, and being exposed ([0036]: an insulating layer comprising holes for exposing the electrode recording sites ‘1’-‘5’);
wherein the plurality of electric wire units includes a first electric wire unit (see electrodes and its interconnect corresponding to ‘1’, ‘2’ and ‘3’ in the annotated Fig. 3) and a second electric wire unit (see electrodes and its interconnect corresponding to ‘4’ and ‘5’ in the annotated Fig. 3) which are stacked in the thickness direction and which are members of the plurality of electric wire units (interconnects are all stacked in the thickness direction; and the interconnects and its electrodes ‘1’-‘5’ are all members of the plurality of electric wire units as shown in Fig. 3),
wherein the plurality of electric wires of the electric wire array comprises a plurality of first electric wires included in the first electric wire unit (interconnects ‘1’, ‘2’ and ‘3’) and a plurality of second electric wires included in the second electric wire unit (interconnects ‘4’ and ‘5’),
wherein the plurality of electrode holes of the electric wire array comprises a plurality of first electrode holes respectively corresponding to the plurality of first electric wires (the insulating layer comprising holes for exposing the electrodes ‘1’, ‘2’ and ‘3’) and a plurality of second electrode holes respective corresponding to the plurality of second electric wires (the insulating layer comprising holes for exposing the electrodes ‘4’ and ‘5’),
wherein the plurality of electrode holes are arranged in such a manner as to be positioned a distance apart from each other along the length direction (electrodes ‘1’, ‘2’ and ‘3’ and its corresponding holes along the insulation layer are spaced apart in the length direction; same goes for electrodes ‘4’ and ‘5’ and its corresponding holes along the insulation layer) and being sequentially arranged in a successive manner along the thickness direction (electrodes ‘1’ and ‘4’ or ‘2’ and ‘4’ or ‘2’ and ‘5’ or ‘3’ and ‘5’ are sequentially arranged in a successive manner along the thickness direction as shown in Fig. 3 above), and
wherein the thickness direction is a direction from the substrate portion to the electric wire unit (the thickness direction is labeled in Fig. 3 above) and the length direction is a direction vertical to the thickness direction (the length direction is perpendicular to the thickness direction in Fig. 3 above),
wherein the plurality of electric wires are partitioned into a first thickness section having a maximum thickness (Fig. 3A shows the full neural probe in which the proximal end of the plurality of electric wires has the maximum thickness) and a second thickness section other than the first thickness section (the distal end of the neural probe),
wherein a length of the first thickness section is greater than a length of the second thickness section (this is an arbitrary selection in which the distal end of the neural tip is smaller than the intermediate portion and proximal end combined of the neural probe tip),
wherein the plurality of first electric wires comprises:
a first sub-wire having a first sub-electrode hole (the interconnect and electrode hole on the insulating layer associated with electrode ‘2’ reads on the first sub-wire and the first sub-electrode hole, respectively) and a second sub-wire having a second sub-electrode hole (the interconnect and electrode hole on the insulating layer associated with electrode ‘3’ reads on the first sub-wire and the first sub-electrode hole, respectively),
the first sub-wire and the second sub-wire being spaced from each other on the same plane (the interconnects associated with electrode ‘2’ and ‘3’ are on the same substrate or plane) and being overlapped with each other in the length direction (the portion of the interconnects associated with ‘2’ and ‘3’ which overlap in the length direction has been indicated as the dashed line in Fig. 3),
wherein the first sub-electrode hole and the second sub-electroe hole are overlapped with each other in the length direction (the electrodes ‘2’ and ‘3’ and its corresponding holes on the insulating layer are longitudinally aligned),
wherein at least one of the plurality of second electrode holes are disposed (electrode ‘5’ and its corresponding hole on the insulating layer),
wherein at least one of the plurality of second electrode holes are disposed, in the thickness direction, above a region between the first sub-electrode hole and the second sub-electrode hole as viewed along the length direction (the electrode ‘5’ sits above a region between the electrodes ‘2’ and ‘3’ as shown in above Fig. 3).
In regards to claim 2, Masmanidis further discloses wherein an entire thickness of a first end portion of the plurality of electric wires (interconnects at the distal end of the neural probe in Fig. 3) is smaller than an entire thickness of a second end portion of the plurality of electric wires (the distal portion comprising the interconnects is smaller in width than the proximal portion of the interconnects as shown in Fig. 3 of the neural probe) and wherein a section with a maximum width, of the plurality of electric wires is positioned more adjacent to the second end portion than to the first end portion (the examiner notes that the claim does not recite any relationship between the width and the thickness and the examiner assumes that both are interchangeable. As shown in Fig. 3 of the neural probe, the proximal end of the neural probe comprising the interconnects have higher width than the interconnects at the distal end of the neural probe).
In regards to claim 5, Masmanidis further discloses wherein the plurality of first electrode holes overlap in the length direction (electrodes ‘1’, ‘2’ and ‘3’ and its corresponding hole in the insulating layer in Fig. 3 are aligned in the longitudinal direction), and the plurality of second electrode holes overlap in the length direction (electrodes ‘4’ and ‘5’ and its corresponding hole in the insulating layer in Fig. 3 are aligned in the longitudinal direction).
In regards to claim 6, Masmanidis further discloses wherein the plurality of first electric wires are arranged in such a manner as to be positioned a distance apart from each other (the interconnects associated with electrode ‘1’, ‘2’ and ‘3’ are longitudinally and adjacently spaced apart), and the plurality of second electric wires are arranged in such a manner as to be positioned a distance apart from each other (the interconnects associated with electrode ‘4’ and ‘5’ are longitudinally and adjacently spaced apart).
In regards to claim 11, Masmanidis further discloses wherein the plurality of first electric wires further comprise a third sub-wire having a third sub-electrode hole (electrode ‘1’ and its associated interconnect in annotated Fig. 3).
In regards to claim 12, Masmanidis further discloses wherein the first sub-wire and the second sub-wire are arranged on the substrate portion (the interconnect associated with electrodes ‘2’ and ‘3’ are both disposed on the same substrate as explained in [0031]).
Response to Arguments
Applicant's arguments filed on December 7, 2025 is fully acknowledged.
With respect to the rejection of claims 1-3, 6 and 12 under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Nikumb et al. (U.S. PGPub. No. 2008/0119711) has been considered and is persuasive. Therefore, a new ground of rejection has been made above, in view of Masmanidis et al. (hereinafter ‘Masmanidis’, U.S. PGPub. No. 2009/0177144).
Furthermore, Applicant’s argument solely directed towards the secondary reference failure to cure the above-noted deficiency of independent claim 1 have been considered and is persuasive. Therefore, the rejection has been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUNHWA KIM whose telephone number is (571)270-1265. The examiner can normally be reached 9AM-5:30PM.
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/EUN HWA KIM/Primary Examiner, Art Unit 3794 2/9/2026