DETAILED ACTION
Claims 1, 3-12 have been cancelled.
Authorization for Internet Communications
The examiner encourages Applicant to submit an authorization to communicate with the examiner via the Internet by making the following statement (from MPEP 502.03):
“Recognizing that Internet communications are not secure, I hereby authorize the USPTO to communicate with the undersigned and practitioners in accordance with 37 CFR 1.33 and 37 CFR 1.34 concerning any subject matter of this application by video conferencing, instant messaging, or electronic mail. I understand that a copy of these communications will be made of record in the application file.”
Please note that the above statement can only be submitted via Central Fax, Regular postal mail, or EFS Web (PTO/SB/439).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Election/Restrictions
Claims 2, 13-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/17/2024.
Information Disclosure Statement
The listing of references in the amended specification (i.e.Techopedia, see page 2, line 26) is not a proper information disclosure statement. 37 CFR 1.98(b) requires a list of all patents, publications, or other information submitted for consideration by the Office, and MPEP § 609.04(a) states, "the list may not be incorporated into the specification but must be submitted in a separate paper." Therefore, unless the references have been cited by the examiner on form PTO-892, they have not been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the cancellation of Figure 3 as indicated by the replacement specification and remarks pg. 10. See MPEP 608.02(t) Cancellation of Figures. If a drawing figure is canceled, a replacement sheet of drawings must be submitted without the figure (see 37 CFR 1.121(d) ). If the canceled drawing figure was the only drawing on the sheet, then only a marked-up copy of the drawing sheet including an annotation showing that the drawing has been cancelled is required. The marked-up (annotated) copy must be clearly labeled as "Annotated Sheet" and must be presented in the amendment or remarks section of the amendment document which explains the changes to the drawings (see 37 CFR 1.121(d)(1) ). The brief description of the drawings should also be amended to reflect this change.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 20-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 20, and 22 recite “determining, during execution of the code portion, a set of concurrency parameters indicative of a parallel scalability of the code portion on each type of the plurality of processing elements; determining, based on the set of concurrency parameters, an expected change in processing time resulting from varying a number of processing elements of the first type or the second type; dynamically assigning, based on the expected change in processing time, one or more processing elements of the first type or the second type to the code portion, and executing the code portion on the one or more processing elements assigned to the code portion, to reduce total execution time or energy consumption of the computing application.” However, examiner cannot find clear supported for the newly added limitations, especially the concurrency parameters. Applicant should point to support and indicate how each part of the specification supports the claim, or remove the subject matter.
Claims 21, and 23 rejected based on dependency to independent claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 20-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Regarding claim 20 this part of the eligibility analysis evaluates whether the claim falls within any statutory category. MPEP §2106.03. The claim recites method steps; thus, the claim is directed to a process which is one of the statutory categories of invention.
Step 2A Prong 1: This part of the eligibility analysis evaluates whether the claim recites a judicial exception. As explained in MPEP 2106.04(II) and the October 2019 Update, a claim “recites” a judicial exception when the judicial exception is “set forth” or “described” in the claim.
The limitations “determining, during execution of the code portion, a set of concurrency parameters indicative of a parallel scalability of the code portion on each type of the plurality of processing elements; determining, based on the set of concurrency parameters, an expected change in processing time resulting from varying a number of processing elements of the first type or the second type; dynamically assigning, based on the expected change in processing time, one or more processing elements of the first type or the second type to the code portion” as drafted, recite functions that, under its broadest reasonable interpretation, covers functions that could reasonably be performed in the mind, including with the aid of pen and paper, but for the recitation of generic computer components. That is, the limitations as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the functions through observation, evaluation, judgment and/or opinion, or even with the aid of pen and paper. Thus, these limitations recite and fall within the “Mental Processes” grouping of abstract ideas. See MPEP §2106.04(a)(2). Accordingly, claim 1 recites a judicial exception (i.e. an abstract idea).
Step 2A, Prong 2, This part of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception into a practical application of the exception. This evaluation is performed by (a) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (b) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. 2019 PEG Section III(A)(2), 84 Fed. Reg. at 54-55.
In this case, this judicial exception is not integrated into a practical application. The claim recites the following additional elements “a computing application comprising a plurality of code portions, the parallel computing system comprising a plurality of processing elements of different types, including a first type comprising central processing units (CPUs) and a second type comprising graphical processing units (GPUs)” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception. The additional elements fail to meaningfully limit the claim because the element is regarding a generic computing component, thus not practical application under prong 2.
The claim includes additional elements of insignificant extra solution activity “executing the code portion on the one or more processing elements assigned to the code portion, to reduce total execution time or energy consumption of the computing application” and does not require any particular application of the recited “executing” step and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Step 2B, This part of the eligibility analysis evaluates whether the claim as a whole amounts to significantly more than the recited exception, i.e., whether any additional element, or combination of additional elements, adds an inventive concept to the claim. MPEP 2106.05. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “executing the code portion on the one or more processing elements assigned to the code portion, to reduce total execution time or energy consumption of the computing application” amount to no more than mere instructions, or generic computer/computer components to carry out the exception. Mere instructions to apply an exception cannot provide an inventive concept. See MPEP 2106.05(f). Accordingly, the claim does not appear to be patent eligible under 35 USC 101.
Claim 21 is a dependent claim rejected for the same reasons as claim 1. Furthermore, the claims do not add additional elements and does not render the judicial exception as a practical limitation or make a combination that is significantly more than the judicial exception because the step is still drawn to an abstract idea. The limitation is an additional element reciting computer instruction; these additional elements are merely instructions to implement an abstract idea on a computer. MPEP 2106.04(d).
Claim 22, is an independent system claim rejected for the same reasons as claim 20.
Claim 23, corresponds with claim 21 and is rejected for the same reasons as claim 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20, are rejected under 35 U.S.C. 103 as being unpatentable over Papakipos et al. (U.S. PG PUB 2008/0005547) in view of Weissmann et al. (U.S. PG PUB 2012/0185709)..
Regarding claim 20, Papakipos teaches a method of dynamically managing resource allocation (see ¶ [0116] “In some embodiments, the LSI 100 provides functions for performing typical memory allocation operations, such as allocating/de-allocating memory and resizing memory blocks”) of a parallel computing system for processing a computing application (see ¶[0135] “the code segment 24 is executed on a parallel-processing computer system”) comprising a plurality of code portions (see ¶ [0029] “In some embodiments, a processing element includes one or more cores, which may share at least a portion of the same instruction”)`, the parallel computing system comprising a plurality of processing elements of different types, including a first type comprising central processing units (CPUs) and a second type comprising graphical processing units (GPUs) (see ¶ [0057] “The program sequences are then executed on processing elements of the parallel-processing computer system (e.g., a GPU or multi-core CPUs)”), the method comprising:
Papakipos does not expressly disclose, however, Weissmann teaches
for each code portion of the plurality of code portions (see ¶[0016] “In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code.”):
determining, during execution of the code portion, a set of concurrency parameters indicative of a parallel scalability of the code portion on each type of the plurality of processing elements (see ¶[0053] “] So parameter Sn, in one scenario, is introduced to compensate for such scalability. To illustrate, low scalability code will be close to 0 and high scalability will be close to 1, with other levels of scalability ranging therein. Note that the predication of the scalability factor will be done by the hardware)”);
determining, based on the set of concurrency parameters, an expected change in processing time resulting from varying a number of processing elements of the first type or the second type (see ¶ [0033] “As a specific illustrative example, assume that hardware thread 101a and 101b are occupied with software threads. Here, current thread utilization (e.g. a number of cycles active over a period of time) of thread 101a and 101b is determined. And from that current thread utilization, it's estimated/predicted what the new thread utilization (and/or power consumption) would look like after a consolidation of threads to one core, such as core 101. From the new thread utilization and/or power consumption (e.g. power consumption would be less after consolidation), it's determined that there is an opportunity for thread 101b to be migrated to core 101 to save power, while still being able to accommodate the current workload on processor 100.”);
dynamically assigning, based on the expected change in processing time, one or more processing elements of the first type or the second type to the code portion (see ¶ [0033] “Here, current thread utilization (e.g. a number of cycles active over a period of time) of thread 101a and 101b is determined. And from that current thread utilization, it's estimated/predicted what the new thread utilization (and/or power consumption) would look like after a consolidation of threads to one core, such as core 101.”), and
executing the code portion on the one or more processing elements assigned to the code portion, to reduce total execution time or energy consumption of the computing application (see ¶ [0046] “From the current activity metric (e.g. thread utilization), an estimated utilization for consolidation is determined. In other words, it's extrapolated what the current workload (executing threads 550-553 and the utilization/activity they are generating) would look like accumulated on the subset of active cores 570”).
Hence, it would have been obvious to one of ordinary skill in the art to modify the teachings of Papakipos by adapting Weissmann to energy conservation and energy efficiency in specific integrated circuits (see ¶[0013] of Weissmann).
Regarding claim 21, Papakipos does not expressly disclose, however, Weissmann teaches wherein the energy consumption of the computing application is an energy consumption cost or a thermal cooling cost (see ¶ [0033] “From the new thread utilization and/or power consumption (e.g. power consumption would be less after consolidation), it's determined that there is an opportunity for thread 101b to be migrated to core 101 to save power, while still being able to accommodate the current workload on processor 100.”).
Hence, it would have been obvious to one of ordinary skill in the art to modify the teachings of Papakipos by adapting Weissmann to energy conservation and energy efficiency in specific integrated circuits (see ¶[0013] of Weissmann).
Regarding claim 22, an independent system claim corresponding to method claim 20, and is rejected for the same reasons. In addition, Papakipos teaches a plurality of processing elements of different types, including a first type comprising central processing units (CPUs) and a second type comprising graphical processing units (GPUs); and one or more processors interfaced with the plurality of processing elements (see ¶ [0057] “The program sequences are then executed on processing elements of the parallel-processing computer system (e.g., a GPU or multi-core CPUs)”).
Regarding claim 23, is a system claim corresponding with claim 21, and is rejected for the same reasons.
Response to Arguments
Applicant's arguments filed 5/16/2025 have been fully considered but they are not persuasive.
Regarding amended specification, does not appear to be new matter, as the steps listed have been previously mentioned in the original claims and specification.
Regarding amended drawings, are objected to because they do not clearly indicate that Fig 3 has been deleted.
Regarding 112 rejections, applicants argue the rejection is overcome due to the cancellation of claims. Examiner has added new 112 rejections due to the new issues in the new claims.
Regarding 101 rejections, applicants argue that the claims are not directed to a judicial exception but rather integrates into a technological improvement, and, the claims recite significantly more than the abstract idea.
Examiner disagrees. The claimed parallel computing system is a generic computing component and are no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception
The claim includes additional elements “a computing application comprising a plurality of code portions, the parallel computing system comprising a plurality of processing elements of different types, including a first type comprising central processing units (CPUs) and a second type comprising graphical processing units (GPUs)” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception. The additional elements fails to meaningfully limit the claim because the element is regarding a generic computing component, thus not practical application under prong 2. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
The claim includes additional elements “executing the code portion on the one or more processing elements assigned to the code portion, to reduce total execution time or energy consumption of the computing application” and does not require any particular application of the recited “executing” step and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept. Accordingly, the claim does not appear to be patent eligible under 35 USC 101.
Regarding 103 rejections, Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Flautner et al. (U.S. PG PUB 2007/0266385) teaches a performance range of a processor in a data processing apparatus is dynamically varied by recalculating at least one performance-range limit in dependence upon a quality of service value for a give processing task. The processor performance level is varied by selecting from a plurality of possible performance levels of a performance range having the performance-range limit.
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Carina Yun
Patent Examiner
Art Unit 2194
/CARINA YUN/Examiner, Art Unit 2194