Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed 01/07/2026, with respect to claims 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The claims have been rejected under 35 U.S.C. 112(a) and 35 U.S.C. 112(b) due to the added limitations the new grounds of rejection presents subject matter which was not described in the specification in such a way as to reasonably convey in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
No Prior Art Rejection
Under MPEP2163.06 I, amended limitations have been considered, and a 35 U.S.C 112(a) and 112(b) rejection has been made. However, due to the nature of the new matter no prior art rejection has been made.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 11 recite the limitation “for any portion of the active layer of the third transistor whose orthographic projection on the base substrate is covered by the orthographic projection of the gate electrode of the third transistor on the base substrate, the orthographic projection on the base substrate is also covered by the orthographic projection of the respective voltage supply line on the base substrate” in lines 20-24 in claim 1 and lines 26-30 in claim 11. The applicant asserts Fig. 5B paragraph 58 teaches the aforementioned limitation (see for example (Applicant Arguments/Remarks filed 01/07/2026). The Examiner respectfully disagrees, and the aforementioned limitations in claims 1 and 11 were not described in the specification. As shown in Fig. 4A of the specification of the instant application the portion of the gate line GL which acts as the gate electrode containing the a gate protrusion GP, is shown overlapping the active layer ACT3 of the third transistor T3, but not overlapping its respective voltage supply lines Vdd. This contradicts the limitation which requires any portion of the active layer overlapped with the gate line GL to also be overlapped with the voltage supply lines Vdd. Further there is no language within the specification that would suggest the embodiment as shown in Fig. 5B contains a different layout of the device or different dimensions of elements that would suggest the teachings of the device as shown in Fig. 4A are not applicable. Therefore, based on the layout and descriptions provided in the specification , there is no evidence that any portion of the active layer of the third transistor whose orthographic projection on the base substrate is covered by the orthographic projection of the gate electrode of the third transistor on the base substrate has an orthographic projection also covered by the orthographic projection of the respective voltage supply line on the base substrate.
Claims 2-10 and 12-19 are rejected due to depending on claims 1 and 11.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
It is unclear to one skilled in the art what the Applicant regards as the gate electrode in claims 1 and 11 (emphasis added). Claims 1 and 11 recite the limitation “for any portion of the active layer of the third transistor whose orthographic projection on the base substrate is covered by the orthographic projection of the gate electrode of the third transistor on the base substrate, the orthographic projection on the base substrate is also covered by the orthographic projection of the respective voltage supply line on the base substrate” in lines 20-24 in claim 1 and lines 26-30 in claim 11. The Examiner asserts the aforementioned limitations regarding the gate electrode in claims 1 and 11 were not described in the specification. As shown in Fig. 4A of the specification of the instant application the portion of the gate line GL which has been used to represent the gate electrode the gate electrode containing the a gate protrusion GP, is shown overlapping the active layer ACT3 of the third transistor T3, but not overlapping its respective voltage supply lines Vdd. This contradicts the limitation which requires any portion of the active layer overlapped with the gate line GL to also be overlapped with the voltage supply lines Vdd. Further there is nothing within the specification that allows one to distinguish the gate line from the gate electrode.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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