DETAILED ACTION
1. This Office Action is responsive to claims filed for App. 17/613,323 on November 3, 2025. Claims 1-15 are pending. Claim 7-15 have been withdrawn in light of an earlier restriction requirement.
America Invents Act
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ueda
( US 2019/0362673 A1 ) in view of Ueno ( US 2020/0402457 A1 ).
Ueda teaches in Claim 1:
An electronic circuit for thin-film transistor degradation compensation ( [0002] discloses a threshold voltage of a driving transistor which causes luminance unevenness and Figure 2 provides a pixel circuit for compensation ), the circuit comprising:
a driving TFT that supplies current from a driving source to a load [and is connected directly to the load] ( Figure 2, [0063], [0066] discloses a driving transistor M1 for supplying a drive current to the EL element OLED. As for the direct connection, please note the combination below );
a compensation TFT, [configured as a capacitor], that is provided between gate and [source] terminals of the driving TFT ( Figure 2, [0067] discloses a compensation transistor M3 which is between the gate and drain terminal of M1. As for the configuration as a transistor as well as aspects of the source terminal connection, please note the reasoning below. However, initially, a compensation transistor is used to diode-connect the driving transistor M1 and stores charges as a result, hence the “capacitor” aspect );
a storage TFT, configured as a capacitor ( Figure 2, [0063] discloses a capacitor Cst );
a plurality of switching TFTs, configured to act as switches ( Figure 2, [0063] disclose multiple other transistors which act as switches, such as M2, M4 and M5, for example );
two control signals, comprising a row-select signal and a boosting signal ( Figure 2, [0065] discloses a scanning line Sj which can be selected (read as a row-select signal) and [0064] discloses a power source line Vini which applies through M4 and M4 is turned on by Sj-1 (read as a boosting signal) );
an input signal ( Figure 2, [0065] discloses a data voltage charged on data line Di and supplied through writing transistor M2 );
wherein, when the row-select signal is on and the boosting signal is off, the plurality of switches are set such that charge flows from the input signal to the storage TFT ( Figure 2, [0071] discloses the storage capacitor Cst is charged with the data voltage when scanning line Sj is in a select state ) and
when the row-select signal is off and the boosting signal is on, the plurality of switches are set such that charge flows from the storage TFT to the compensation TFT and a gate of the driving TFT, such that the compensation TFT compensates for degradation of the driving TFT ( Figure 2, [0072] discloses after the Cst charging period, initialization transistor M4 turns on (by changing the state of Sj-1) such that Vini is applied to adjust the boost capacitor Cbs ). Figure 8, [0086], [0089] discloses how the compensation transistor M3 is affected by Cbs and how Cbs assists in compensating for the threshold compensation ); but
Ueda does not explicitly teach wherein the compensation transistor is “configured as a capacitor” as well as being “provided between gate and source terminals of the driving TFT”.
However, compensation transistors are well known in the art for storing the parasitic capacitance between the gate and drain of the driving transistor, in this case, M1, essentially designing the transistor as a capacitor. Furthermore, Ueda teaches in [0086] of the concept of a capacitor transistor, such as M8, often implemented as a MOS capacitor. In addition, initially, a compensation transistor is used to diode-connect the driving transistor M1 and stores charges as a result, hence the “capacitor” aspect. Respectfully, one of ordinary skill in the art would realize the compensation transistor is used to store charges and/or allow a charge to be transferred at different times, and could design this has a transistor with a controlling signal or a capacitor with terminals that more traditionally store charges. To further support this notion, Ueda teaches in Figure 15 of replacing M8 with a traditional capacitor Cbs (please compare Figures 2 and 15) and the same functionality is achieved.
To expand on the capacitor aspect and for the connection between a gate and source terminal of the drive transistor (see the [source] limitation above), in the same field of endeavor, pixel circuits, Ueno teaches of a similar setup with drive transistor Tdr and light emitting element OLED, ( Ueno, Figure 1, [0067] ). Specifically, Figure 1 shows a similar drive transistor Tdr (akin to M1 of Ueda) and a similar threshold voltage compensation transistor TD (akin to M3 of Ueda). Ueno teaches in [0068] that the terminals, other than the gate, can be interchanged based on the design of the transistor and this is clearly within ordinary skill in the art. Ueno simply refers to the terminals as a first and second conduction terminal as a result, due to the interchangeability of the terminals. Furthermore, Applicant’s own Figure 1 shows the location of T2 relative to T0. Please note VDD and the OLED element on two different terminals of T0. Respectfully, both Ueda and Ueno teach of a similar layout and this, and in combination with [0068] teaches of this limitation. As a result, one of ordinary skill in the art would realize to be able to have the compensation transistor, configured as a capacitor, to be between the gate and source terminals of the drive transistor.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the transistor as a capacitor, with the motivation that it is a well known design choice and Ueda essentially suggests the substitution of a transistor as a capacitor, interchanging the two types of elements, ( Ueda, [0009] ). Furthermore, Ueda teaches in [0068] of the interchangeability of the source and drain terminals as the transistor can be designed accordingly.
Ueda also does not explicitly teach wherein the driving TFT “is connected directly to the load”.
However, the intervening element, the emission control transistor M6, is well known for being placed in different locations. To emphasize, in the same field of endeavor, pixel circuits, Ueno teaches of a similar setup with drive transistor Tdr and light emitting element OLED, ( Ueno, Figure 1, [0067] ). Notably, the emission control aspects, embodied as a power supply control transistor TA, is placed elsewhere in the circuit, as is true for light emission control transistor TB. As a result, the drive transistor Tdr is directly connected to light emitting element OLED. As combined with Ueda, a simple rearrangement of parts can be made.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the relocation of emission transistors TA and TB, as taught by Ueno, with the motivation that the re-arrangement of the light emission control aspects does not impact functionality, as evidenced by Ueno, [0079] and the mere rearrangement of elements is a design choice issue.
Ueda teaches in Claim 2:
An electronic circuit according to claim 1, wherein the geometry of the driving and compensation TFTs is configured to balance charge components in the emitting phase. ( The term “geometry” is not well defined and please note the broadest reasonable interpretation aspect here. [0067] discloses the compensation transistor M3 is provided between the gate and drain terminal of M1 and this is to be able to compensate for the threshold voltage (read as balancing charge components) )
Ueda teaches in Claim 3:
An electronic circuit according to claim 1, wherein the geometry of the driving and compensation TFTs is configured based on bending forces on the driving and compensation TFTs. ( The term “geometry” is not well defined and please note the broadest reasonable interpretation aspect here. [0067] discloses the compensation transistor M3 is provided between the gate and drain terminal of M1 and this is to be able to compensate for the threshold voltage. Please note threshold compensation occurs because of degradation of the driving transistor (read as bending forces) )
Ueda teaches in Claim 4:
An electronic circuit according to claim 1, wherein the plurality of switching TFTs is configured to isolate the compensation TFT and the gate of the driving TFT from interference of the input signal. ( Figure 2, [0063] disclose the details on several other transistors and how the on/off state of these preceding transistors will isolate/impact M1 and M3, i.e. with these transistors in an off state, M1 and M3 are not conducting )
Ueda teaches in Claim 5:
An electronic circuit according to claim 1, wherein the plurality of switching TFTs is configured to allow acquisition of the input signal without cross-talk to neighboring pixels. ( Figure 2, [0089] discloses the data voltage Vdata is applied on data line Di in accordance with data line capacitor Cdi and this is in part to ensure the proper Vdata level is applied. Respectfully, this concept describes eliminating cross-talk, which is a well known concept and Examiner asserts Official Notice to this being well known )
Ueda teaches in Claim 6:
An electronic circuit according to claim 1, wherein the plurality of switching TFTs comprises 3 TFTs. ( Figure 2, [0063] disclose detail on the multiple other transistors which act as switches, such as M2, M4 and M5, for example )
Response to Arguments
6. Applicant’s arguments considered, but are respectfully not persuasive.
Please note the updated rejection. However, the same grounds of rejection have been maintained, Ueda in light of Ueno. Ueno teaches in [0068] that the terminals of a transistor can be interchanged based on the design of the transistor, as is well known in the art. Furthermore, Applicant’s own Figure 1 shows the location of T2 relative to T0. Please note VDD and the OLED element on two different terminals of T0. Respectfully, both Ueda and Ueno teach of a similar layout and this, and in combination with [0068] teaches of this limitation.
Conclusion
7. All claims are either identical to or patentably indistinct from the claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621